PROPERTIES AND CHARACTERIZATION OF DEEPLY-ETCHED, HIGH-INDEX- CONTRAST RIDGE WAVEGUIDE STRUCTURES. A Dissertation. Submitted to the Graduate School

Transcription

1 PROPERTIES AND CHARACTERIZATION OF DEEPLY-ETCHED, HIGH-INDEX- CONTRAST RIDGE WAVEGUIDE STRUCTURES A Dissertation Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Christopher S. Seibert Douglas C. Hall, Director Graduate Program in Electrical Engineering Notre Dame, Indiana April 2012

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3 PROPERTIES AND CHARACTERIZATION OF DEEPLY-ETCHED, HIGH-INDEX- CONTRAST RIDGE WAVEGUIDE STRUCTURES Abstract By Christopher S. Seibert In order to fill the need for more densely packed photonic integrated circuits (PICs) the higher optical confinement provided by high-index-contrast (HIC) ridge waveguide (RWG) structures is required. In order to realize the high index contrast (Δn) between the semiconductor waveguide core and the dielectric cladding, an oxygenenhanced non-selective wet thermal oxidation (OENSO) process developed at the University of Notre Dame has been applied to the fabrication of GaAs and InP based HIC RWGs. In this work, the unique characteristics of HIC RWGs as well as the interface between the semiconductor and the native oxide have been examined. Utilizing this process, passive single mode HIC RWG devices have been fabricated which exhibit record low propagation losses. Active diode laser devices are fabricated with improved performance over previous results. For the first time these devices have been modified for junction side down bonding to heatsinks and characterized under continuous wave (CW) excitation while mounted to a temperature controlled stage. Finally, the use of the OENSO process has been extended for use in the oxidation of InGaAs lattice matched to InP. As proof of the efficacy of this process for use in this new material system, a novel native-oxide confined quantum cascade laser operating at λ=5.4 μm has been demonstrated.

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5 CONTENTS Figures... vi Tables... xii Acknowledgments... xiii Abbreviations... xiv Chapter 1: Introduction... 1 Chapter 2: Oxidation of III-As Compound Semiconductors Background Thermochemical Evaluation As-Oxide Reduction Oxidation Sealing of GaAs Chapter 3: Laser Structure and Fabrication Laser Structure Passive Waveguide Structure Fabrication Process General Process Flow Double Trench Process Laser ridge protection Incomplete Metallization Oxide pinch-off in narrow ridges Heat-Sinking Chapter 4: Simulation of Ridge Waveguide Properties Effective Index and Single Mode Cutoff Passive Waveguide Structure Active Laser Structure Calculation of Facet Reflectance Comparison of Methods... 31

6 4.2.2 Simple Fresnel Reflectance Complete Fresnel Reflectance FIMMWAVE Simulation Passive Structure Simulation Results Active Structure Simulation Results Conclusions Chapter 5: Determination of RWG Propagation Loss Introduction Design and Fabrication Testing Sources of Error Discrete Defects Imperfect Facets Results for Individual Waveguides Comparison of loss values: individual and linear fit Determination of group index Comparison to the state of the art Future work Conclusions Chapter 6: Characterization of the Electrical Quality of the semiconductor/oxide interface Introduction Time-Resolved Photoluminescence λ=488 nm pump trials λ=650 nm pump trials Conclusions Chapter 7: Active Device Studies Double Trench Devices Introduction Pulsed Testing CW L-I Measurements Temperature Dependent Measurements CW Spectral Characterization Thermal Impedance Measurements Proposed Improvements Teardrop shaped lasers Lasers with etched facets Fabrication Results Fabrication Issues Future Work Conclusions v

7 Chapter 8: Oxidation of InGaAs compounds on InP Background Initial Oxidation and Device Studies Optimization of Oxidation Conditions Future Work Conclusion Chapter 9: Conclusions Appendix A: General Process Flow for HIC RWG Laser Diodes Appendix B: Heatsinking Procedure B.1 Mounting laser die to AlN submount B.2 Mounting AlN submount to c-block References v

8 FIGURES Figure 1.1. Schematic view of a HIC RWG fabricated using the OENSO process Figure 2.1. Oxidation rates of (a) Al 0.3 Ga 0.7 As and (b) Al 0.8 Ga 0.2 As native oxides formed by mixing O 2 with the ultrahigh purity N 2 +H 2 O process gas. From Ref. [5] Figure 2.2. Thermodynamic favorability, Gibbs free energy (ΔG 778 ), of the wet and dry oxidation reactions for the various III-V compound semiconductors Figure 2.3. GaAs sample patterned with photoresist (left), after oxygen plasma treatment and solvent clean (center), after thermal oxidation at 420 C for 90 minutes with 0.2% O 2 /N 2 (right) Figure 3.1. Overview of the generalized process for deep etched non-selectively oxidized RWG laser diodes Figure 3.2. Schematic cross section of a double trench laser diode Figure 3.3. Cross section of the photoresist profile protecting the active ridge of a double trench laser diode before removal of the mesa SiN x layer from Ref. [33] Figure 3.4. Cross-sectional SEM of a double trench laser after non-selective oxidation. Insets show the presence of oxide on the sidewall but not top of the active ridge (left) and oxide on the sidewalls and top of the support mesas (right) Figure 3.5. SEM cross sections of a double trench laser diode overview (A), laser ridge (B), and mesa edge (C) after p-contact metallization Figure 3.6. SEM cross sections of oxide pinch-off in narrow RWG lasers Figure 3.7. Comparison of SEM cross sections of active ridge structure (left) and undoped passive ridge structure (right) Figure 4.1. Simulated effective mode index vs. ridge width for the first two TE (red) and TM (blue) modes of the passive waveguide structure at λ=1550 nm v

9 Figure 4.2. Simulated effective mode index vs. ridge width for the first 4 TE (red) and TM (blue) modes of the active waveguide structure at λ=808 nm Figure 4.3. Heterostructure used by Ikegami and later Herzinger et al. for the calculation of facet reflectance. After Ref. [37] Figure 4.4. Single mode numerical (solid) and multimode finite element (dashed) calculations for facet reflectance vs. waveguide core thickness for structure shown in Figure 4.4. After Ref. [37] Figure 4.5. Comparison of facet reflectance calculated by Herzinger et al. and the complete Fresnel equations (left axis) and confinement factor (right axis) vs. core thickness for the structure in Figure Figure 4.6. Comparison of facet reflectance calculated by Herzinger et al. (solid and dashed) and the results of the FIMMWAVE simulation (points) Figure 4.7. Simulated facet reflectance vs. ridge waveguide width for both the TE and TM polarizations Figure 4.8. Reflectance vs. angle of incidence with air for the TE and TM polarizations Figure 4.9. (Left axis) Facet reflectance vs. the angle of incidence at the facet for both simulated (solid) and Fresnel calculations (dashed). (Right axis): Ridge waveguide width vs. angle of incidence at the facet Figure Simulated facet reflectance vs. ridge waveguide width for the first two modes in both the TE and TM polarizations for the active laser structure at λ=808 nm Figure 5.1. Normalized electric field strength vs. waveguide width for a sample HIC RWG structure with either thermal oxide or deposited dielectric cladding. The dashed line represents an empirical fit (i.e., does not have an explicit functional form) Figure 5.2. Fabricated high-index-contrast ridge waveguides with (A) PECVD deposited SiO 2 and (B) OENSO thermal oxide claddings. Dashed lines indicate the location of the graded index core region Figure 5.3. Sample plot of output power vs. wavelength in the TM mode for a w=2.57 μm OENSO clad ridge waveguide v

10 Figure 5.4. Sample plot of length dependent data and linear fit for the TE mode of a w=2.77 μm OENSO clad ridge waveguide before (red) and after (blue) exclusion of data points from presumed defective waveguides Figure 5.5. Propagation loss coefficient calculated via the linear fitting method vs. ridge waveguide width for all waveguides tested Figure 5.6. Experimentally determined and simulated values for facet reflectance vs. ridge waveguide width Figure 5.7. Normalized transmission vs. phase difference for a 1 cm waveguide sample with R=0.3 for various values of α Figure 5.8. Sample length dependent data showing effect of a discrete defect present in a single waveguide tested at three different lengths Figure 5.9. Simulated facet reflectance vs. facet angle for various TE mode waveguide widths Figure Normalized transmission vs. phase difference for a 1 cm waveguide sample with α=1 cm -1 for various values of facet reflectance Figure Top view of left and right facets of a PECVD clad RWG from the same sample Figure Top view of left and right facets of an OENSO clad RWG from the same sample Figure Cross-sectional SEM of an OENSO waveguide with a crack incurred during cleaving Figure Propagation loss coefficient of the TE polarization vs. RWG width for OENSO and PECVD clad waveguides. Solid points indicate single mode (SM) waveguides, outlined points indicate multimode (MM) waveguides Figure Propagation loss coefficient of the TM polarization vs. RWG width for OENSO and PECVD clad waveguides. Solid points indicate single mode (SM) waveguides, outlined points indicate multimode (MM) waveguides v

11 Figure Comparison of propagation loss coefficient and facet reflectance for both individual results and the linear fit vs. ridge waveguide width for TE polarized OENSO clad waveguides Figure Comparison of propagation loss coefficient and facet reflectance for both individual results and the linear fit vs. ridge waveguide width for TM polarized OENSO clad waveguides Figure Group index vs. RWG width for both TE and TM polarizations. Points represent experimental data, solid lines represent simulated values Figure Propagation loss coefficient vs. index contrast for waveguides reported in the literature. Note: Log scale on both axes Figure Propagation loss coefficient vs. index contrast for HIC waveguides reported in the literature. Note: Log scale on y-axis Figure 6.1. Carrier lifetime vs. distance from ridge edge for an ICP etched ridge. Pump at λ=488 nm Figure 6.2. Carrier lifetime across a bulk sample after removal us the cap and upper cladding layers. X (red) and Y (blue) sweeps across the center of the sample in that dimension. Pump at λ=488 nm. Zero in X and Y correlates to the left and bottom edges of the sample, respectively Figure 6.3. Ratio of carrier lifetime at an etched edge to carrier lifetime in the bulk immediately adjacent to the edge for as etched (red) and etched and oxidized (blue) samples Figure 6.4. Carrier lifetime across a bulk sample after removal of the GaAs cap. Pump at λ=650 nm. Zero in X corresponds to the left edge of the sample Figure 6.5. Ratio of carrier lifetime at an edge to carrier lifetime in the bulk immediately adjacent to the edge for as etched (or cleaved) and etched (or cleaved) and oxidized. Samples prepared with both RIE (red) and ICP-RIE (blue) etching Figure 7.1. Sample L-I curve for a L=790 μm, w=6.75 μm laser tested p-side down under pulsed (2% duty cycle) excitation Figure 7.2. Sample L-I curve for a L=790 μm, w=6.75 μm laser tested p-side down under pulsed (2% and 50% duty cycle) as well as CW excitation

12 Figure 7.3. CW L-I curves for a w=4.75 μm, L=0.85 mm device for various TEC temperatures Figure 7.4.Threshold current density vs. TEC temperature for a w=4.75 μm L=0.85 mm device with a characteristic temperature of T 0 =179.4 C Figure 7.5. Output spectra for a w=6.75 μm wide device at CW drive currents of I=1.9, 2.8, and 4.2 times threshold current at 15 C Figure 7.6. Output spectra for various TEC temperatures for a w=4.75 μm, L=1.25 mm device with a CW drive current of 40 ma (just above threshold) Figure 7.7. Peak wavelength vs. TEC temperature for a w=4.75 μm, L=1.25 mm under pulsed (5% duty cycle) and CW excitation Figure 7.8. Optical micrograph of an oxidized (450 C, 30 min, 0.4% O 2 /N 2 ) double trench laser structure Figure 7.9. Teardrop geometry utilizing a matched bend design. From Ref.[12] Figure L-I curves for a teardrop shaped laser utilizing the matched bend design with a threshold of I th =43 ma and a slope efficiency R d of W/A. From Ref. [12] Figure SEM image of the metalized facet of a w=2.9 µm active core waveguide. 102 Figure L-I of a typical w=2.9 µm device tested pulsed and cw. Inset shows a linear spectrum of a similar device with a peak wavelength of nm and a SMSR of ~20 db from Ref. [92] Figure Top view SEM images of a 4 µm and 8 µm wide etched facets at and 5000X respectively Figure Cross section view of oxide thickness on the etched facet. Solid and dashed lines represent the location of the graded region and quantum well respectively Figure Calculated reflectance value of the etched facet versus oxide thickness for 100% and 91.7% reflecting metal mirrors x

13 Figure 8.1. SEM cross section of an InP QCL heterostructure oxidation test sample after non-selective oxidation at 500 C for 4 hours Figure 8.2. SEM cross section of native oxide confined laser ridge before metallization. Inset shows thickness of oxide formed in the field between devices Figure 8.3. P-I-V characteristics of native oxide confined QCL device. Inset shows a representative linear spectrum Figure 8.4. Optical microscope images of early InGaAs thermal oxides. Right: 4 hr oxidation, 525 C, 0.7% added O 2, no cover piece, Left: 6 hr oxidation, 500 C, 0.7% added O 2, InGaAs cover piece Figure 8.5. InGaAs sample with silicon shim in direct contact with sample surface during oxidation, indicated by dotted lines Figure 8.6. InGaAs sample oxidized with (upper right, t=350 nm) and without (lower left, t=200 nm) Si cover piece in direct contact with the sample Figure 8.7. Leakage current density vs. applied bias voltage. Inset: Optical image of capacitor fabricated on InGaAs oxide Figure 8.8. Oxide thickness vs. relative O 2 content for a 2 hour long oxidation at various process temperatures. Without added O 2 no oxide growth is observed Figure 8.9. Oxide thickness vs. time for 475 C (0.5% O 2 /N 2 ) and 510 C (0.7% O 2 /N 2 ). After an initial time delay before the onset of growth, linear oxidation rates of 34 nm/hr and 120 nm/hr, respectively, are observed, indicating a reaction limited process Figure SEM image of shallow etched QCL ridge fabricated using a two step wet/dry etch recipe xi

14 TABLES Table 5.1 Lowest Propagation Loss Coefficient Values Table 5.2 Average Group Index Values Table 5.3 Low Loss, Single Mode, Waveguides in the Literature xii

15 ACKNOWLEDGMENTS I would like to acknowledge parents Fred and Carla Seibert, my brother Jeremy and sister-in-law Lily, and my grandmother, and my friends Brian and Meghan Flaherty for all of their love and support over the years, without which I would never had made it this far. I would also like to thank my beloved Jessica for bringing so much happiness into my life. For his friendship and guidance over the years, as well as his understanding that tents sometimes leak, I must also thank my advisor Doug Hall. Thanks also go to all of my friends and fellow graduate students, especially Kevin, Hubert, Vince, Glenn, Ralf, Erin, Jason, Ken, Wanging, and Jinyang for their advice and support along the way, both academic and otherwise. I would also like to thank Vladimir Protasenko and Alexander Mintariov for the use of their time resolved testing systems. And finally, I have to thank the lab staff: Mike Thomas, Mark Richmond, Keith Darr, and Mike Young for keeping the lab up and running and for fixing everything I have broken over the years. xiii

16 ABBREVIATIONS PIC... Photonic integrated circuit OENSO... Oxygen-enhanced non-selective oxidation HIC... High index contrast RWG... Ridge waveguide GRINSCH... Graded index spate confinement heterostructure PECVD... Plasma enhanced chemical vapor deposition RIE... Reactive ion etching ICP... Inductively coupled plasma LER... Line edge roughness SOI... Silicon-on-insulator SEM... Scanning electron microscope PL... Photoluminescence TRPL... Time resolved photoluminescence TCSPC... Time correlated single photon counting CW... Continuous wave SMSR... Side mode suppression ratio VCSEL... Vertical cavity surface emitting laser AR... Anti-reflective xiv

17 HR... Highly-reflective IBE... Ion beam etching CAIBE... Chemically assisted ion beam etching VASE... Variable angle spectroscopic ellipsometry TIR...Total internal reflection xv

18 CHAPTER 1: INTRODUCTION The integration of photonics in our daily lives in the form of light emitting semiconductor devices has become amazingly prevalent. Nearly all of our electronic devices have some sort of light emitter in them, even the lowly LED used as a power indicator. Screens displaying information read off of a disc by a laser or transmitted over the internet via a fiber-optic network are now commonplace. Advancements in these technologies have been driven by a wide range of factors: the desire for more energy efficient lighting has led to the development of white light emitting LED packages to replace the resistance heaters that also give off light [1] (also known as incandescent light bulbs); the need to fit more data onto a disk helped spur the development of the blue laser (most notably for BluRay devices); and the development of an efficient semiconductor laser which emits green light with the goal of creating RGB (red-greenblue) projectors small enough to fit into the mobile devices of tomorrow. Unquestionably, one of the biggest motivating factors in the development of optoelectronic devices has been the seemingly unquenchable thirst for data in today s technology driven society. A recent study released by Cisco Systems predicts that total yearly internet traffic will reach the zetabyte (10 21 bytes/year) threshold by the year 2015 [2]. Much of that data is handled by fiber optic communication networks, utilizing their 1

19 ability to send multiple signals over a single optical fiber via wavelength division multiplexing (WDM). But to keep up with the pace of technology, such devices must achieve higher data transfer rates, leading to the use of photonic integrated circuits (PICs), which ideally place all of the active and passive components needed for the generation, routing, and detection of light onto a single chip. As with electrical components and the inevitable push of Moore s law toward smaller dimensions, there is also a strong desire to shrink the size of optical components. Due to the high cost to grow, process, and package the semiconductor materials used for photonic circuits, as well as the fact that light is already propagating at the fundamental speed limit in the chosen material; size is both speed and money for PICs. The key to reducing the size of the overall chip is to increase the optical confinement of the light in the waveguides which route signals around the chip by increasing the difference, or contrast, in refractive index between the waveguide core and cladding, Δn=n core -n cladding. A drastic decrease in the bending radius of light from several millimeters [3] down to only a few microns [4] has been enabled through the introduction of an oxygen-enhanced non-selective oxidation (OENSO) process at the University of Notre Dame which allows for the thermal oxidation of low aluminum content (x<0.6) Al x Ga 1-x As [5] and the fabrication of waveguides with a much higher index contrast (Δn ~1.5) than that of conventional low index structures (Δn <0.1). This process, which adds trace amounts of O 2 (<0.7%) relative to a N 2 water vapor carrier gas, has also shown the capability of oxidizing aluminum free GaAs [6], InGaAsN and GaAsP [7], and even InGaAs latticed matched to InP [8]. A cross sectional view of the high index contrast (HIC) ridge waveguide (RWG) fabricated using this process is shown in Figure

20 Figure 1.1. Schematic view of a HIC RWG fabricated using the OENSO process. The primary objective of this work is to further explore and characterize HIC RWG structures fabricated using the OENSO process. To this point in the development of this novel process, its efficacy has been shown for creating active devices with performance better than traditional weak-index guided structures or HIC structures with a deposited dielectric layer [4, 7, 9]. Work has also been completed to apply this process to curved waveguides of various geometries including half racetrack lasers [4], ring resonators [10], and teardrop shaped lasers [11, 12]. It has also been shown that as the waveguide width is narrowed, the loss caused by the transition from straight to curved sections can be minimized, allowing for smaller bending radii [10, 13]. The obvious future extension of this work is to explore the integration of these laser devices into PICs, but before this can be completed a greater understanding of the 3

21 basic HIC RWG device must be achieved. One cannot make a curved resonator which is coupled into a PIC without understanding many different aspects, including: the characteristics of a straight ridge, the waveguide s performance when curved in a tight bend, and the optimum design for the output coupler. It follows that if the performance of a simple straight HIC RWG is not completely understood then it is very difficult to use that structure to design more complicated devices. For this reason, one goal of this work to more fully understand and characterize straight diode lasers fabricated with the OENSO process. To complete this goal, several approaches have been taken. The unique properties of HIC RWG structures are first simulated (Chapter 4). Next, the quality of the semiconductor/oxide interface formed by the OENSO process is examined though both waveguide loss measurements (Chapter 5) and time resolved photoluminescence studies (Chapter 6). Though various process improvements (Chapter 3), the ability to mount HIC RWG lasers fabricated via the OENSO process p-side down to heatsinks has been developed, and this procedure has enabled the spectral and thermal properties of straight lasers (Chapter 7) to be characterized fully under continuous wave (CW) operation for the first time since the discovery of the OENSO process. Unique lasers have also been demonstrated (Chapter 7) which are more suitable for integration into PICs, namely both teardrop-shaped resonators and lasers with etched and oxidized rear facets. Finally, the extension of the oxygen-enhanced oxidation process to InGaAs lattice matched to InP, an important material system for telecommunications applications, is demonstrated (Chapter 8). The efficacy of this oxide for use in optoelectronic applications is demonstrated through the fabrication of a novel native oxide confined quantum cascade laser (QCL) 4

22 operating at λ=5.4 μm (Chapter 8). Because of the diverse nature of this work, relevant background information, conclusions, and suggestions for future research will be made within each chapter where applicable, with a brief summary of this work presented in the final chapter. 5

23 CHAPTER 2: OXIDATION OF III-AS COMPOUND SEMICONDUCTORS 2.1 Background For many years researchers have explored methods for forming a high quality native oxide, similar to thermal SiO 2 on Si, on various compound semiconductors. These investigations into the growth of oxides onto the compounds of interest in this work (GaAs and InGaAs) include anodic [14, 15], plasma [16, 17], and liquid phase oxidation [18, 19]. Most notably, thermal oxides grown via the selective oxidation of high aluminum content Al x Ga 1-x As (x>0.80), first discovered in the 1990 s [20], have found widespread use in modern devices. This oxidation process is used to selectively form buried oxides, most commonly for current apertures in vertical cavity surface emitting lasers (VCSELs) [21, 22]. More recently a variation of wet thermal oxidation we call oxygen-enhanced nonselective oxidation (OENSO) utilized in this work has enabled the thermal oxidation of low aluminum content (x<0.6) Al x Ga 1-x As [5], and the aluminum free semiconductors InGaAsN, GaAsP, and GaAs [6, 7]. The OENSO process involves adding precisely controlled trace amounts (<1%) of dry oxygen to the traditional N 2 carrier gas and water vapor used during wet oxidation, and significantly enhances the oxidation rate of materials which are traditionally difficult to thermally oxidize. Figure 2.1, taken from 6

24 Ref. [5], shows the oxidation rates of Al 0.3 Ga 0.7 As and Al 0.8 Ga 0.2 As for added oxygen contents ranging from 0 to 1%. This plot reveals that when no oxygen is added to the process gas the oxidation rate of the Al 0.8 Ga 0.2 As is more than 17 times the oxidation rate of Al 0.3 Ga 0.7 As. However, when just 0.74% (7400 ppm) of oxygen is added to the N 2 carrier gas this selectivity in the oxidation rates is reduced to ~2.4 times, indicating the potential of this process for use in oxidizing low aluminum content III-As materials. Figure 2.1. Oxidation rates of (a) Al 0.3 Ga 0.7 As and (b) Al 0.8 Ga 0.2 As native oxides formed by mixing O 2 with the ultrahigh purity N 2 +H 2 O process gas. From Ref. [5]. 2.2 Thermochemical Evaluation To explain the enhancement of the oxidation rate achieved through the controlled addition of oxygen one must look at the thermodynamic favorability of the reactions 7

25 involved in the traditional wet and dry thermal oxidation processes, as well as the role of hydrogen during oxidation. This analysis was first presented for the selective oxidation of high aluminum content (x>0.80) Al x Ga 1-x As [23], and later for the nonselective oxidation of low aluminum content (x>0.30) Al x Ga 1-x As [5]. More recently this analysis was extended to InGaAs/AlInAs lattice matched to InP [8]. The following reactions are for the dry and wet oxidation of AlAs, GaAs, and InAs. Similar oxidation reactions involving the formation of As 2 O 5 (s), which can be found in Refs. [5, 23], are excluded here for brevity. The Gibbs Free Energy of each reaction is calculated at 500 C (773 K). Dry Reactions: 2AlAs(s)+3O 2 (g) Al 2 O 3 (s)+as 2 O 3 (l) Eq. 2-1 ΔG 773 =-1692 kj/mol 2GaAs(s)+3O 2 (g) Ga 2 O 3 (s)+as 2 O 3 (l) Eq. 2-2 ΔG 773 =-1211 kj/mol 2InAs(s)+3O 2 (g) In 2 O 3 (s)+as 2 O 3 (l) Eq. 2-3 ΔG 773 =-1080 kj/mol Wet Reactions: 2AlAs(s)+6H 2 O(g) Al 2 O 3 (s)+as 2 O 3 (l)+6h 2 (g) Eq. 2-4 ΔG 773 =-462 kj/mol 2GaAs(s)+6H 2 O(g) Ga 2 O 3 (s)+as 2 O 3 (l)+6h 2 (g) Eq

26 ΔG 773 =+19 kj/mol 2InAs(s)+6H 2 O(g) In 2 O 3 (s)+as 2 O 3 (l)+6h 2 (g) Eq. 2-6 ΔG 773 =+150 kj/mol Figure 3.1 shows the Gibbs free energy, ΔG 773, for all of the above reactions at 773 K (500 C). Although the optimum oxidation processes occur at varied temperatures between 420 C and 525 C depending on the compound to be oxidized, these values are representative of the overall trends, as they change very little over this temperature range. The thermodynamic favorability, which increases as the Gibbs free energy becomes more negative, is calculated for each of the three binary endpoint compounds using the material parameters and theory outlined in Ref. [24] and physical constants take from Ref [24]. Due to a lack of thermochemical data for the specific ternary alloys used in this work, the solid and dashed lines simply represent a linear interpolation to suggest where ΔG 773 might lie for various ternary alloy compositions. 9

27 Figure 2.2. Thermodynamic favorability, Gibbs free energy (ΔG 778 ), of the wet and dry oxidation reactions for the various III-V compound semiconductors. 2.3 As-Oxide Reduction From the previous figure we can clearly see that in all cases the reactions involving dry O 2 are more energetically favorable than the wet reactions. This explains the enhancement of oxidation rates by adding dry oxygen, but does not explain the decrease in oxidation rate seen for the non-selective oxidation of AlGaAs [5] and GaAs [6] above certain O 2 concentrations. The latter can be explained by examining the role of hydrogen in removing As from the oxide matrix [23]. As the thermal oxide grows, the H 2 released by the wet oxidation reaction and the As-oxide (an intermediate reaction byproduct) react, through the reaction shown below to create H 2 O and volatile As, which can then diffuse out of the oxide: 10

28 As 2 O 3 (l)+3h 2 (g) 2As+3H 2 O(g) Eq. 2-7 ΔG 773 =-132 kj/mol When the dry and wet reactions are not properly balanced a dense arsenic oxide forms as the result of the more favorable dry oxidation reaction. This dense oxide blocks the diffusion of oxidants to the reaction site and results in the growth of only a thin terminal oxide, explaining the precipitous drop in the oxidation rate of AlGaAs for added oxygen contents above 0.75%, as seen in Figure 2.1. This removal of the As-oxide is very important to not only the oxidation rate of the material, as seen in Figure 2.1, but also to the quality of the electrical interface. It is know that As 2 O 3 is unstable and can react with GaAs to form Ga 2 O 3 and free As, even at low temperatures [14, 25]. If this As remains at the interface, it can act as a defect state and possibly cause Fermi-level pinning [26, 27]. Thus, the ability of the OENSO process to remove this As 2 O 3 from the interface is an important aspect which allows the process to generate an interface of sufficient quality for use in optoelectronic devices. 2.4 Oxidation Sealing of GaAs The effect of As removal on the final oxidation thickness is further highlighted by a unique oxidation sealing process developed in this work. This process utilizes oxygen plasma to form a dense layer of oxide on the sample surface, blocking the further oxidation of the underlying material. The use of oxygen plasma for the oxidation of compound semiconductors has been reported elsewhere [16, 17], but in this work it was uniquely applied to form an oxidation mask for GaAs. 11

29 Figure 2.3. GaAs sample patterned with photoresist (left), after oxygen plasma treatment and solvent clean (center), after thermal oxidation at 420 C for 90 minutes with 0.2% O 2 /N 2 (right). Figure 2.3 details this oxidation sealing process. The sample is first patterned with photoresist, exposing the portion of the sample to be sealed from further oxidation (left). The sample is then placed in an O 2 plasma (20 sccm O 2, 120 mt, 1500 W, 5 min), forming a dense layer oxide layer in the exposed area. After stripping away the photoresist no visible change is evident on the sample s surface (center). After a standard oxidation the effect of the sealing is clearly seen by the growth of oxide on the lower right portion of the sample (right). Additionally, we see that the portion of the sample exposed to the plasma did not oxidize. 12

30 CHAPTER 3: LASER STRUCTURE AND FABRICATION 3.1 Laser Structure The epitaxial heterostructure used for the work in this proposal is the commercially available EpiWorks λ=808 nm EpiLaser structure. This graded index separate confinement heterostructure (GRINSCH) has already been shown to be capable of producing highly efficient (η ext =86%) HIC RWG lasers [9]. The structure is designed to closely match that of Ref. [28]. This heterostructure has a 200 nm thick heavily doped (N A =3x10 19 ) p+ GaAs cap layer, a 1.5 µm thick Al 0.6 Ga 0.4 As p-type (N A =1x10 18 ) upper waveguide cladding layer, an 800 nm thick undoped waveguide core region linearly graded from Al 0.6 Ga 0.4 As at the upper and lower cladding to Al 0.35 Ga 0.65 As at the center. At the center of this graded region is a single 7 nm thick strained InAlGaAs quantum well (λ=808 nm). The lower cladding consists of a 1.5 µm thick n-type (N D =1x10 18 ) Al 0.6 Ga 0.4 As layer which is then graded over a 200 nm section to the n-type GaAs substrate. The doping concentration of the p-type and n-type layers is gradually reduced and drops below 1x10 16 cm -3 at the graded core region. 13

31 3.2 Passive Waveguide Structure The epitaxial heterostructure used for passive waveguides is similar to the structure outlined in Section 3.1. To optimize the structure for passive waveguiding at λ=1550 nm it contains no quantum well and a thicker (4 μm) lower cladding to reduce substrate leakage. To reduce free carrier absorption the structure is unintentionally doped p-type with an acceptor (C) concentration which is estimated from other samples to be approximately 1x10 16 cm -3. Samples used in this work were taken from the same epitaxial wafer as used in Ref. [29], grown via MOCVD at Sarnoff Corporation in Princeton, New Jersey. 3.3 Fabrication Process The following section outlines the general steps involved in the fabrication of HIC RWG laser diodes using the oxygen-enhanced non-selective wet thermal oxidation process. Depending on the type of device being made and the type of lithography used, some alterations to the process are made, which will be outlined in later sections. 3.4 General Process Flow A general outline of the process flow can be seen in Figure 3.1, with details of the complete process found in Appendix A. The basic process is to first deposit a ~200 nm thick layer of SiN x, using plasma-enhanced chemical vapor deposition (PECVD), over the entire sample. This layer acts as both an etch mask as well as an oxidation mask during processing. Using either optical or electron-beam (e-beam) lithography the 14

32 sample is patterned, as shown in part A of Figure 3.1. The resist pattern is used as an etch mask for the SiN x layer during CF 4 :O 2 plasma etching, and is then removed. The remaining SiN x is then used as an etch mask for either reactive ion etching (RIE) or inductively coupled (ICP) reactive ion etching, using a BCl 3 :Cl 2 plasma to deeply etch the heterostructure below the laser active region and into the lower cladding. These steps are shown in part B of Figure 3.1. Figure 3.1. Overview of the generalized process for deep etched nonselectively oxidized RWG laser diodes. After etching, the sample is placed in the III-V wet oxidation furnace and nonselectively oxidized at 450 C with between 0.1% and 0.7% oxygen added relative to the dry nitrogen carrier gas, which is bubbled through de-ionized water heated to 95 C to produce water vapor. Details of the oxidation system can be found in Ref. [30]. The SiN x mask prevents oxidation of the top GaAs cap layer of the structure while this 15

33 process grows an insulating native oxide on the sidewalls of the ridges as well as in the field between devices, as shown in part C of Figure 3.1. The p+ GaAs cap layer is then exposed by removing the remaining SiN x mask, which is selectively removed in a CF 4 :O 2 plasma. Due to the selectivity of the etch rate between the SiN x and the native oxide no lithography step is needed before this etch. On laser devices intended for bar testing an additional lithography step is then completed which will electrically isolate each device after the evaporation and lift-off a 20 µm wide section of the p-side metal contact in the field between the ridges. Devices which are to be diced and tested as individual die do not require this step. The Ti/Au p- side contact is then deposited on the top-side of the sample utilizing a double angle evaporation which coats the sidewalls of the ridges. The sidewalls are coated so that electrical contact can be made anywhere on the top surface of the sample, not only to the top of the laser ridge, as well as to enhance heat removal from the laser active region. After lift-off of the isolation stripes, the backside of the sample (substrate) is lapped and polished to a final thickness of ~100 µm and a AuGe/Ni/Au ohmic contact is deposited on the backside of the sample via thermal evaporation. This contact consists of a Au 0.88 Ge 0.22 layer followed by a layer of Ni in a 6:1 ratio (360 Å:60 Å) and then a ~100 nm thick layer of Au. After annealing the devices at 410 C for 7 seconds to alloy the contact the sample can be cleaved into bars (forming the laser resonator mirrors) for testing. Finished devices have a cross section as show in Part D of Figure

34 3.5 Double Trench Process To achieve the greatest effect from heat sinking a diode laser it is desirable to bond the device with the active region as close to the heat sink as possible, or p-side down. When mounting a device with a very narrow ridge p-side down some type of support structure is desired to stabilize and reduce the mechanical stress on the ridge. In order to add support mesas to either side of the ridge, as shown in Figure 3.2, some changes must be made to the fabrication process reported by other in Refs [31, 32]. The important aspect of the fabrication is to ensure that the support mesas are electrically isolated so that there is not a current leakage path. This can be done by either leaving the SiN x oxidation mask on the mesa ridges or by removing this mask before oxidation and allowing the top of the support mesas to oxidize at the same time as the ridge sidewalls. The oxidation of the GaAs cap on top of the support mesas used by the second approach is a novel feature of the OENSO process which is not achievable through traditional selective oxidation [6]. Either of these options requires additional lithography and etching steps. For this work, the second approach has been chosen in order to avoid any adhesion or de-lamination issues arising from oxidizing underneath the SiN x layer. 17

35 Figure 3.2. Schematic cross section of a double trench laser diode Laser ridge protection Initial attempts to fabricate the double trench design revealed the need for an alteration to the original process. In these test runs, issues arose because the Shipley 1813 photoresist used to mask the active ridge during the removal of the SiN x mask from the top of the support mesas did not uniformly cover the top of the ridge. Due to this non-uniform coverage of the ~1.5 µm thick resist on the top of the ~3 µm tall ridge some of the SiN x oxidation mask was inadvertently removed prior to oxidation. This led to partial oxidation of the top of the laser ridge, making it difficult to make the p-side electrical contact on top of the ridge. To correct for this it was determined that a thicker photoresist must be used to protect the ridge during the additional etching step which removes the nitride from the top of the support mesas. Work done in collaboration with Mr. William Hank Dettlaff as part of his senior design project during the school year addressed this issue. A photoresist with a nominal thickness of 7-10 µm, Rohm Haas SPR , was chosen for this step [33]. 18

36 Figure 3.3. Cross section of the photoresist profile protecting the active ridge of a double trench laser diode before removal of the mesa SiN x layer from Ref. [33]. Figure 3.3 shows the photoresist profile of the pattern used to protect the active ridge during nitride removal on the support mesas. This figure shows a ~25 µm wide stripe of photoresist completely covering a 6 µm wide laser ridge (which is the widest ridge on the current double trench mask). While there is obvious misalignment in the protective stripe, the nitride mask on top of the ridge is still fully protected. Figure 3.4 shows a sample after removal of the SiN x mask on the support mesas and the subsequent oxidation. The insets of this figure clearly show that the support mesas and the sidewalls of the active ridge are completely isolated by oxide while the current path at the top of the active ridge remains open. This oxide effectively provides an isolation layer to keep current from leaking into the support mesas, solving the issues seen in previous fabrication runs. 19

37 Figure 3.4. Cross-sectional SEM of a double trench laser after nonselective oxidation. Insets show the presence of oxide on the sidewall but not top of the active ridge (left) and oxide on the sidewalls and top of the support mesas (right) Incomplete Metallization A second issue arose during initial attempts to fabricate lasers using the double trench process. Due to the shadowing effect of the laser ridge and mesa during the two angled evaporations for the p-contact metal, gaps in the metal were seen next to the laser ridge and support mesa respectively. This issue is highlighted in cross sectional SEM images of Figure 3.5. Figure 3.5 A shows a cross section of a metalized device. Close inspection reveals breaks in the metal around the laser ridge itself (Figure 3.5 B) and beside one of the support mesas (Figure 3.5 C). The gaps in the metal layer are highlighted by the yellow circles. The ideal solution to this problem would be to perform a sputter deposition of the p-contact metal. However, at the time of writing this capability was not yet installed in the Notre Dame fabrication facility. For this reason a simple 45 stage was constructed for use in any of the electron-beam evaporators. 20

38 Performing the deposition at a 45 angle from each side of the sample results in a fairly uniform and conformal metal contact across the entire structure. Figure 3.5. SEM cross sections of a double trench laser diode overview (A), laser ridge (B), and mesa edge (C) after p-contact metallization. 3.6 Oxide pinch-off in narrow ridges During attempts to fabricate ridge waveguides at or near the single mode cutoff width of w~0.9 μm at λ=808 nm, a new fabrication issue was discovered that is unique to deeply etched RWG lasers fabricated with the OENSO process. This is the phenomenon of the pinching off of the current path into the active region by the oxide, or so called oxide pinch-off, is illustrated in the SEM cross sections of narrow ridge lasers of Figure 3.6. On the left of this figure we see a w=1.36 μm wide laser diode after oxidation. The enhanced oxidation at the top of the upper cladding has narrowed the current path to 0.6 μm, less than half of the active width of the device. As the active 21

39 width of devices shrinks, this narrowing of the current path will increase the device resistance as well as heating effects, degrading the overall performance of the device. In the extreme case, shown on the right hand side of Figure 3.6, this effect will completely pinch off the current path into the device. This will electrically isolate the device from the p-side metal contact made to the top of the ridge, rendering the laser in-operable. Figure 3.6. SEM cross sections of oxide pinch-off in narrow RWG lasers. A related, but somewhat more nuanced area of enhanced oxidation rate can also be seen at the bottom of each laser ridge in Figure 3.6. Here we can see a slight increase in the oxide thickness compared to the center of the active region, although not as large as the disparity in the thickness at the upper cladding. To explain each of these effects, one must consider the doping profile of the structure described in Section 3.1. The areas where the enhanced oxidation rates occur correspond to the more heavily doped areas of the structure. This also explains why the enhancement effect is more noticeable at the top of the ridge. The etch is typically stopped ~2.5 to 3 μm into the structure, before the n- 22

40 type doping has reached its maximum concentration. Were the etch to go deeper into the structure, it is possible that this effect may be just as prominent in the n-type lower cladding as it is in the p-type upper cladding. The relation of this effect to doping concentration is further demonstrated when oxidized ridges from both the active (doped) structure and passive waveguiding (undoped) structure are compared side by side. Figure 3.7 shows these two structures with the active ridge on the left and passive ridge on the right. Both samples were oxidized with 0.4 % added O 2 relative to the N 2 carrier gas at 450 C for 30 minutes. We can clearly see the enhancement of the oxidation rate in the doped structure on the left hand side, while no such effect is present in the undoped structure on the right. Figure 3.7. Comparison of SEM cross sections of active ridge structure (left) and un-doped passive ridge structure (right). By reducing the thickness of the oxide in the active region the thickness in the heavily doped region will also decrease. However, in order to ensure that the intensity of the electric field in the oxide is as low as possible at the outer oxide/metal interface to 23

41 prevent absorption losses in the metal, a thicker oxide is preferred. The current oxide thickness used for active devices is 5 to 6 times the 1/e penetration depth of the electric field in the native oxide (~54 nm), or ~300 nm oxide in the active region. Several attempts at using some sort of oxidation sealing technique to ameliorate the effects of the enhanced oxidation rate have been attempted, with none presenting promising results. For this reason, if a future project aims to fabricate narrow ridge lasers, at w 1.5 μm, it is suggested that a new epitaxial structure be designed, similar to the GRINSCH structure used in this work, but with a different doping profile and/or aluminum composition profile in the upper and lower cladding layers. This structure should be optimized to minimize the excess oxide thickness now occurring in the regions with an enhanced oxidation rate. 3.7 Heat-Sinking Initial work on the heat sinking procedure was done in collaboration with Mr. William Hank Dettlaff as part of his senior design project during the school year [33]. With this initial work as a starting point a procedure for bonding completed laser devices to AlN submounts coated with AuSn (80%:20%) was developed. This procedure, which is outlined in detail in Appendix B, will be summarized here. Bonding is completed using a WestBond model 7372E eutectic die bonder. The AuSn coated AlN submount is heated to 310 C (above the eutectic point of 278 C) under a N 2 ambient to prevent oxidation during bonding. The laser die to be mounted is also heated by placing it on the work holder with the submount in order to reduce thermal stress. After the 24

42 desired temperature is reached, the die is placed onto the submount using a vacuum pickup tool on the bonder. Once placed on the submount a scrub cycle (30 cycles, 2 mil scrub) is completed. After the completion of the scrub cycle the system is cooled to below 100 C and the submount is removed. Next the AlN submount is then mounted to a gold plated copper c-block using indium solder. This is also completed using the heated work holder of the WestBond die bonder. A preform of indium foil approximately the size of the submount is placed on the c-block and is then heated to 200 C (well above indium s melting point of 157 C) and the submount is placed on the c-block. A separate probe is used to hold the submount in place as the work holder is cooled back down to room temperature. At this point, the c-block is removed from the work holder and the heat sinking procedure is complete. Some issues with the reliability of the bonding to the submounts were encountered during testing, with the laser die releasing from the submount during subsequent handling. This is believed to be caused in part by known issues in the quality of the AuSn solder; specifically, the presence of too many oxides in the submounts purchased from a commercial supplier has been identified by collaborators at Innovative Photonic Solutions, Inc. (Princeton, NJ). Future work will be conducted with new submounts provided by Innovative Photonic Solutions Inc fabricated using co-evaporated AuSn, which have been found to consistently increase the quality and reliability of the bond between the device and the submount. This change should also help with the reliability of the bonding process, and solve the issue of devices coming un-mounted from the submounts observed in this work. 25

43 CHAPTER 4: SIMULATION OF RIDGE WAVEGUIDE PROPERTIES 4.1 Effective Index and Single Mode Cutoff In order to achieve single mode performance for the waveguide structures used in this work it is necessary to determine the single mode cutoff width for both the active and passive waveguide structures used. This width was determined via the simulation of the effective index of the waveguide modes for both the TE and TM polarization in each structure using the FIMMWAVE simulation software package. The cutoff for single mode performance is defined as the ridge width at which the mode index of the second order mode of a given polarization falls below the refractive index of the Al 0.6 Ga 0.4 As lower cladding. The model proposed by Adachi, Ref [34], is used by the FIMMWAVE software program for the calculation of the refractive index of the Al x Ga 1-x As layers, and thus was used for all calculations in this work Passive Waveguide Structure To determine the dimensions required for single mode for the passive waveguide structure the effective index of the first and second order modes for both the TE and TM polarizations were simulated at λ=1550 nm. The results of this simulation can be seen in Figure 4.1. Once the effective index of a given mode drops below the refractive index of the lower cladding layer (indicated by the black dashed line), it is no longer considered to be a guided mode. Thus, the cutoff for single mode performance is then defined as the ridge width at which the effective mode index of the second order mode of a given 26

44 polarization falls below the lower cladding index of the Al 0.6 Ga 0.4 As (n=3.125 at λ=1550 nm). From these results it is determined that the single mode cutoff widths are 2.9 μm and 2.95 μm for the TE and TM polarizations respectively. Figure 4.1. Simulated effective mode index vs. ridge width for the first two TE (red) and TM (blue) modes of the passive waveguide structure at λ=1550 nm Active Laser Structure The calculations outlined in Section were repeated for the active waveguide structure designed for waveguiding at λ=808 nm. The results of this simulation for the first four modes of both the TE and TM polarizations are displayed in Figure 4.2. Due to the wavelength dependent nature of the refractive index, the index for the Al 0.6 Ga 0.4 As lower cladding lies at n=3.263 at the λ=808 nm lasing wavelength for the active structure. From this calculation we can see that the single mode cutoff width for both the TE and 27

45 TM polarizations lies at approximately w~0.9 μm. It should be noted that although this result indicates that the waveguide width must be below 1 μm to guarantee single mode performance, actual laser device results exhibit single mode performance for waveguides several microns in width [4, 35]. This is attributed to increased scattering loss for the higher order modes, which have greater electric field strength at the semiconductor/oxide interface, preventing them from lasing. This effect will be further explained in Chapter 5. Figure 4.2. Simulated effective mode index vs. ridge width for the first 4 TE (red) and TM (blue) modes of the active waveguide structure at λ=808 nm. 4.2 Calculation of Facet Reflectance The calculation of facet reflectance is an important problem related to both active and passive structures in this work. For the active structures, an accurate knowledge of 28

46 facet reflectance is required to determine the internal efficiency of the device. For the passive waveguide structures the accuracy of the loss measurement is directly tied to the accuracy of the reflectance value used. For this reason, a study was undertaken to determine which method should be used to most accurately determine the facet reflectance for these ridge waveguide structures. In order to calculate the facet reflectance of a ridge waveguide several methods are considered. The commonly accepted model found in the literature for the calculation of the facet reflectance of a waveguide is the model proposed by Ikegami [36] and later updated by Herzinger et al. [37] to include more unbound radiation modes. Each of these methods involves matching the electric fields of the waveguide to those in the air. The structure considered by these works can be found in Figure 4.3, shown here with Δn=10% between the core and cladding layers. Figure 4.3. Heterostructure used by Ikegami and later Herzinger et al. for the calculation of facet reflectance. After Ref. [37]. 29

47 Figure 4.4 gives the of facet reflectance for the structure shown Figure 4.3 as obtained in Ref. [37] for both the single mode numerical calculation, which considers only the fundamental mode, and finite element analysis, which considers the fundamental and radiation modes. The single mode numerical results agree well with those found by Ikegami (not shown), with some variation between expected results and those found via the finite element method. This is attributed to cross coupling between the fundamental and radiation modes [37], which is not included in Ikegami s model. The difference is found to be greater for the TM polarization due to an increase in this coupling coefficient at certain modal indices compared to the TE case [37]. As a result of its increased accuracy, the multimode finite element model will be used as the basis to determine the accuracy of the methods discussed in the subsequent sections. Figure 4.4. Single mode numerical (solid) and multimode finite element (dashed) calculations for facet reflectance vs. waveguide core thickness for structure shown in Figure 4.4. After Ref. [37]. 30

48 4.2.1 Comparison of Methods The following sections will detail various methods for calculating the facet reflectance of a HIC RWG structure. The results of this method will then be compared to the results found in Figure 4.4. In this way the most effective method for the calculation will be determined Simple Fresnel Reflectance The most common equation for calculating the reflectance of an interface between any two materials is the simple Fresnel reflectance formula of equation 4-1: Eq. 4-1 where n 1 and n 2 are the refractive index of the first and second materials in question respectively, or n core and n air in the case of a waveguide facet. For the structure in Figure 4.3, this calculation is R~0.32. This equation assumes normal incidence between the propagating wave and the facet. This form also does not take into account the dimensions of the waveguide, or the polarization of the incident wave, and thus is not appropriate for the case considered here Complete Fresnel Reflectance and 4-3: More complete versions of the Fresnel equations can be found in Equations

49 Eq. 4-2 Eq. 4-3 where θ 1 and θ 2 are the angles at which the wave is propagating in the first and second media respectively. Because these forms do take into account the angle at which the wave is incident onto the facet, as well as the polarization of that wave, they are more appropriate for the case of a guided wave propagating in a waveguide. The characteristic angle at which the mode propagates within the waveguide (θ 1 ) can be calculated as θ=asin(n eff /n core ), where n eff is the effective index of the guided mode. This effective index will vary with the structure of the waveguide, and can be easily calculated via the FIMMWAVE software package, as outlined in Section Figure 4.5 shows the reflectance values calculated using Equations 4-3 and 4-4 above, using mode angles calculated from simulated effective index values (dashed lines). The solid lines in this figure represent results shown in Figure 4.4. One can see that for core thicknesses below 700 nm the two results begin to diverge rapidly. This can be explained by examining the confinement factor, Γ, within the waveguide core, which can also be calculated via the FIMMWAVE simulation software. We can see for the range in which the Fresnel calculations begin to diverge from the Herzinger model that Γ begins to decline rapidly. As Γ decreases, less and less of the propagating wave is confined within the waveguide core and a larger percentage is found in the cladding. The 32

50 light within the cladding will experience a lower reflection coefficient, due to the lower index contrast between the cladding and air, thus introducing error into the calculation. Therefore, in waveguides which have significant fractions of their power outside of the waveguide core, the Fresnel equations are not applicable. Limitations within the FIMMWAVE software will not allow for the calculation of the confinement factor in graded regions, such as the GRINSCH structure used in this work, but an approximate calculation of Γ for a HIC structure which has a core with a refractive index of n core =3.204 (the average refractive index of the graded core) indicates a confinement of ~85% for the single mode RWG widths used in this work. This low confinement factor makes the application of the Fresnel equations to the GRIN RWG structure in this work inappropriate. Figure 4.5. Comparison of facet reflectance calculated by Herzinger et al. and the complete Fresnel equations (left axis) and confinement factor (right axis) vs. core thickness for the structure in Figure

51 4.2.4 FIMMWAVE Simulation To calculate the facet reflectance of the RWG structure used in this work, the FIMMWAVE simulation software by PhotonDesign Inc. was chosen. This software package calculates facet reflectance by finding the set of bound and radiation modes within the RWG as well as a complete set of modes in an adjoining air section. The program then calculates the overlap integral of the mode of interest (the fundamental mode) with the set of modes in air via a rigorous algorithm. Although only the fundamental mode (either TE or TM) is of interest, to accurately calculate reflectance many radiation modes must be simulated. This allows for a complete basis set of modes at the interface between the waveguide and air, and also allows for some cross coupling between modes. For a set number of modes in the air section (n=250), the reflectivity of the fundamental TE mode increases from to when the number of modes in the RWG is increased from 2 to 150 modes. A total number of 100 modes in the RWG section were used to provide greater accuracy while minimizing simulation time. In order to verify the accuracy of the FIMMWAVE simulation software for calculating facet reflectance the structure shown in Figure 4.3 was simulated and the results were compared to those in Figure 4.4. From this comparison, shown in Figure 4.6, we see that there is good agreement in the TE case between the multimode finite element (dashed) calculations. In the TM case there is some disagreement between the finite element approach and simulation. This is most likely due to the effect of cross coupling between the fundamental TM mode and the radiation modes, the same reason for the disagreement found by Herzinger [37] in his comparison to Ikegami s single mode case [36]. Overall, the fairly good agreement between these results to the commonly 34

52 accepted model found in the literature verifies the accuracy of the FIMMWAVE software. For this reason, the FIMMWAVE software package was chosen as the most accurate method for the calculation of facet reflectance for the structures used in this work. Figure 4.6. Comparison of facet reflectance calculated by Herzinger et al. (solid and dashed) and the results of the FIMMWAVE simulation (points) Passive Structure Simulation Results With the accuracy of the FIMMWAVE software for the calculation of facet reflectance verified, the software was next used to simulate the facet reflectance for the passive waveguide structure used in this work for waveguide widths varying from w=1.4 μm to w=3.4 μm at λ=1550 nm. The results of this simulation for both the TE and TM polarizations can be found in Figure 4.7. From these results we can see that the facet 35

53 reflectance for the fundamental TE mode is a low R=0.248 for the narrowest single mode ridge waveguides presented in the study outlined in Section (w~1.4 μm) and gradually increases to R=0.302 for the widest waveguides in the study (w~3.4 μm). The TM polarization, however, follows the opposite trend with the reflectance value decreasing from R=0.283 for the narrowest waveguides to R=0.253 for the widest waveguides. Simulations for a PECVD deposited dielectric cladding resulted in reflectance values equal to those of the native oxide-clad waveguides to within Figure 4.7. Simulated facet reflectance vs. ridge waveguide width for both the TE and TM polarizations. These trends for both the TE and TM cases can be explained by examining the Fresnel equations for a slab waveguide similar to the GRIN structure used in this work. In this calculation a refractive index of n=3.204 was used for the graded index core for 36

54 simplification. The results of this calculation can be seen in Figure 4.8. Here we see that as the angle of incidence increases the reflectance of the TM mode continues to rise until it reaches the critical angle (θ C =18.2 ), where it achieves total internal reflection (TIR). In the TE case the reflectance value gradually decreases until it reaches the Brewster angle, θ B =17.1, the angle of zero reflectance for this mode. While the Brewster angle is typically thought of as a phenomenon of the TM polarization, we must remember that in this case our definitions for TE and TM modes are relative to the slab waveguide and not the facet. For this reason equation 4-2 applies to the TM mode of the waveguide and equation 4-3 applies to the TE mode of the waveguide. Figure 4.8. Reflectance vs. angle of incidence with air for the TE and TM polarizations. 37

55 Including the effect of ridge waveguide width on the angle of incidence (right hand axis of Figure 4.9) explains why we see the trends for the reflectance values in the simulation results of Figure 4.7. Figure 4.9 below compares the simulated reflectance values to the values obtained by applying the Fresnel equations. Here we see that the simulation follows the expected trends, with the reflectance of the TE polarization increasing with increasing ridge width and vice versa for the TM polarization. The difference between the Fresnel values and the simulated values is caused by variation between the simplified model used for the Fresnel calculations (uniform core with n eff = 3.204) and the GRIN core used in the simulations. Figure 4.9. (Left axis) Facet reflectance vs. the angle of incidence at the facet for both simulated (solid) and Fresnel calculations (dashed). (Right axis): Ridge waveguide width vs. angle of incidence at the facet. 38

56 4.2.6 Active Structure Simulation Results Using the same method applied for simulating the facet reflectance of the passive waveguide structure in the previous section the facet reflectance for the first two modes in both the TE and TM polarizations was simulated for the active laser structure. The results of this evaluation can be found in Figure The same general trends seen in Figure 4.7 are again present for the active structure. The polarization of the TM mode, both first and second order, begins at a higher value and then decreases to R~0.25 for wider waveguide widths. The TE polarization on the other hand has a lower reflectance for the narrow ridges and increases to R~0.32 for wider guide widths. Although laser ridges of wider than the maximum simulated value of w=5 μm are typically fabricated, the reflectance appears to have reached a steady state value by this point, so simulations of wider waveguide widths are not necessary. These results also partially explain why laser ridges typically favor the TE polarization when lasing. Lasing will first occur in the lowest loss mode, and because the lower reflectance of the TM polarization causes a higher loss for these modes relative to the TE modes, the TE modes will lase preferentially. This assumes an equal modal gain for each polarization, which is not always the case, most notably when strain is introduced into the active region. When this is the case a compressive strain will typically increase the gain of the TE polarization (as is the case for the laser structure used in this work), while tensile strain increases the gain of the TM polarization [38]. 39

57 Figure Simulated facet reflectance vs. ridge waveguide width for the first two modes in both the TE and TM polarizations for the active laser structure at λ=808 nm. An interesting result of these simulations is the fact that if the width of the active device can be narrowed to below w=0.9 μm, the reflectance of the TE polarized modes drops off precipitously, while the reflectance of the TM polarization is increased. This indicates that in this case the TM polarization will have a lower loss. If this effect is paired with increasing the gain of the TM polarization, as in the case of a quantum well under tensile strain [38], it may be possible to create a TM polarized laser. It is important to note that in order to achieve this result a very narrow waveguide is required. Such a waveguide would be extremely sensitive to scattering loss at a roughened sidewall, a problem which the fabrication techniques outlined in Chapter 3, as well as the structures outlined in Chapter 5, are uniquely capable of addressing. 40

58 4.3 Conclusions The FIMMWAVE software program by Photon Design, Inc. has been used to determine the single mode cutoff widths and facet reflectances for the TE and TM polarizations of the passive waveguide structure (λ=1550 nm) and the active laser structure (λ=808 nm). Comparing various methods for the determination of facet reflectance, the FIMMWAVE software has been proven to be an accurate method for performing such calculations. 41

59 CHAPTER 5: DETERMINATION OF RWG PROPAGATION LOSS 5.1 Introduction Models for the scattering loss at the rough interfaces of a waveguide were first proposed by Marcuse [39] and later refined by Tien [40]. The equation put forth by Tien, shown in the form found in Ref. [41], is written as: σ k0h ES ε α = Eq β E dx where α is scattering loss, k 0 is the free space wave number, β is the propagation constant, Δε is the difference in the dielectric constant of the core and cladding (refractive indices squared), h is the transverse propagation constant in the waveguide, σ is the interface 2 E roughness, and S 2 E dx is the normalized intensity of the electric field at the core/cladding interface. From this equation we see that the scattering loss scales with σ 2 and, therefore, reducing the roughness will have a large effect on any waveguide structure, regardless of the index contrast. For HIC waveguides the effect of this scattering loss is magnified because of the increased factor Δε due to the increased index contrast and the increased strength of the electric field at the sidewall [42]. Using simulation software (FIMMWAVE by Photon 42

60 Design Group), the electric field profile of the fundamental mode in a HIC RWG structure can be simulated and the normalized field strength at the sidewall can be calculated. The results of these calculations are shown in Figure 5.1 for TE polarized waveguides with single mode widths between 1.5 µm and 3.4 µm at λ=1550 nm. Figure 5.1. Normalized electric field strength vs. waveguide width for a sample HIC RWG structure with either thermal oxide or deposited dielectric cladding. The dashed line represents an empirical fit (i.e., does not have an explicit functional form). Here we see that as the waveguide width is decreased there is an increase in the electric field strength at the sidewall. It is also evident that the electric field strength is slightly lower, between 6.5% (w=3.4 μm) and 8% (w=1.5 μm) lower, for the waveguides 43

61 with the PECVD deposited dielectric as a result of the higher optical confinement caused by its slightly larger lateral index contrast (Δn~0.15). This larger index contrast leads to an approximately 5% increase in Δε relative to waveguides with OENSO oxide claddings. These factors affecting the overall loss coefficients should be considered when a direct comparison is made between waveguides with claddings of different indices. As Figure 5.1 shows, there is a strong dependence of the sidewall electric field strength, and by extension the scattering loss, on the width of the waveguide. Since the width and index contrast of the waveguides are fixed during the design phase, the only avenue left to reduce scattering loss is to reduce σ, which is typically controlled by the etching process. Price et al. showed that the roughness resulting from a dry etching process began to significantly increase the scattering loss for relatively shallow etches which did not even go into the core of the waveguide [43]. While wet etching would offer improved sidewall roughness over competing dry etch processes, it is difficult to control the final sidewall profile, so dry etching techniques are usually chosen. Through careful optimization of the etching process, the amplitude of the sidewall roughness can be greatly reduced. However, it is still desirable to have some method of smoothing away this roughness after etching. In the silicon material system it has been shown that the oxidation process, by smoothing away roughness as the oxide grows, can significantly reduce the loss of silicon-on-insulator (SOI) waveguides [44]. Recently, a similar oxidation smoothing effect has been demonstrated at Notre Dame during nonselective oxidation in the Al x Ga 1-x As system, confirmed through both scanning electron microscopy (SEM) characterization of the roughness [45] and through the direct 44

62 measurement of scattering loss in passive HIC waveguides [29]. However, the question still remains if this process is capable of reducing the roughness of a highly optimized sidewall. To answer this question the study outlined in the following sections was undertaken to determine the scattering loss of single mode, HIC RWGs fabricated with both PECVD deposited SiO 2 and thermally grown OENSO oxide dielectric claddings. 5.2 Design and Fabrication To ensure single mode performance for the waveguides tested using the Fabry- Perot method the simulations outlined in Section were performed. Based on these results (Figure 4.1) a mask pattern containing ridges varying in width between 1.0 μm and 3.3 μm was fabricated and used to lithographically define ridges for both PECVD and OENSO clad devices. With the addition of a SiN x etch mask and optimized ICP-RIE etching, single mode waveguides are fabricated on the passive waveguide structure outlined in Section 3.2 on the same wafer used in Ref. [29]. The fabrication process used is a simplification of the laser diode process flow outlined in Appendix A, stopping after the OENSO oxidation step (Step 20). Improvements in the fabrication process over our previous work [29] include the use of a SiN x hard etch mask and optimized ICP-RIE etching. After fabrication, the width of each individual waveguide is determined via cross-sectional SEM. Figure 5.2 contains sample images of completed ridge waveguides with either (A) PECVD deposited SiO 2 or (B) a OENSO native oxide cladding layers. These waveguides are 1.67 μm and 1.68 μm wide, respectively. The 700 nm thick graded-index core is denoted by the dashed lines in the figure. 45

63 Figure 5.2. Fabricated high-index-contrast ridge waveguides with (A) PECVD deposited SiO 2 and (B) OENSO thermal oxide claddings. Dashed lines indicate the location of the graded index core region. 5.3 Testing Completed devices are then cleaved into two unique lengths between 1 mm and 5 mm and single mode waveguides are tested on the Fabry-Perot testbed outlined in Refs. [29, 46]. The two samples are then cleaved into two shorter pieces (4 total) of unique length, and each waveguide sample is re-tested. The output of a continuously tunable Agilent 81940A laser is coupled into a specific waveguide via a lensed fiber. This fiber is single mode at λ=1550 nm, polarization maintaining, and anti-reflection coated with a spot size of ~2.5 μm and a working distance of ~13 μm. Each waveguide is tested with both the TE polarization (electric field normal to the growth direction) and, with the fiber is rotated 90, TM polarization light. The output of the ridge waveguide is then collected into a lens and focused onto a Ge detector. For each test the wavelength of the input 46

64 signal is tuned over a 5 nm range from nm to nm. A sample of the recorded output power vs. wavelength curve is shown in Figure 5.3. Figure 5.3. Sample plot of output power vs. wavelength in the TM mode for a w=2.57 μm OENSO clad ridge waveguide. From data such as that in Figure 5.3 the K-value ([P max -P min ]/[P max +P min ]) can be determined. If the length of the waveguide and the facet reflectance are known, the loss coefficient, α, can be determined using Equation 5-2. From this equation we can see that the K-value, which is proportional to the depth of the fringes (P min /P max ), is inversely proportional to the loss of the waveguide being tested. 47

65 2 ( 1 K ) 1 ln = α L ln R Eq. 5-2 K If the reflectance value is not known, however, both α and R can be determined simultaneously by performing measurements of the K-value for multiple guide lengths and plotting the value on the left hand side of Equation 5-2 versus length. A linear fit can then be performed on the data, as shown in Figure 5.4. The slope of this linear fit gives α for the given waveguide and the intercept is proportional to the facet reflectance. To increase the accuracy of the results, a MATLAB script was used to exclude data which fell well outside of the expected linear fit. The outlying points are reasonably associated with defective waveguides having bad facet cleaves or other major discrete defects. Data from waveguides of nominally equivalent widths were averaged together to increase accuracy and allow for more points in the fitting process. Figure 5.4 shows both the complete data set (red) and the truncated data set (blue). In the case of this particular set of waveguides, fitting of the complete data set yields a loss of α=1.89 cm -1 and R=0.228 and a fitting coefficient R 2 (not to be confused with the reflectance squared) of R 2 = After truncation of the data set to exclude outlier data, this procedure results in a loss coefficients of α=2.19 cm -1 and R=0.252 with R 2 = The reported loss coefficient increases, but the overall confidence in the result is increased. 48

66 Figure 5.4. Sample plot of length dependent data and linear fit for the TE mode of a w=2.77 μm OENSO clad ridge waveguide before (red) and after (blue) exclusion of data points from presumed defective waveguides. The linear fitting procedure described above was completed for all of the waveguides tested in this work. The linear regression function in MATLAB was used for the fitting, and error bars for both α (slope) and R (exp(-intercept)) are taken from the t- statistics of the fit. Error bars for the ridge width are taken as one standard deviation of the average of waveguide widths for each set. The results for both polarizations and both cladding materials can be found in Figure 5.5 below. As reported in this figure, minimum average loss coefficients in the TE polarization of 1.456±0.125 cm -1 and 2.185±0.137 cm -1 are seen for the PECVD and OENSO clad devices, respectively. Minimum loss coefficients in the TM polarization of 1.441±0.151 cm -1 and 2.041±0.137 cm -1 are seen for the PECVD and OENSO clad devices respectively. These values, along 49

67 with those determined using simulated reflectance values (discussed in Section 5.5) are listed in Table 5.1. The loss values obtained show a significant improvement over our previous work reported in Ref. [29], with the TE polarization loss having been reduced by greater than a factor of 2 for OENSO clad waveguides and a factor of more than 18 for PECVD clad waveguides. Although no data is available for the TM polarization of the previous waveguides, a similar reduction in loss can expected. It should be noted when making the comparison between these two devices that the difference in the refractive indices of the cladding layers does have an effect. However, as discussed in Section 5.1, the increase in scattering loss caused by the increase in index contrast (Δn~0.15) of ~5% for the PECVD dielectric clad waveguides is compensated by the decreased electric field strength at the side wall for these devices (6.5% to 8% depending on width). This allows us to make a fair apples to apples comparison between the devices with these two different cladding layer materials. Experimental results for the facet reflectance obtained from the linear fit of the waveguide loss data, as discussed above, as well as values determined by simulation can be found in Figure 5.6. The experimental results for facet reflectance are quite different than what is predicted by simulation. While the experimental values are near the simulated results at wider waveguide widths (w 3 μm), at narrower guide widths the R values drop significantly below the expected values. This trend also follows qualitatively with device yield, with more functional devices at the wider widths and fewer operating at the narrowest widths. Additionally, the trends seen in the simulations, notably R TM decreasing for increasing waveguide width, are not seen in the experimental results. Reasons for these differences will be discussed in the following section. 50

68 Figure 5.5. Propagation loss coefficient calculated via the linear fitting method vs. ridge waveguide width for all waveguides tested. Figure 5.6. Experimentally determined and simulated values for facet reflectance vs. ridge waveguide width. 51

69 5.4 Sources of Error To examine these results in further detail, we will discuss the two major contributors to error in this experiment: discrete defects and imperfect facets Discrete Defects In determining the effect of a discrete defect we first examine the effect on the K- value (also fringe depth) from such a defective waveguide. In general, when a defect is present it increases the loss of a given waveguide. From the sample fringe plot for a 1 cm cavity with a facet reflectance of R=0.3 and various loss values, shown in Figure 5.7, we can see that this increase in loss will decrease both the K-value and the depth. This decrease in K-value will increase the value on the left hand side of Equation 5-2, which will affect the result of a linear fit. Figure 5.7. Normalized transmission vs. phase difference for a 1 cm waveguide sample with R=0.3 for various values of α. 52

70 In explaining the effect a discrete defect has on the linear fitting of the waveguide data in this experiment, one can imagine a single waveguide containing such a defect which is tested at its full length and then cleaved into two shorter sections of differing length. This waveguide initially has a 1 cm long cavity with a facet reflectance of R=0.30 and a loss of α=1 cm -1 if no defects are present. The red linear fit in Figure 5.8 depicts a length dependent data set for this waveguide if it were tested at 1 cm, and two segments of 0.3 cm and 0.7 cm. Figure 5.8. Sample length dependent data showing effect of a discrete defect present in a single waveguide tested at three different lengths. Now, we can introduce a defect into the waveguide which adds an additional 0.25 cm -1 of loss to the waveguide, increasing the term on the left hand side of Equation 5-2 for the 1 cm guide length. When this 1 cm waveguide is then cleaved into two segments 53

71 of 0.3 cm and 0.7 cm there is a chance that this defect will be in either section. The blue and green linear fits in Figure 5.8 show the effects when this defect occurs in the longer and shorter sections, respectively. From the linear fits we see that this defect has increased the loss coefficient in each case, to α=1.36 cm -1 when found in the L=0.7 cm long section or to α=1.23 cm -1 when it is found in the shorter (L=0.3 cm) section. The presence of the defect also alters the reflectance value extracted from the linear fit, raising the reflectance to R=0.33 when the defect is in the longer (L=0.7 cm) section and R=0.31 for a defect in the shorter (L=0.3 cm) section. This defect also results in decreases in the confidence in the fit results to R 2 = when present in the L=0.7 cm section or to R 2 =0.948 when present in the L=0.3 cm section. This example clearly illustrates how a discrete defect can affect the results of the linear fitting procedure for loss and facet reflectance, as well as the overall confidence in the result Imperfect Facets To determine the effect of an imperfect or angled cleave on the determination of loss, we will first consider the effect of an angled facet. Figure 5.9 contains the results of simulations for the facet reflectance of facets angled between 0 degrees (normal incidence) and 5 degrees off normal. From these results we can see that when an angle is introduced into the facet, there will be a lowering of the facet reflectance. It is for this reason that angled facets are commonly, intentionally used when feedback is undesirable for a given device. 54

72 Figure 5.9. Simulated facet reflectance vs. facet angle for various TE mode waveguide widths. Considering the fact that an imperfect (angled or damaged) cleave will always lower the reflectance of the facet, the effect of a change in facet reflectance on the transmission of a Fabry-Perot cavity can be examined. Figure 5.10 shows the result of a calculation of the transmission of such a cavity with a fixed loss coefficient of α=1 cm -1 and a fixed length of L=1 cm for various values of facet reflectance. Here we see that as the reflectance is lowered, the fringe depth decreases for a specific loss. This means that for a waveguide with a certain characteristic loss, an imperfect cleave will result in an artificially low fringe depth (or high K-value). In this way, an artificially elevated K- value will also affect the experimental determination of R through the linear fitting method discussed above, in the same fashion as does a discrete defect. Additionally, if Equation 5-2 is used to calculate α using an assumed (or simulated) value for R, which 55

73 should be an upper limit on the facet reflectance, this will cause an over-estimation in the loss of the waveguide in question. Figure Normalized transmission vs. phase difference for a 1 cm waveguide sample with α=1 cm -1 for various values of facet reflectance. To further explore possibility of error introduced by the facet, top-down SEM micrographs were taken of some of the waveguide samples used in this work. Figure 5.11 A and B each show such an examination of the left (L) and right (R) hand side of separate PECVD clad waveguides. The two waveguides are on the same chip, meaning that they share a common cleave on each side. From Figure 5.11 A, we can see that the angle of the facet on the left and right hand sides vary significantly. The left hand side is parallel to the cleave, where as the right hand side shows a 6 offset from the rest of the cleave. The presence of this angle on one side of the sample will introduce error into 56

74 any data tested on this particular waveguide. Additionally, we see that for this narrow waveguide there is a difference in waveguide width of approximately 200 nm from one end of the sample to the other. This variation is caused by either non-uniform lithography across the sample or a non-uniform thickness of the deposited dielectric. When we examine the larger waveguide of Figure 5.11 B we see that this waveguide again has a left hand facet that is parallel to the rest of the cleave. Looking at the right hand side we again see a slight tilt to the facet, approximately 5.5, but the tilt is only present at the bottom half of the facet, not the entire facet as with the waveguide in Figure 5.11 A. This demonstrates that although both facets are formed by the same cleave, the error from one waveguide to another will vary, even within a single sample. Figure Top view of left and right facets of a PECVD clad RWG from the same sample. A similar top-down examination of the OENSO clad waveguides was also performed, and is shown in Figure In side A of this figure, we see that the left and right facets of the waveguide are very similar and appear to be parallel to the cleave. The 57

75 facets of the waveguide shown in Figure 5.12 B seem to not be perfectly parallel to the cleave, and do not appear to be completely straight. These deviations from a perfectly normal facet will again introduce error into the measurement. Again we see that this error will not be the same from waveguide to waveguide, even within a single sample. Finally, from close examination of Figure 5.11 and Figure 5.12 we can see that the PECVD clad waveguide appears to have a rougher edge than the OENSO clad waveguide. Because this top down approach only sees the outer edge of the cladding layer, this roughness may not be characteristic of the roughness of the inner oxide/semiconductor interface. Due to the fact that the measured propagation losses of waveguides with the two different claddings appear to be the same, as will be discussed in Section 5.5, this roughness at the outer interface is characteristic of the dielectric deposition process in PECVD, not of the lithographic or etching processes which define the inner interface for the waveguides with the PECVD deposited dielectric cladding. Figure Top view of left and right facets of an OENSO clad RWG from the same sample. 58

76 One final issue arising from cleaving, other than slight tilts to the facet, is physical damage caused by the mechanical stress of cleaving. This can lead to the ridge chipping or cracking, resulting in a non-functioning device. A sample image of a waveguide which has suffered cracking in its lower cladding is show in Figure Figure Cross-sectional SEM of an OENSO waveguide with a crack incurred during cleaving. 5.5 Results for Individual Waveguides After determination of the K-value for each guide tested, simulated values for R (given in Figure 4.7), were used in Equation 5-2 above to determine the loss of each waveguide. The results for TE and TM polarization are shown in Figure 5.14 and Figure 5.15 respectively. Minimum losses in the TE polarization of 1.43 cm -1 and 1.68 cm -1 are seen for the PECVD and OENSO clad devices respectively. Minimum losses in the TM polarization of 0.58 cm -1 and 0.67 cm -1 are seen for the PECVD and OENSO clad devices 59

77 respectively. These values are also listed in Table 5.1. Although in each case the PECVD clad waveguides had slightly lower loss, the scatter in the data shows no clear evidence that either method for achieving a dielectric cladding is superior to the other. The achievement of lower loss in the PECVD guides may also be due to the waveguides in question having fewer discrete defects when compared to other devices. Figure Propagation loss coefficient of the TE polarization vs. RWG width for OENSO and PECVD clad waveguides. Solid points indicate single mode (SM) waveguides, outlined points indicate multimode (MM) waveguides. 60

78 Figure Propagation loss coefficient of the TM polarization vs. RWG width for OENSO and PECVD clad waveguides. Solid points indicate single mode (SM) waveguides, outlined points indicate multimode (MM) waveguides. 5.6 Comparison of loss values: individual and linear fit Figure 5.16 and Figure 5.17 compare the propagation loss coefficients for a group of several different length waveguides as calculated via the linear fitting method (Section 5.1) and the individual waveguide results calculated using a simulated reflectance value (Section 5.5) versus ridge waveguide width for the TE and TM polarizations respectively (right hand axis). A comparison of the facet reflectance determined via the linear fit and simulation is also depicted (left hand axis). A similar comparison of the PECVD dielectric clad devices (not shown) yields similar results. A comparison of the lowest 61

79 measured losses determined by each approach can be found in Table 5.1. From this comparison we can see that the lowest loss coefficients for each case are from the calculation involving individual waveguides using a simulated reflectance. This is not surprising because such hero results typically lie outside of the range highlighted by the error bars. These points represent those waveguides which contain the fewest discrete defects and or facet imperfections. For this reason, the lowest loss values are typically reported because they are indicative of what is achievable if these various yield-related processing issues and other errors can be resolved [47]. Figure Comparison of propagation loss coefficient and facet reflectance for both individual results and the linear fit vs. ridge waveguide width for TE polarized OENSO clad waveguides. 62

80 Figure Comparison of propagation loss coefficient and facet reflectance for both individual results and the linear fit vs. ridge waveguide width for TM polarized OENSO clad waveguides. From these results we see that there is some discrepancy in the agreement between the propagation loss coefficients obtained from the linear fit and the values for individual waveguides calculated using a simulated reflectance value. These differences can be explained when we also examine the variations in the agreement between facet reflectance values obtained from the two methods. For both polarizations, in cases where the loss coefficient value from the linear fit lies above most of the individual values, the R value from the linear fit also lies above the simulated value. This is due to the fact that when the reflectance value is larger for a given data set the loss value will also be larger as explained in Section The opposite is true in cases where the loss coefficients 63

81 obtained by the linear fit are lower than the individually calculated points while the reflectance value is much lower than predicted by simulation. TABLE 5.1 LOWEST PROPAGATION LOSS COEFFICIENT VALUES Sample Description α, Linear Fit (cm -1 ) α, Simulated R (cm -1 ) OENSO clad, TE 2.185± OENSO clad, TM 2.041± PECVD clad, TE 1.456± PECVD clad, TM 1.441± Determination of group index From this experiment we can also extract the group index of the fundamental mode. This is done by determining the spacing between the fringes in the experimental sweep (seen in Figure 5.3). This spacing, Δλ, can then be used to determine the group index via the following equation: n g 2 λ = 2 λ L Eq. 5-3 The results of this calculation for the experimentally determined group index can be found in Figure 5.18 along with simulation results. As this plot shows, there is significant spread in the data with no apparent dependence on waveguide width, cladding material, or polarization. Table 5.2 contains the average values and standard deviation for the group index for each sample. The average group index of n g ~3.320 for the OENSO clad waveguides is slightly higher than the PECVD clad waveguide average 64

82 value of n g ~ However, because this difference is within one standard deviation, σ~0.0131, it cannot considered to be statistically significant. Figure Group index vs. RWG width for both TE and TM polarizations. Points represent experimental data, solid lines represent simulated values. TABLE 5.2 AVERAGE GROUP INDEX VALUES Sample Description Average Group Index, n g Standard Deviation OENSO clad, TE OENSO clad, TM PECVD clad, TE PECVD clad, TM

83 5.8 Comparison to the state of the art To place these results into context, a literature search for reports of low-loss single mode waveguides was undertaken. The results of this search can be found in Figure 5.19, with the full results and citations found in Table 5.3. This plot shows the propagation loss coefficient, α, in db/cm (4.34 db/cm=1 cm -1 ) versus the lateral index contrast, Δn, between the core and cladding of the waveguide. Because of the wide range of values present for both α and Δn, both axes are plotted on a log scale. The lowest loss waveguides found in the literature, with an extraordinarily low loss of α=0.001 db/cm, and an index contrast of Δn=0.54 [48] are not included in this plot. From this plot we can see that there is a wide range in both the index contrast and reported loss values. Figure Propagation loss coefficient vs. index contrast for waveguides reported in the literature. Note: Log scale on both axes. 66

84 To make a fair comparison between the waveguides in this work and those found in the literature, several items must be taken into account. First of all, we look at the index contrast of the waveguides in question. As we have described, the RWGs in this work feature a high index contrast of Δn 1.5, which allows for the possibility of an extremely small bending radius. For this reason we will limit our comparison to waveguides which have a similarly high index of Δn 1.0. Additionally, we will exclude those waveguides which do not consist of semiconductor material, such as lithium niobate [49] or some variety of As x S y [50, 51]. Making these simplifications, the data can be re-plotted to include only the HIC waveguides, shown in Figure This leaves us with a much smaller set of waveguides with which to draw a fair comparison. Figure Propagation loss coefficient vs. index contrast for HIC waveguides reported in the literature. Note: Log scale on y-axis. 67

85 Next, we further differentiate the waveguides by defining single mode to mean a waveguide whose width is below the cutoff width for single mode performance, as seen in Figure 4.1. The first of these works utilizes a complicated etching and regrowth technique to fabricate their waveguides [52]. The authors report that at longer guide lengths the waveguides are single mode; however, at shorter guide lengths, near-field patterns reveal that these waveguides are not truly single mode. The single mode performance at longer guide lengths is most likely due to increased scattering of higher order modes, which filters out these modes during their propagation aver a relatively longer distance. For this reason the work in Ref. [52] does not qualify as a true single mode waveguide. Nest examining the waveguides reported in Ref. [53], which report losses as low as 3.5 db/cm for a deeply etched InP based waveguide with an index contrast of Δn~1.6. The structure in this work achieves single mode performance only by coupling the waveguide into a multimode interference (MMI) coupler, which filters out the even numbered modes. This filtering effect allows waveguides up to the cutoff width of the 3 rd order mode to propagate effectively only a single mode. Were the waveguides in Ref. [53] not to employ this MMI filtering design, they require much narrower waveguides to ensure single mode operation, which would result in considerably higher propagation losses. For this reason we can exclude this report from a direct comparison with our waveguides. Finally, we compare our waveguides to those of Ref. [54]. Here the waveguide structure is deeply etched GaAs with an air cladding (Δn~2.4) and achieves losses as low as α=4.34 db/cm (α=1 cm -1 ), lower than the those of this work. The structure used by the 68

86 authors is specifically designed to have a very small vertical index contrast between the waveguide core and the lower cladding. This increases in the lower cladding index increases the cutoff width for single mode propagation (effectively shifting the dashed line in Figure 4.1 up) by causing higher order modes to couple into the substrate. These waveguides do meet our definition for single mode performance; however, this approach significantly limits the minimum bending radii these waveguides can achieve to radii greater than 100 μm [54]. This happens because as the light goes around a bend it shifts to the outer edge of the waveguide, where it experiences a decreased effective index. For this structure, the slight local decrease upon bending will drop the effective index below the index of the lower cladding, causing leakage into the substrate. So while the structure used in Ref. [54] does minimize the loss of straight waveguides, it cannot be applied as extensively as the structure used in this dissertation to the large number of applications that require a small bending radius. Of the other waveguides found in the literature, those found in Ref. [55] are the most similar. This work reports deeply etched GaAs waveguides with an index contrast of Δn=2.3 and losses as low as 12 db/cm. The waveguides in this work were single mode at λ=1550 nm at widths ranging from 0.42 μm and 0.82 μm, much narrower than those in our work. If the dimensions of these waveguides were increased to values near the single mode cutoff, it is likely that they would perform as well or better than the waveguides in our work. However, these waveguides were fabricated using highly optimized electron-beam lithography and chemically assisted ion beam etching, two processes which are not as compatible with batch processing as the contact lithography and ICP-RIE etching used in this work. Finally, it should also be noted that some reports, 69

87 such as Ref. [42] contain values as low as 1.8 db/cm, but these reports are for widths above the single mode cutoff. For waveguides in Ref. [42] below the single mode cutoff width, the reported loss of α~21 db/cm is much higher than the results in the present work. 5.9 Future work In future studies, several suggestions may be incorporated to improve the overall loss results and increase measurement accuracy. First of all, reducing the number of different ridge waveguide widths on each sample will improve the overall accuracy. This will allow more averaging to lessen the effect of discrete defects and cleaving imperfections. Using projection lithography in combination with a reticle fabricated via electron-beam lithography will also decrease the roughness of the initial lithographically defined pattern. Conventional projection lithography will not offer the low line edge roughness achievable with EBL, but it will lower the roughness when compared to the current methods (contact lithography with a mask fabricated in-house) while still maintain a batch processing compatible process. Additionally, a new epitaxial wafer grown with a lower intrinsic carrier concentration of less than 1x10 14 cm -3, as noted in Refs. [56, 57], will reduce the free carrier absorption in the structure and lower the overall propagation loss. In order to reduce the possibility of facet defects, the waveguides should also be thinned from their initial thickness of ~450 μm to ~100 μm prior to cleaving and testing, as is conventionally done during laser diode fabrication. To reduce the possibility of damage to the waveguides during cleaving, as in Figure 5.13, 70

88 RWGs can be encapsulated in a thick dielectric film for added structural support. Finally, a study may be undertaken to determine if the added O 2 content in the OENSO process has an effect on the overall propagation loss of ridge waveguides Conclusions For the reasons outlined above, we believe that the ridge waveguides report in this work represent a record low loss for a true single mode waveguide (below the single mode cutoff width) which is compatible (i.e., has a high lateral index contrast) with the small bending radii required for photonic integration. Unlike in our previous work [29], no significant difference was seen when comparing the loss coefficient of waveguides with a PECVD deposited cladding versus an OENSO dielectric. This is due to the further optimization of the fabrication process and indicates that when starting with an optimized sidewall, as is the case here, the benefit of the oxidation smoothing provided by the OENSO process is minimized. However, it should be noted that all avenues for improvement in the OENSO processing conditions have not been explored. The effect of the O 2 /N 2 ratio on the smoothing capability of the OESNO process has not yet been investigated. The use of angle lapping and SEM imaging can be used in addition to Fabry-Perot loss measurements to determine if changing this ratio has an effect on the final sidewall roughness and propagation loss. This angle lapping procedure has been described elsewhere [58], and a fixture has been purchased for the MultiPrep lapping/polishing tool for this purpose. Additionally, furnace modifications for the improvement of oxide 71

89 uniformity, such as the honeycomb flow straightener as outlined in Ref. [59], which provides more uniform gas flow and increased oxide uniformity, can also be examined. It is important to note that while we are no longer reducing the loss with the OENSO process, the process is not increasing the propagation loss. While the fabrication process for the passive waveguides in this study is similar, when fabricating active waveguides the OENSO process offers a simpler, self aligned process when compared to the use of a deposited dielectric cladding. As will be discussed in Chapter 6, for active device applications oxidation may also yield a cleaner, better electrically passivated interface, eliminating damage caused by dry etching, thus offering forth further advantages over deposited dielectrics. 72

90 TABLE 5.3 LOW LOSS, SINGLE MODE, WAVEGUIDES IN THE LITERATURE Index Contrast Loss Coefficient (db/cm) Material Reference GaAs [60] InP [61] InP [62] GaAs [62] InP [63] GaAs [64] GaAs [65] Polysiloxane [66] SiN x in SiO 2 [48] As 2 S 3 [51] 1 3 Lithium Niobate [49] As 0.42 S 0.58 [50] GaAs [52] GaAs [29] GaAs (TE) This Work GaAs (TM) This Work InP [53] InGaAsP on SiO 2 [67] GaAs [29] GaAs (TE) This Work GaAs (TM) This Work 2 45 GaAs [68] GaAs [55] GaAs [54] InP [42] 73

91 CHAPTER 6: CHARACTERIZATION OF THE ELECTRICAL QUALITY OF THE SEMICONDUCTOR/OXIDE INTERFACE 6.1 Introduction In addition to the reduction in scattering loss due to the smoothing effect of the OENSO process, the thermally grown native oxide is thought to provide some degree of electrical passivation of the etched surface as well. Due to the deep dry etch used to form the HIC ridge, surface states originating from dangling bonds as well as ion damage can create bulk defects near the surface which can also capture electrons and holes. The associated energy levels introduced within the semiconductor energy gap can serve as centers for nonradiative electron-hole recombination, reducing the overall efficiency of an active device. In this work time resolved photoluminescence is attempted to unambiguously determine if the electrical quality of the thermally oxidized interface is improved compared to that of deposited dielectrics in addition to an expected improvement due to the reduction of ion-damage as the oxide grows inward from the etched surface. We hope to determine if the thermal oxide provides a cleaner, better passivated oxide/semiconductor interface than that of a deposited dielectric. 74

92 6.2 Time-Resolved Photoluminescence Time-resolved photoluminescence (TRPL) is a technique for examining the evolution of a photoluminescent signal over time. By exciting a semiconductor sample with an ultra-short pulse, typically less than 1 ns, and then tracking the photoluminescent (PL) intensity over time the minority carrier lifetime of the sample can be extracted. The system used for this experiment is a PicoHarp 300 stand alone time correlated single photon counting (TCSPC) system with 4 ps resolution. The excitation source is a 2W Fianium Supercontinuum SC450 ultra-broadband white-light laser pulsed laser source (λ=460 to 2200 nm, 6 ps pulse duration, 20 MHz repetition rate). The light emitted from the sample is focused into a Princeton Instrument s Acton 2500i spectrometer, the detector of which is connected to the TCSPC system. The TRPL technique was commonly used in early photonics research to characterize the quality of the new materials being grown, specifically the quality of the interfaces between quantum wells and the surrounding layers. Through a careful study of the carrier lifetime versus the thickness of a quantum well, the surface recombination velocity can be determined at the interfaces between layers [69-71]. In these studies, low surface recombination velocities, well below 1000 cm/s, were found for various GaAs/Al x Ga 1-x As heterostructures, indicating the high quality of the growth techniques used. In more recent work, TRPL has been applied to determine recombination velocity of carriers at etched interfaces, particularly etch exposed active regions of optical devices such as quantum well and microdisc lasers. In these studies mesa structures of varying diameters are uniformly excited by a laser pulse and the carrier lifetime is extracted. 75

93 A simplified version of these experiments is used to determine qualitatively, without the direct determination of surface recombination velocities, if the OENSO process improves the electrical quality of the oxide/semiconductor interface. To make this determination, a single ridge is etched into the active epi-strucutre described in Section 3.1. The sample is then excited with an approximately 6 μm diameter pump beam and the carrier lifetime is determined both at the etched ridge (typically with the excitation spot half on/half off of the ridge) and 25 μm from this edge. 25 μm was chosen as the distance from the edge to use as an approximate bulk lifetime value because it was determined via experiment that the carrier lifetime has recovered to a steady state value by that point, shown in Figure 6.1. Figure 6.1. Carrier lifetime vs. distance from ridge edge for an ICP etched ridge. Pump at λ=488 nm. 76

94 6.3 λ=488 nm pump trials Initial lifetime testing was performed on the active structure described in Section 3.1 with an excitation wavelength of λ=488 nm. Due to the strong absorption of the Al 0.6 Ga 0.4 As cladding and GaAs cap layers at this wavelength the entire cap and most of the upper cladding layer was removed. Wet chemical etching was used to remove these layers: 1:10 citric peroxide to selectively remove the GaAs cap and 1:8:80 HCl:H 2 O 2 :H 2 O to non-selectively remove the upper cladding layer. After this material was removed the carrier lifetime was mapped across the bulk sample before further processing. The results of this mapping can be Figure 6.2 for a 4 mm by 16 mm sample. From this data it can be seen that the carrier lifetime varies significantly with position across the sample, from approximately nanoseconds to more than 1.30 ns. The average lifetime was ns ± ns, a 15% standard deviation in the measurement. After initial testing of the carrier lifetime of the bulk material, it was further processed by etching a single ridge, or step, across the entire sample in the ICP-RIE tool. The ridge was etched through the GRIN core and quantum well into the lower cladding. After etching, the sample was cleaved in half, with half of the sample being oxidized and the other half left as etched. Both samples receive the same refresh etch typically used prior to oxidation (5 seconds in 1:4 HCl:H 2 O) to ensure similar surface quality after etching. The oxidized sample was oxidized at 450 C for 30 minutes with a 0.4% O 2 /N 2 ratio. This oxidation condition was chosen because it is the condition most commonly used in the fabrication of OENSO lasers. Carrier lifetimes are then taken on both the as etched and etched and oxidized samples at the edge of the ridge and 25 μm from this edge at multiple locations along the ridge. In order to correct for the large variation seen in the 77

95 carrier lifetime in the sample before processing, the ratio of lifetime at the ridge edge to the lifetime in the bulk immediately adjacent to the ridge is considered. Averaging data taken from each sample yields an average ratio of ± for the as etched sample and ± for the etched and oxidized ridge. While these results indicate a slight improvement in carrier lifetime in the oxidized sample, this improvement is still within the error of the experimental data. Figure 6.2. Carrier lifetime across a bulk sample after removal us the cap and upper cladding layers. X (red) and Y (blue) sweeps across the center of the sample in that dimension. Pump at λ=488 nm. Zero in X and Y correlates to the left and bottom edges of the sample, respectively. 78

96 Figure 6.3. Ratio of carrier lifetime at an etched edge to carrier lifetime in the bulk immediately adjacent to the edge for as etched (red) and etched and oxidized (blue) samples. 6.4 λ=650 nm pump trials In an attempt to remove the variable of etching depth when removing the upper cladding layer from the GRINSCH structure, the excitation wavelength was moved to λ=650 nm. With a photon energy of approximately E=1.91 ev, this wavelength is now below the bandgap of the Al 0.6 Ga 0.4 As cladding layer (E=2.03 ev). Because the upper cladding is now transparent at the pump wavelength this layer no longer needs to be removed; only the GaAs cap, which is easily removed via a selective wet etch, must be removed. After this change, another sample was prepared and the carrier lifetime was mapped across the sample prior to further processing. The experimental results obtained can be seen in Figure 6.4 below for mapping across the length of a 12 mm by 10 mm sample in the top, bottom, and center. The variability of the carrier lifetime across the 79

97 sample was greatly reduced, with an average lifetime of ns ± ns. This 2.3% variation is a vast improvement over the 15% variation in the etched samples pumped at λ=488 nm. Figure 6.4. Carrier lifetime across a bulk sample after removal of the GaAs cap. Pump at λ=650 nm. Zero in X corresponds to the left edge of the sample. With the variation in the carrier lifetimes within the bulk reduced to acceptable levels, the previous experiment involving testing the lifetime at the edge of an etched ridge relative to the bulk immediately adjacent to the ridge is repeated. Additionally, lifetimes were also taken at a cleaved edge which was exposed to the processing conditions (labeled etched cleave ) as well as the bulk immediately adjacent to the cleaved edge. By exposing this cleaved edge to the processing conditions (i.e. plasma), it received a similar surface treatment as the etched ridge. Samples were prepared with 80

98 both RIE and ICP-RIE etching. Again, half of the sample is left as etched; the other half is oxidized for 30 minutes at 450 C with a 0.4% O 2 /N 2 ratio. The results of this experiment can be seen in Figure 6.5. Figure 6.5. Ratio of carrier lifetime at an edge to carrier lifetime in the bulk immediately adjacent to the edge for as etched (or cleaved) and etched (or cleaved) and oxidized. Samples prepared with both RIE (red) and ICP-RIE (blue) etching. From the figure above we can see that in the RIE case there is a definite improvement in the ratio of lifetimes after oxidation. The lifetime ratio at the edge of an etched ridge improved from ± 0.08 to ± 0.07, with a similar margin of improvement seen for the cleaved edge that was exposed to the processing conditions. While this does indicate that the lifetime is improving though application of the OENSO process, this improvement again falls within the experimental error. 81

99 For the ICP-RIE etched case found in Figure 6.5, we see very little difference between an as-etched and etched and oxidized sample. For the etched ridge the average ratio of lifetimes is ± for an as-etched sample and ± for the etched and oxidized case. The cleaved edge shows a similar result, with a 1% relative improvement for the oxidized sample. These results indicate that the carrier lifetime at an ICP-RIE etched edge is not affected significantly, positively or negatively, by the application of the OENSO process. It must be noted that during the two days that data was taken for the previous study, the lifetime of samples measured on day one was approximately 200 picoseconds higher than the expected bulk lifetimes from the previous study (in Figure 6.4) and also higher than testing on days of testing. All data for RIE etched samples, and the data for the un-oxidized ICP-RIE etched ridge were taken on day one, with data on the unoxidized ICP-RIE etched cleave and oxidized ICP-RIE sample taken on day two. This discrepancy was not discovered until after the testing was completed, and no known cause for this shift has been determined. 6.5 Conclusions From the studies outlined in this chapter several lessons can be learned. First of all, using an excitation wavelength that is transparent to the upper cladding layer of the epi-structure is preferred because it was shown to reduce variability in the carrier lifetimes across a bulk sample. Secondly, it is concluded that while there is evidence of improvement in the lifetime at an etched edge prepared using RIE etching, which is 82

100 known to cause greater damage than ICP-RIE etching because of its higher DC bias (~300 V for RIE vs. ~120 V for ICP-RIE), the improvement is not statistically significant for the data collected. In the case of an etched ridge fabricated using a more optimized ICP-RIE etching recipe, no statistical difference is seen in samples that have been oxidized when compared to samples that have not been oxidized. As is the case with the passive waveguides studied in Chapter 5, the use of different O 2 /N 2 ratios has not yet been explored, and may carry the possibility of improved interface quality by optimizing the removal of As 2 O 3 from the oxide/semiconductor interface. As discussed in Section 2.3, the removal of the oxide is important to forming an electrically clean interface. Overall, these results indicate that at worst, the application of the OENSO process does not degrade the electrical quality of the semiconductor/oxide interface of a deeply etched device. This is important because, even if the OENSO process does not offer a greatly improved electrical interface over other methods for electrically passivating the oxide/semiconductor interface of deeply etched optoelectronic devices, the simplified, self-aligned process still offers a distinct advantage over deeply etched devices with a deposited dielectric cladding layer. 83

101 CHAPTER 7: ACTIVE DEVICE STUDIES 7.1 Double Trench Devices Introduction Having examined several of the important aspects of HIC RWG structures fabricated using the OENSO process, we turn our attention to the use of this process to fabricate active laser devices. Previous work on such devices has shown great promise, with devices fabricated in this fashion demonstrating improved performance over conventional gain guided lasers and HIC RWG devices fabricated with a PECVD deposited dielectric [7], racetrack ring resonators with bending radii as small as r=6 μm [7], as well as devices with low internal loss values [72]. However, the lack of proper heat-sinking has limited the analysis of these devices to p-side up testing at room temperature, and any CW measurements have been taken at low drive levels only slightly above threshold. As was outlined in Chapter 3, a significant portion of this work was directed toward developing the processes required to properly heat-sink devices for further testing. The results outlined in the following sections represent the first successful demonstration of HIC RWG p-n laser diode fabricated via the OENSO process operating p-side down, bonded to a heatsink, on a temperature controlled stage. 84

102 7.1.2 Pulsed Testing Using the fabrication process outlined in Section 3.4 straight waveguide devices have been fabricated at 3 separate active region widths (w=4.75 μm, w=5.75 μm, w=6.75 μm). Devices are initially tested p-side down on a gold plated copper block under pulsed excitation with a duty cycle of approximately 2% (2 μs on, 100 μs off) using a Keithley 2520 pulsed laser diode testing system. This is the first demonstration of HIC RWG lasers fabricated using the OENSO process p-side down, a new capability enabled by the double trench laser process. Figure 7.1 shows the output power from a single facet vs. drive current for typical devices at each width. Figure 7.1. Sample L-I curve for a L=790 μm, w=6.75 μm laser tested p- side down under pulsed (2% duty cycle) excitation. 85

103 These three devices exhibited threshold currents of 21.6 ma, 18.9 ma, and 21.5 ma with single facet slope efficiencies of W/A, W/A, and W/A for w=4.75 μm, w=5.75 μm, and w=6.75 μm stripe widths, respectively. Assuming equal output power from both facets, these slope efficiencies equate to external differential quantum efficiencies of η ext =68.51%, 66.01%, and 65.73%, respectively, for the three stripe widths. The highest external efficiency measured is η ext =75.95% for a w=6.75 μm device of length L=793 μm. Our group has previously reported a w=7 μm, L=452 μm device fabricated using the same material with an external efficiency of η ext =78% [31]. Due to the inverse relationship between length and external efficiency, we find by extrapolation of the data from this reference that the reported device of the same cavity length (L=793 μm) would have an efficiency of η ext =61%. This indicates an approximately 25% relative improvement in efficiency for the ICP-RIE etched device in this work over previous devices fabricated using standard RIE etching CW L-I Measurements After initial pulse testing, several laser die were mounted p-side down to AlN submounts coated with Au 0.80 Sn 0.20 solder using a WestBond model 7300 eutectic die bonder. Once the laser die are bonded to the submounts, the submounts themselves are then mounted to gold plated copper c-blocks using a small preform of indium foil using the process outlined in Appendix B. These devices can then be attached to an ILX Lightwave Model 4409 laser diode mount with an integrated thermo-electric cooler (TEC). The use of a TEC allows for the devices to be run CW at higher drive levels than previously achievable for unmounted devices tested p-side up. Figure 7.2 shows the 86

104 characteristic L-I curve for a single device operated pulsed at 2% and 50% duty cycles, as well as under CW excitation with the TEC operating at 15 C. Figure 7.2. Sample L-I curve for a L=790 μm, w=6.75 μm laser tested p- side down under pulsed (2% and 50% duty cycle) as well as CW excitation. The near agreement of these three curves indicates very efficient removal of heat from the active region of the device. Additionally, the CW curve indicates negligible thermal-rollover up to 200 ma of drive current (~8 times threshold). This indicates a distinct improvement over previous unbounded p-side up testing, where complete thermal rollover occurred at ~5 times the threshold current for similar devices [31]. It should be noted that the output power indicated by this curve is reduced to approximately two times below the true output power of the device due to the detector being placed further from the output facet of the heat-sunk device in the present test setup than in the case of the 87

105 unmounted device. This difference is due to a limitation on the proximity of the detector to the output facet for devices mounted n-side up to the LDX 4409 laser diode mount and contacted using a standard probe tip. This can be eliminated in future tests through the use of gold wire bonds between the die and an isolated test pad on the c-block package Temperature Dependent Measurements By tuning the temperature of the TEC during testing, the characteristic temperature, T 0, of devices can also be determined. This measure comes from the equation for threshold current density from Ref. [38]: T J th = J 0 * exp Eq. 7-1 T0 where J th is threshold current density, T is temperature, and T 0 is the characteristic temperature. Solving for T 0 we obtain the following expression: T T0 = Eq. 7-2 ln( ) J th From this equation, we can see that for a higher T 0 there is less change in the threshold current density over a given temperature range, and thus less temperature instability in the device. Experimentally we can determine T 0 by determining the threshold current density for a given device at various temperatures. The slope of a linear fit of the natural log of these threshold current densities versus temperature will then provide 1/T 0. Figure 7.3 contains sample L-I curves for such a device at temperatures ranging between 15 C and 30 C (the upper limit of the current TEC) for a w=4.75 μm, L= 0.85 mm device under CW excitation. After the determination of the threshold 88

106 current density at each temperature linear fitting was completed, as shown in Figure 7.4. This fitting procedure indicates a characteristic temperature of T 0 =179.4 C. This value for T 0 compared favorably with values found in the literature, with reported values ranging from 128 C to 185 C for λ=808 nm devices [73-75]. Figure 7.3. CW L-I curves for a w=4.75 μm, L=0.85 mm device for various TEC temperatures. 89

107 Figure 7.4.Threshold current density vs. TEC temperature for a w=4.75 μm L=0.85 mm device with a characteristic temperature of T 0 =179.4 C CW Spectral Characterization Proper heat-sinking of devices also allows for spectral characterization of these laser diodes at higher drive levels than previously achievable. Figure 7.5 shows the output spectra for a single w=6.75 μm device at three different CW drive levels. At 1.9 times threshold a side-mode suppression ratio (SMSR) of 15 dbm is seen, which increases to ~24 dbm at 2.8 times threshold. This agrees with previous results showing single spectral mode performance with SMSRs greater than 20 db at up to 3 times threshold [31]. However, at higher drive levels (not achieved in the previous work with unbonded devices) we see several spectral modes present which are not evident in the spectra from lower drive levels. This indicates that, at least at this device width, the spectral performance degrades with increasing pump power. 90

108 Figure 7.5. Output spectra for a w=6.75 μm wide device at CW drive currents of I=1.9, 2.8, and 4.2 times threshold current at 15 C Thermal Impedance Measurements In addition to analysis of the spectral characteristics of devices at higher drive levels, it is also possible to determine the thermal impedance (or thermal resistance) R th of devices. This is accomplished using the wavelength nulling technique first proposed by Paoli [76]. In this technique spectral characteristics, specifically the peak emission wavelength, are determined as a function of temperature for a given device under both pulsed and CW operation. The thermal impedance is then determined using the following equation: T = R * P Eq. 7-3 CW th CW 91

109 where ΔT CW is the required temperature shift the peak emission wavelength under CW operation to the peak wavelength seen under pulsed operation, R th is the thermal impedance, and P CW is the total power that must be dissipated (total electrical input power minus optical output power). Low duty cycles are chosen for the pulsed measurements in order to minimize heating in the device. For the measurements presented here a duty cycle ~5% (5 μs on, 100 μs off) is used. Drive currents just above threshold and at approximately two times threshold are used for CW measurements. Figure 7.6 shows the temperature dependence of the spectra for a w=4.75 μm, L=1.25 mm device with a CW drive current of 40 ma (1.33 times threshold). From this figure we see a wavelength shift of approximately Δλ=0.22 nm/ C. Figure 7.6. Output spectra for various TEC temperatures for a w=4.75 μm, L=1.25 mm device with a CW drive current of 40 ma (just above threshold). 92

110 Figure 7.7 contains the peak wavelength versus TEC temperature for the data in Figure 7.6 taken at I=40 ma drive current for both pulsed (5% duty cycle) and CW excitation. From this figure we see that a temperature shift of 6.65 C is required to null the wavelength shift relative to the peak wavelength under pulsed excitation. The total electrical power delivered to the device was 69.9 mw with an optical output power of 8.21 mw. These values correspond to a thermal impedance of R th =107.8 C/W. Figure 7.7. Peak wavelength vs. TEC temperature for a w=4.75 μm, L=1.25 mm under pulsed (5% duty cycle) and CW excitation. Placing this result into context, a comparable commercially available device is the 54xx Series single mode diode laser available from JDSU. This device has a specified thermal resistance of 60 C/W for a 3 μm emitter operating at λ=808 nm, approximately 50% lower than the devices in this work. However, as this is a commercially available 93

111 device, it is likely that it has been bonded to its heatsink using a highly optimized bonding procedure not available in the current work. Additionally, it should be noted that thermal impedance has been found to be very dependent on ridge width [77, 78], with values reported in the literature for longer wavelength lasers (λ=1.3 μm) of between 50 C/W and 200 C/W for devices varying in width from 1 to 5 μm. It is expected that a HIC RWG structure can potentially have a lower thermal resistance than was found in this experiment due to the close proximity of the active region to the metal contact on the sidewalls of the ridge. The reason why this has not yet been accomplished can be explained by examining the currently realized structure. Looking in the lateral direction, heat must first flow through the semiconductor, which is a relatively poor thermal conductor with thermal conductivities ranging between W/K-cm and 0.15 W/K-cm for the AlGaAs compounds found in this structure [79]. It must then flow through the oxide, which has a thermal conductivity which has yet to be determined, and then into the metal contact which has a high thermal conductivity of >3 W/K-cm [80]. However, this layer is presently relatively thin, and in the lateral direction, the next material is either the AuSn solder, which has a thermal conductivity of 0.57 W/K-cm [77], or in the case of a void in the solder, air which has a thermal conductivity well below 0.1 W/K-cm [80]. As will be discussed further in the next section, using a thick, electroplated gold layer (high thermal conductivity material) to fill the trench on either side of the active ridge should help to significantly lower the measured thermal impedance. 94

112 7.1.7 Proposed Improvements Several improvements are needed in order to optimize the performance of devices which are bonded p-side down to AlN submounts. As discussed in Section 3.7 a known issue in the quality of the AuSn on the AlN submounts used in this work caused devices to release from the submount during the subsequent testing and handling after bonding. This issue is being addressed through the acquisition of new submounts which have been shown to be more reliable by Innovative Photonic Solutions, Inc., in their work with commercially packaged diode lasers. The implementation of a thick, electroplated, gold layer on the p-side of devices will also improve both device performance and the yield in bonding laser devices. If properly electroplated, the trench on either side of the active laser ridge will fill with gold, and this will help to eliminate any voids between the metal contact and the solder on the submount. In addition to an improvement in the thermal properties, adding a thick layer of gold (2-4 μm) will also increase the yield in bonding devices. The shorting of devices bonded p-side down due to solder wicking up the edge of the chip and making contact to the n-type epi-layers or substrate on the output facet of the device is well known. Currently the active region is only ~2 μm from the top surface of the chip when bonded p-side down, which is easily shorted by even thin (1-3 μm thick) solders. Adding a thick gold layer will effectively move the active region several microns higher from the solder, and thus make shorting of the solder to the n-type substrate much less likely. It should be noted that if this approach is chosen for future work, two slight adjustments must be made to the fabrication process to accommodate the thick gold layer. Before the electroplating step, a masking process must be completed which leaves 95

113 channels open to facilitate the cleaving of devices. A thick photoresist, such as the SPR220-7 that is already used during the fabrication of double trench devices, must be used. Secondly, it is recommended that after electroplating, an additional Ti/Pt/Au contact layer should be evaporated onto the top of the thick gold layer. The platinum in this second contact will act as a diffusion barrier that will keep the thick gold layer from melting into the AuSn solder and altering the 80%/20% stoichiometric ratio. Finally, for future fabrication runs of double trench devices it is suggested that after removing the SiN x layer from the top of the support mesas on either side of the laser ridge that the GaAs cap layer be removed using a selective wet etch. Removing this layer will expose the Al 0.6 Ga 0.4 As upper cladding layer, which will oxidize much more readily than the GaAs. While the GaAs on the top of the support mesas does oxidize at 450 C, the typical oxidation temperature for the devices used in this work, this temperature is higher than the optimum oxidation temperature of 420 C for GaAs [6]. Images of the oxidized GaAs on top of the support mesas, such as in Figure 7.8, reveal an oxide with grainy, non-uniform color when compared to the Al 0.6 Ga 0.4 As found at the bottom of the trench. Removing the GaAs cap from the support mesas will have minimal effect on the structural support provided by the mesas (introducing only a 200 nm height difference) but will result in a thicker, more electrically insulating AlGaAs oxide being formed on the top of the support mesas. 96

114 Figure 7.8. Optical micrograph of an oxidized (450 C, 30 min, 0.4% O 2 /N 2 ) double trench laser structure. 7.2 Teardrop shaped lasers Previous work with curved devices has shown that the OENSO process is capable of creating half racetrack ring resonators (HR 3 ) with extremely tight bend radii, r<6 µm [4]. Further work has shown that decreasing the width of the waveguides used can significantly reduce the loss introduced by the transitions between straight and curved sections of a device [10]. This loss is caused by mode conversion at the transition due to differences in modal profile between the straight and curved sections. A more detailed explanation of this effect can be found in Ref. [13]. As a solution to this problem, the use of a matched bend design [81, 82] can help to reduce or eliminate this modal mismatch and thus reduce the overall loss of the curved resonator. The concept of the matched bend is based on the beating behavior of the mode within a bent section, or the fact that the location of the peak of the guided mode moves in relation to the center of the guide as it propagates, or beats. This beating behavior is 97

115 proportional to the width and radius of the structure by the factor w 3 /R [13], which ideally should be kept as low as practically possible. Due to the cubed nature of the width in this relationship, a small decrease in the width of the waveguide can result in a large decrease in the bending radius. This is the impetus for shrinking the waveguide width as much as possible for curved waveguides. In order to take advantage of the unique ability of the HIC RWG fabricated via the OENSO process to tightly confine, and therefore tightly curve light, teardrop shaped resonators were fabricated using the matched bend design discussed above. A schematic of this device can be seen in Figure 7.9. Teardrop shaped resonators also have the desirable aspect of eliminating the rear facet of a traditional Fabry-Perot laser cavity with reflectors formed by cleaving. While the specifics of the device design, which was completed by Mr. Wangqing Yuan of the University of Notre Dame, have been presented elsewhere [12, 13], the fabrication was completed using the process developed in this work, and outlined in Section 3.3, and thus the results will be included here. Figure 7.9. Teardrop geometry utilizing a matched bend design. From Ref.[12]. 98

116 The only change to the standard fabrication procedure outlined in Chapter 3 is the use of electron beam lithography to define the teardrop pattern. After the completion of the fabrication process, a single output is formed via cleaving and devices were subsequently pulse tested p-side up. Figure 7.10 contains a pulsed L-I curve and a spectra (inset) for a completed device. The device illustrated in this figure had a threshold current of I th =43 ma and a slope efficiency of R d =0.465 W/A (η d ~30%) which was an improvement over previous researchers low index contrast devices, which had a representative threshold current of 127 ma and efficiency of η d ~15% [83]. This is also an improvement over a previous teardrop design utilizing long, gradual s-bends fabricated at the University of Notre Dame, which exhibited a threshold current of 55 ma (a threshold current density of 550 A/cm 2 ) and a slope efficiency of W/A (η d ~23%) [11]. Figure L-I curves for a teardrop shaped laser utilizing the matched bend design with a threshold of I th =43 ma and a slope efficiency R d of W/A. From Ref. [12]. 99

117 7.3 Lasers with etched facets All lasers require the creation of a resonant cavity in which photons can interact with a gain medium. In the current generation of edge emitting lasers, it is often taken for granted that III-V semiconductors are readily cleaved along (110) crystal planes, making it a trivial matter to fabricate perfect, or near perfect, output facets on laser waveguides that are aligned perpendicular to this plane. The obvious downside of this simple technique is that it severely limits the geometry of the device by forcing the chip containing the lasers to be the length of the resonant cavity. This method also forms two identical facets for a single device, meaning 50% of the output power escapes at each end of the chip. Two optical coatings (anti-reflective (AR) and highly-reflective (HR)) are typically applied to the facets in order to make a single output device. These coating processes, while effective, add to the fabrication time and the cost of finished devices. To eliminate the dependence on cleaved facets, many processes for etching facets have been designed that utilize wet etching [84, 85] or various dry etching techniques such as ion beam etching (IBE) [86], chemically assisted ion beam etching (CAIBE) [87], RIE [88], and ICP RIE [89]. These techniques have been shown to create high quality facets with reflectivities as high as 28% and scattering losses as low as 3% [85] and can be reliable to high output powers (e.g., 5 W from a 100 µm wide aperture after facet coating [90]). However, with the exception of the work by Shieh et al. in which a CAIBE etched facet was passivated using an anodic oxide and then metalized to form a high reflector [91], each of these techniques still require a separate step to create an HR coating on one 100

118 of the facets. The use of anodic oxidation for this purpose is also limited in its application for optical coatings due to the formation of a terminal oxide of t~75 nm [91], which is not suitable for desired coating thicknesses which are typically a multiple of λ/4n in thickness. The flexibility of the OENSO process to grow any desired oxide thickness makes it very suitable for this purpose. Additionally, many, including the work by Shieh et al., require multiple etch and lithography steps to define the laser ridge and the facets separately. Using the self-aligned process outlined in Section 3.3 a single output laser device has been realized which eliminates these drawbacks Fabrication The fabrication of lasers with an etched and metalized high reflector and a cleaved output facet is nearly identical to the standard self-aligned process outlined in Section 3.4. One alteration is found during the p-side metal contact deposition. During this step care is taken to angle the etched facets toward the metal source to ensure complete metallization of the facet. Figure 7.11 shows an edge-on SEM image of the completed facet on a w=2.9 µm (4 µm mask width) ridge waveguide. 101

119 Figure SEM image of the metalized facet of a w=2.9 µm active core waveguide Results Two sets of devices with one etched and metalized facet and one cleaved output facet have been fabricated and tested. One set was fabricated using RIE etching and the other with ICP etching. The RIE etched devices did not lase during testing, indicating too much roughness at the etched facet, and will not be discussed further. The devices with ICP-RIE etched facets did lase during testing, and will be outlined in the following sections. All devices were initially pulse tested p-side up at an ~2% duty cycle. Some devices were then tested CW p-side up for further characterization. Figure 7.12 shows pulsed and CW L-I curves of a w=2.9 µm wide device (w=4 µm mask width). The threshold current of the device was 30 ma under pulsed excitation and 33 ma under CW excitation. The thermal rollover seen in the device at ma CW drive current indicates the need for proper heat sinking, such as that outlined in Section 7.1, before characterization can be completed to higher drive currents. 102

120 Figure L-I of a typical w=2.9 µm device tested pulsed and cw. Inset shows a linear spectrum of a similar device with a peak wavelength of nm and a SMSR of ~20 db from Ref. [92]. The device exhibited an external differential quantum efficiency of η d =17.7% from the cleaved output facet. The inset of Figure 7.12 is a linear scale spectrum taken on a similar device under cw excitation at ~3X threshold. It shows single mode operation with a peak wavelength λ=808.6 nm and a SMSR of 20 db. Similar devices had SMSRs of up to 30 db Fabrication Issues Several issues arose during the fabrication of the ICP-RIE etched lasers. The first issue was the final shape of the facet after etching. Due to non-idealities in the lithography (improper calibration of the exposure time) and erosion during etching, the 103

121 corners of the ridges became rounded. This became more of an issue as the ridges become narrower. Figure 7.13 shows top view SEM images of the facets of 4 µm and 8 µm wide devices at and 5000 times magnification, respectively. One can see that the facet of the 4 µm device has only ~1.5 µm that is completely perpendicular to the propagation direction versus almost 5 µm for the 8 µm device. Any power reflecting outside of this small area will most likely scatter into unguided modes and be lost. For future devices, more care must be taken to avoid rounding of the end facets through more careful lithography and optimized etching. Figure Top view SEM images of a 4 µm and 8 µm wide etched facets at and 5000X respectively. Another processing issue which occurred during the initial fabrication run was the improper thickness of the insulating oxide grown on the etched facet. As with any highly reflective coating the thickness of this layer should be a multiple of λ/2n, a half wavelength in the material, or nm for λ=808 nm light in the oxide (n ox ~1.6). 104

122 Figure 7.14 shows a cross section perpendicular to the propagation direction of a 90 µm wide device, which essentially replicates the facet of a narrower device. From this view we can see that t~350 nm of oxide was grown on the rear laser facet. Figure Cross section view of oxide thickness on the etched facet. Solid and dashed lines represent the location of the graded region and quantum well respectively. Figure 7.15 shows the calculated percentage of power reflected from the facet versus the thickness of the insulating oxide. The calculation has been done for both an ideal 100% reflecting metal mirror and a 91.7% reflecting mirror. The 91.7% factor was chosen based on a variable angle spectroscopic ellipsometry (VASE) simulation of a Ti/Au metal stack similar to that used in the present fabrication. The maximum reflectance calculated for devices with a 350 nm thick oxide layer (as was grown on the 1 st generation devices presented here) is only ~45%, assuming no absorption loss in the metal and no scattering loss at the oxide/metal interface. A more realistic assumption 105

123 with some absorption loss at the mirror results in less than 40% reflection at the facet. On future devices the oxidation time must be controlled so that a film with a thickness corresponding to optimum reflectance is achieved. Figure Calculated reflectance value of the etched facet versus oxide thickness for 100% and 91.7% reflecting metal mirrors Future Work In addition to addressing the fabrication issues outlined above, some process improvements can also be made to allow for both the front and rear facets of a device to be etched and oxidized. If a procedure for selectively removing the OENSO grown oxide can be developed, the etched facet process could be used to fabricate a device with an etched output facet with a thermally oxidized AR coating and an etched, oxidized, and metalized rear facet. This etch could allow for the growth of a λ/2n thick oxide, corresponding to a highly reflective optical coating, on both etched facets of the device. 106

124 The oxide on the front (output) facet could then be selectively removed to create a λ/4n thick oxide, resulting in an antireflection coating. 7.4 Conclusions In conclusion, the first demonstration of HIC RWG lasers fabricated using the OENSO process operating p-side down on a temperature controlled stage has been made. These deeply etched devices have thermal impedances as low as R th =107 C/W with characteristic temperatures as high as T 0 =180 C. External efficiencies as high as η ext =76% have been achieved, which represents a 25% improvement over lasers fabricated using RIE etching. This work, combined with the implementation of the suggested future work, should yield reliable, high performance devices which are suitable for further characterization. Additionally, novel devices which are more suitable for integration into photonic integrated circuits, including teardrop shaped lasers utilizing a matched bend design and lasers with an etched, oxidized, and metalized rear facet, have been demonstrated. 107

125 CHAPTER 8: OXIDATION OF InGaAs COMPOUNDS ON InP 8.1 Background In the field of optoelectronics, InP based alloys find many useful applications, particularly at telecommunications wavelengths for lasers and photodiodes, and at much longer wavelengths with the recent emergence of quantum cascade lasers (QCLs) operating in the mid-infrared (mid-ir). However, the Al free InGaAs relatively lower Al content of Al x In 1-x As alloys that are lattice matched to InP are difficult or impossible to oxidize by conventional methods at practical process temperatures. As outline in Chapter 2, several methods for oxidizing InAlAs and InGaAs have been explored in an attempt to overcome this limitation, including UV ozone oxidation [93], liquid phase oxidation [18], anodic oxidation [15], and plasma oxidation [16]. As part of this work, the use of the OENSO process was first reported for use in the fabrication of a QCL laser operating at λ=5.4 μm [8]. Since that report, progress has been made in growing more uniform thermal oxides on In 0.53 Ga 0.47 As through the use of a silicon cover piece in direct contact with the sample during thermal oxidation. 108

126 8.2 Initial Oxidation and Device Studies With the thermochemical evaluation found in Section 2.2 as a basis, an attempt was first made to thermally oxidize the waveguiding and active regions of a standard quantum cascade laser structure similar to that found in Refs. [94, 95], with an output wavelength of λ=5.4 µm. This structure consists of a 4.1 µm thick upper InP layer and a 30-stage, 1.53 µm thick, active core region consisting of compressively-strained In 0.6 Ga 0.4 As wells and tensile-strained In 0.44 Al 0.56 As barriers sandwiched between 0.33 µm thick In 0.53 Ga 0.47 As waveguide layers latticed matched to the InP substrate. This structure can be seen in Figure 8.1. Epitaxial growth is completed at 638 C using metal organic chemical vapor deposition on nominally exact (001) InP substrates at the University of Wisconsin-Madison. Initial oxidation test samples, such as the one shown in Figure 8.1, are fabricated by first depositing a 200 nm thick SiN x layer to act as an etch mask. This layer is then patterned into stripes using standard photolithography and reactive ion etching. A two step wet etching process consisting of a hydrochloric - phosphoric acid solution to etch through the upper InP layer is followed by a citric peroxide etch to expose the InGaAs waveguide layers and active region. This test process results in the undercut ridge profile seen in the figure. After etching, samples are oxidized at 500 C with 0.7% O 2 added relative to the N 2 carrier gas, which is bubbled through 95 C deionized H 2 O. This oxidation step forms a relatively uniform ~250 nm thick oxide on the ridge sidewall, as seen in Figure 8.1. Note that in the OENSO process, the InP cladding layer does not show any signs of oxidation, most likely because a mechanism for P removal similar to the As removal process detailed in Section 2.2 does not occur under these conditions. 109

127 Figure 8.1. SEM cross section of an InP QCL heterostructure oxidation test sample after non-selective oxidation at 500 C for 4 hours. In order for this oxidation process to be applied to a working QCL device the fabrication process was altered to remove the undercut present in Figure 8.1. To accomplish this, the citric peroxide etch is replaced by an HBr:H 2 O 2 :H 2 O solution to avoid the undercutting of the active ridge so that uniform metallization layers can be deposited for device contacts. After etching, samples as shown in Figure 8.2 were oxidized for 8 hours, twice as long as the test sample show in Figure 8.1, at 500 C with 0.7% O 2 added relative to the wet N 2 carrier gas. Oxidation results in ~350 nm of oxide growth in the field between devices (inset of Figure 8.2) and ~500 nm of oxide growth on the active region sidewalls (not shown). Metallization consists of Ti/Au and AuGe/Ni/Au contacts deposited on the top and back side of the devices, respectively. This fabrication process resulted in a device with a ridge height of ~4.9 μm and a ridge width of ~17.5 μm, as shown in the SEM cross section (Figure 8.2). 110

128 Figure 8.2. SEM cross section of native oxide confined laser ridge before metallization. Inset shows thickness of oxide formed in the field between devices. Devices are then cleaved and mounted epi-side up to copper submounts using silver epoxy. Testing is completed under pulsed operation at room temperature and compared to conventional devices (fabricated using a deposited dielectric) fabricated on similar material. An L=3 mm, w=19 µm QCL device with uncoated facets fabricated with the OENSO process has a threshold-current density of J th =3.2 ka/cm 2 for a device, an increase of 33% over similar conventionally processed ridge-waveguide QCL devices with a threshold of J th =2.4 ka/cm 2. Due to non-uniformities in the etch depth of the HBr solution, the ridge profile was intentionally under-etched to allow for sufficient material in the field between devices for oxidation; approximately 0.7 µm of the active core region (i.e., ~ 14 stages) is left un-etched in the native oxide confined devices. After oxidation, resulting in ~0.35 µm of field oxide as well as ~0.35 µm of remaining active region, as seen in the inset of Figure 8.2, leading to significant current spreading adversely affecting the device performance. A corresponding decrease is also seen in the slope efficiency of these devices, which is η s =0.08 W/A per facet for the OENSO devices and η s =0.20 W/A 111

129 per facet for conventional devices. A P-I-V characteristic for a native oxide confined device is shown in Figure 8.3, with a representative spectrum shown in the inset. Figure 8.3. P-I-V characteristics of native oxide confined QCL device. Inset shows a representative linear spectrum. 8.3 Optimization of Oxidation Conditions While these results represent the first demonstrated application of the OENSO to the fabrication of QCL devices, considerable improvement in both oxide quality and uniformity is still desired. Figure 8.4 contains optical microscope images of early InGaAs oxides. For the fabrication of the QCL devices, the oxide uniformity was improved over initial test samples (Figure 8.4, left) through the addition of a cover piece (Figure 8.4, right). However, these samples still suffered from relatively poor uniformity which affected the overall device yield. For this reason a series of studies was 112

130 undertaken to improve the overall uniformity of the thermal oxides with the goal of improved device performance. Figure 8.4. Optical microscope images of early InGaAs thermal oxides. Right: 4 hr oxidation, 525 C, 0.7% added O 2, no cover piece, Left: 6 hr oxidation, 500 C, 0.7% added O 2, InGaAs cover piece During one of these oxidation trials a silicon shim that was being used to suspend the InGaAs cover piece fell into contact with the sample being oxidized. After the completion of the oxidation it was discovered that the portion of the sample that had been in direct contact with the silicon shim grew the most visually uniform oxide over the sample. This sample is shown in Figure 8.5, with the area contained within the dotted lines indicating where the sample was in contact with the silicon shim. 113

131 Figure 8.5. InGaAs sample with silicon shim in direct contact with sample surface during oxidation, indicated by dotted lines. Generally, the use of a cover piece during the oxidation of III-As based compound semiconductors is thought to provide an overpressure of arsenic above the sample during oxidation. At elevated temperatures, the GaAs is known to dissociate and free As leaves the system. When an As bearing cover piece is used, typically suspended tens of microns or more above the surface, As dissociates from both samples. This process causes a buildup of As in the volume between the two samples, creating an overpressure of As which in turn is thought to slow the diffusion of As from the sample. When a silicon cover piece is used in direct contact with a III-As bearing sample, a very small volume is formed between the sample and the silicon, on the order of a few microns, caused by the natural surface roughness of the two samples and/or the presence of particulates on one of the two surfaces. During the oxidation, As that dissociates from the III-As sample fills this small volume, allowing the sample to create its own 114

132 overpressure. It is noted that there are many processes occurring simultaneously in the volume between the sample and the cover piece during the oxidation: process gasses (N 2, O 2, and H 2 O vapor) must still enter this volume to drive the oxidation reaction forward, As leaves the sample (either due to the As removal reaction outlined in Equation 2-7, or through thermal dissociation), and other products of the reaction must also leave the volume. Complete analysis of the chemical reactions and fluid dynamics of this process are considered to be outside of the scope of this work, thus only the results of this process will be discussed herein. For the sample seen in Figure 8.6, half of the sample was covered using a silicon sample, and the other half was left uncovered. The sample was oxidized at 475 C for 12 hours with 0.5% of oxygen added relative to the nitrogen carrier gas. As seen in the figure, there is a large difference in the uniformity of the oxide when comparing the covered area to the uncovered area. There was also a large difference in the oxide thickness between the two areas of the sample. Surface profile measurements, made after patterning and stripping away the oxide, reveal a thickness of 350 nm in the covered area with only 200 nm of oxide in the area of the sample that was uncovered. 115

133 Figure 8.6. InGaAs sample oxidized with (upper right, t=350 nm) and without (lower left, t=200 nm) Si cover piece in direct contact with the sample. This difference in uniformity and thickness also affected the insulating properties of the film. Capacitors with 120 μm inner and 1.2 mm outer contacts (Figure inset) were fabricated on the sample shown in Figure 8.6. The results of current leakage measurements performed on these devices are shown in Figure 8.7. These results indicate that the oxide in the area which was covered during oxidation provides an approximately 2 order of magnitude reduction in the leakage current density when compared to an uncovered sample oxidized under the same conditions. 116

134 Figure 8.7. Leakage current density vs. applied bias voltage. Inset: Optical image of capacitor fabricated on InGaAs oxide. With the use of a silicon cover piece in contact with the InGaAs sample during oxidation, studies of the effect of temperature and added oxygen content were carried out. Figure 8.8 shows the thickness of the thermal oxide after a two hour long oxidation with varying O 2 /N 2 ratios for temperatures between 475 C and 525 C. For lower temperatures, T 500 C, the oxidation thickness saturates above 0.5% O 2 /N 2. This saturation is likely caused by an increase in the growth rate of the dense As 2 O 3 in relation to the As removal reaction (Equation 2-7). In contrast, for temperatures above 500 C the thickness of the oxide grown for a 2 hour process continues to increase up to 0.74% O 2 /N 2, which is the highest ratio achievable with the current experimental setup. At these higher temperatures the thermal dissociation of As plays an increased role, lessening the 117

135 effect of the arsenic removal process of Equation 2-7. Further research is needed to discover where this critical balance point in the reactions for InGaAs oxidation lies for higher temperature oxidations, but other work involving the oxidation of InGaAs in air (~21% O 2 ) bubbled through H 2 O [96, 97] suggests that this point may lie at higher O 2 concentrations than it does for previously studied GaAs based materials (<1% O 2 /N 2 ). Figure 8.8. Oxide thickness vs. relative O 2 content for a 2 hour long oxidation at various process temperatures. Without added O 2 no oxide growth is observed. Figure 8.9 contains the results of a study of the oxide thickness for various oxidation times at 475 C and 510 C. Linear fits of the experimental data in Figure 8.9 indicate growth rates of 34 nm/hr at 475 C and 120 nm/hr at 510 C. For both of the 118

136 temperatures included in this study, a linear growth rate is seen for the maximum oxide thicknesses achieved, which indicates that in this range the oxidation process is reaction limited. Figure 8.9. Oxide thickness vs. time for 475 C (0.5% O 2 /N 2 ) and 510 C (0.7% O 2 /N 2 ). After an initial time delay before the onset of growth, linear oxidation rates of 34 nm/hr and 120 nm/hr, respectively, are observed, indicating a reaction limited process. 8.4 Future Work Future work on native-oxide confined QCL lasers fabricated using the OENSO process should focus on developing a new etching recipe which can more accurately control the final etch depth of the ridge structure. The etch depth for devices is more 119

137 critical for devices fabricated with the OENSO process than traditionally fabricated QCL devices (deep etch and deposited dielectric) because of the resistance of InP to oxidation. To combat this issue, initial work has been completed on a two step wet/dry etch recipe for future devices. A selective wet etch (1:1 hydrochloric: phosphoric acid) is first used to etch the thick upper InP layers and define the laser ridge. This step is followed by a dry ICP-RIE etch step in an Ar/Cl 2 chemistry at elevated temperature (165 C) to etch through the InGaAs/AlInAs waveguide and active region. This second dry etch step is much more uniform and controllable than the HBr based wet etch used in the first generation of devices, and should allow for the etch to be stopped more precisely at the bottom of the active region. This will eliminate the problem of current spreading while still leaving the entire t=300 nm thick lower InGaAs waveguide cladding layer for further oxidation. Figure 8.10 shows an SEM cross section of a test profile fabricated using this new etch. This sample was only etched ~0.5 μm into the QCL active region, however it still demonstrates the suitability of the new etch recipe. At the time of this writing, fabrication of a new set of QCL devices using the etching and oxidation process improvements demonstrated here is awaiting the growth of new QCL material by our collaborators at the University of Wisconsin, Madison. These process improvements are expected to dramatically improve yield and performance of these novel native-oxide confined quantum cascade lasers. 120

138 Figure SEM image of shallow etched QCL ridge fabricated using a two step wet/dry etch recipe. 8.5 Conclusion In conclusion, a first demonstration of the OENSO process in the InGaAs/InP material system has been made. Through the use of a silicon cover piece in direct contact with a sample during oxidation improvements have been made in both the overall uniformity and insulating properties of the new oxide. As a proof of the efficacy of this oxide for use in optoelectronics applications a novel native-oxide confined quantum cascade laser operating at λ=5.4 μm has been demonstrated. Finally, a new two step wet/dry etching process has been developed which is more compatible with the fabrication process for these native-oxide confined devices. 121