Progress in Monolithic III-V/Si and towards processing III-V Devices in Silicon Manufacturing. E.A. (Gene) Fitzgerald

Transcription

1 Progress in Monolithic III-V/Si and towards processing III-V Devices in Silicon Manufacturing E.A. (Gene) Fitzgerald M.J. Mori, C.L.Dohrman, K. Chilukuri MIT Cambridge, MA USA Funding: MARCO IFC and Army Research Office

2 Barriers Historic challenges (and solutions) to monolithic (i.e. single-wafer) CS-CMOS integration Physical Lattice-mismatch GaAs direct growth on Si ρ t ~ cm -2 InP direct growth on GaAs ρ t ~ cm -2 Dislocation engineering, composition-graded ( ) SiGe and InGaAs layers Unknown dislocation density requirements for different materials and applications Default position=material must be perfect layers and new materials=prototypes defined required dislocation levels Thermal Expansion ΔaΔT between CS and Si may crack films Patterned growth, layer transfer of new lattice constants

3 Barriers Si CMOS Compatibility Problem to achieve co-planar CS and CMOS CS contamination Thermal budget compatibility between CS and CMOS Silicon on Lattice-Engineered Silicon (SOLES) and Sifront-end-first process integration Economics and Access Divided industrial structures Silicon mm, mature CS, mm, mature Business models High volume, low cost Low volume, low-to-high cost wafer-size-migration business model

4 CMOS-III-V Integration Platform: Silicon on Lattice-Engineered Substrate (SOLES) SOLES is a platform for coplanar integration No large height differences on front-end Allows use of conventional back-end to interconnect electrically By burying the Ge layer, this wafer can be processed similarly to a standard SOI wafer Si on top, Si on back After front-end CMOS processing, GaAs device layer can be accessed by etching through Si device layer and buried SiO 2 layer Can be fabricated using standard semiconductor processing Si device layer Buried SiO 2 Buried Ge Si 1-x Ge x Graded Buffer Si substrate

5 MOS detector Front-end CMOS Fabrication III-V template Si substrate III-V laser/led Layer Growth III-V template Si substrate III-V Device Layer Fabrication III-V template Si substrate Silicon IC Back-end Processing (inter-level dielectric not shown) III-V template Si substrate

6 Elements of Si-compatible Interconnect SOLES substrate III-V visible emitter on lattice between that of Si and Ge Silicon-processing of III-V optical device

7 Basic SOLES Process Overview Starting Materials: Si donor wafer, Ge virtual substrate handle wafer SiO 2 layer is deposited on handle wafer and planarized by CMP Thin SiO 2 layer will be thermally grown on handle to isolate bond interface from Si device layer H + 2 implant of donor SiO 2 -SiO 2 bonding (NH 4 OH-H 2 O 2 -H 2 O pre-clean) Layer exfoliation by two-step anneal (250 o C and 450 o C) Removal of exfoliation damage by CMP H + Exfoliation damage Bond interface CMPed LPCVD SiO 2 Ge cap Si Donor wafer Si 1-x Ge x Graded Buffer Si handle wafer

8 SOLES Fabrication Results Whole wafer coverage after 30sec CMP Most exfoliation damage removed by CMP, but some damage still seen in TEM exfoliation damage transferred Si Buried SiO 2 Si 0.04 Ge 0.96 cap Graded Si 1-x Ge x 500nm 150mm SOLES wafer Cross-sectional TEM

9 AlInGaP Quaternary Alloys 2.5 AlP Indirect GaP Band Gap (ev) GaAs Direct InP 1 Si InAs Ge Lattice Constant (Å) Vurgaftman, Meyer and Ram-Mohan, Journal of Applied Physics, 89 (11), 5815 (2001) Previous InGaP grade work by L. McGill, A. Kim, T. Chin et. al. and L. Stinson et. al.

10 SQW Heterostructure E c E v, n p-in.29 (Al.3 Ga.7 ).71 P n-in.29 (Al.3 Ga.7 ).71 P n-virtual Substrate Uniform Cap p + -In.29 Ga.71 P u-in.29 Ga.71 P u-in.29 Ga.71 P SQW aids optical and electrical confinement Gives design flexibility Strain n-virtual Substrate Graded Region Composition SQW thickness

11 Comparison of Graded Systems Threading Dislocation Density (cm -2 ) GaP InGaP GaAsP device platform GaAsP GaAs Lattice Constant (Å) InGaP data from A. Kim

12 PL from InGaP SQW

13 LED ARRAY PROCESS SEQUENCE N Ge P - SiGe N Ge 1.Dry Etch Si and Wet etch SiO 2 2.Dry etch Ge isolation Trench 3.Deposit 1.2µm PECVD Oxide 4. Wet etch Oxide growth Wells 5. MOCVD Growth of P ++ Si Capped AlGaInP LED stack on SiGe 6.Etch Polycrystalline Deposits 7. Deposit 3000A PECVD SiO 2 8. Etch Via 1 9 Sputter deposit Ti/Al and pattern

14 CMOS INTEGRATION OF III-V LED Ensure that at no point in the processing sequence the III-V material gets etched or exposed in the CMOS fabrication facility. Use CMOS compatible Contact Metallurgy instead of conventional Au based metals. CMOS Compatible Contact Metallurgy P++Si P+ GaAs SiO 2 LED Stack N GaAs N Ge SiGe/Si Si encapsulation layer to be grown In-Situ in the MOCVD reactor

15 SIMS Analysis of P ++ Si capped LED on SiGe 1E23 Concentration (atoms/cc) P+Si P GaAs P AlGaInP InGaP N AlGaInP N GaAs N Ge Si 1E22 1E21 1E20 1E19 1E18 Ge As Al 1E17 1E16 1E Depth ( µm)

16 Monolithic Visible LED Arrays on Si using SOLES and CMOS-compatible processing Silicon On LatticeEngineered Silicon (SOLES) III-V Device Epi Silicon-like processing

17 P++ Si capped AlGaInP SDH LED on Ge and SiGe 2.50E-007 SEL231 SiGe 2.00E-007 Light Output (W) 1.50E E-007 Ge 200umx200um LED on Ge driven at 30mA 200umx200um LED on SiGe driven at 30mA 5.00E E Current (A) The higher thermal conductivity Of Silicon relative to Ge causes lower heating for LED on SiGe, increasing light power output

18 Compound Semiconductor Materials on Silicon (COSMOS) Compound Semiconductors on Silicon-on-Lattice-Engineered-Substrates (CS on SOLES)

19 Monolithic III-V-Si CMOS Systems COSMOS Integration of Si CMOS with InP HBTs Monolithic=Si industry and model Wide variety of products in single fab Leverage tools (software and hardware) Design platforms Level of abstraction allows a variety of products to be created at design-level Monolithic integration is previous solution to same problem historically ( tyranny of numbers ) Si

20 Summary III-V/Si not inhibited by previous fundamental issues Silicon-on-Lattice-Engineered-Silicon (SOLES) is a substrate embodiment easing the process integration of III-V+Si CMOS Demonstrated Part of COSMOS Visible optical devices on silicon 10 4 cm -2 threading dislocations on lattice constants matched to InGaP across visible spectrum Orange, yellow, and green semiconductor lasers could become a reality Concept of Si LED with embedded III-V active has been demonstrated on SOLES platform COSMOS program may be first step on path to real monolithic III- V-Si-CMOS circuits