RELIABILITY EVALUATION QUALIFICATION OF SOIC8L Narrow & SOIC8L E-PAD XDLF-IDF (EXTREAM DENSITY LEAD FRAME) ATP1 (AMKOR PHILIPPINES SUBCON)

Transcription

1 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT6004 RELIABILITY EVALUATION QUALIFICATION OF SOIC8L Narrow & SOIC8L E-PAD XDLF-IDF (EXTREAM DENSITY LEAD FRAME) ATP1 (AMKOR PHILIPPINES SUBCON) DOCUMENT INFORMATION Version Date Pages Prepared by Approved by Comment May-2016 F.VENTURA I&PC QA&R / B/E A.PLATINI I&PC QA&R MNG. Final report Note: This report is a summary of the reliability trials performed in good faith by STMicroelectronics in order to evaluate the potential reliability risks during the product life using a set of defined test methods. This report does not imply for STMicroelectronics expressly or implicitly any contractual obligations other than as set forth in STMicroelectronics general terms and conditions of Sale. This report and its contents shall not be disclosed to a third party without previous written agreement of STMicroelectronics. 1/10

2 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT6004 General Information Product Line CRO7*U093ADZ L6561D-1HLF/ P/N L6561D13TR-1HLF/ Product Group AMG Product division Industrial & Power Discrete Package SOIC 8L.150 NARROW Silicon Process technology A3 - BCD1 Maturity level step 29 Wafer fab Assembly plant Final Reliability Assessment Reliability Lab Locations AMK6 (ANG MO KIO S PORE) ATP1-SUBCON PHILIPPINES PASSED ST-MOROCCO Document reference AEC-Q100 JESD47 ADCS: Short description Stress test qualification for automotive grade integrated circuits Stress-Test-Driven Qualification of Integrated Circuits General specification for product development 1 GLOSSARY DUT SS Device Under Test Sample Size 2/10

3 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT RELIABILITY EVALUATION OVERVIEW 2.1 Objectives TO QUALIFY NEW XDLF (EXTREAM DENSITY L/FRAME) VERS. ON SOIC8L.15O/E-PAD NARROW PKG. ATP1 SUBCON 2.2 Conclusion Qualification Plan requirements (WORKABILITY/ TESTING / CONSTRUCTION ANALISYS) have been fulfilled without exception. It s stressed that reliability tests have shown that the devices behave correctly against environmental tests (no failure). Moreover, the stability of electrical parameters during the accelerated tests demonstrates the ruggedness of the products and safe operation, which is consequently expected during their lifetime. NOTE: The present RR (RR000116CT6004) CAN BE EXTENDED to all involved AMG/I&PC tech/products assembled on SOIC8L XDLF ATP1 line DENSITY LEAD FRAME SCENARIO: NEW FRAME OLD FRAME 3/10

4 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT Construction note *U093_ P/N: L6561D-1HLF/ L6561D13TR-1HLF/ Wafer/Die fab. information AMK6 Wafer fab manufacturing location ANG MO KIO S PORE Technology BCD 1 Process family A3 BCD1 Die finishing back side CHROMIUM/NICKEL/GOLD Die size 2590,2060 UM Bond pad metallization layers Al/Si Passivation type SIN (NITRIDE) Wafer Testing (EWS) information Electrical testing manufacturing location AMK6 Assembly information Assembly site ATP1/ AMKOR PHILIPPINES Package description SOIC8L NARROW.150 Molding compound SUMITOMO EME G600 ECOPAK 2 COMPLIANCE Frame material OLIN C194 COPPER Die attach process EPOXY GLUE Die attach material HENKEL ABLEBOND 8290 Die pad size 90 X 130 mil XD IDF PN Wire bonding process THERMOSONIC Wires bonding materials/diameters 1.3 mils Au Lead finishing process Pre- plated Package code O7 Final testing information Testing location ST-BSK MOROCCO 4/10

5 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT TESTS RESULTS SUMMARY 3.1 Test vehicle *U093 Lot # 1 Diffusion Process/ Assy Lot Trace Code Product Line Lot Package V6517VN3 CZ6040C601 n/a SOIC 8L NARROW CRO7*U093ADZ Comments Detailed results in below chapter will refer to P/N and Lot #. 3.2 Test plan and results summary P/N L6561D-1HLF/ L6561D13TR-1HLF/ Test PC Std ref. Conditions Steps Note PC TC Y Y JESD22 A020-D JESD22 A-104 MSL_1 HTS C+TH 168H(85 C@85%RH)+3IR@260 Ta = -65 C to 150 C NO DELAMINATION TOP/BOTTOM 0/100 BEFORE & AFTER PRECOND. 500CY 0/ CY 0/77 In case of Automotive customer insert here the family data. In case of rejects include a short description of the failure analysis and corrective actions. 5/10

6 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT ANNEXES: MOUNT BOND DIAGRAM (MBD) 6/10

7 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT Package outline/mechanical data 7/10

8 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT6004 8/10

9 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT6004 9/10

10 AMG Analog & Mems -Group Industrial & Power Conversion Div. Quality & Reliability B-END RR000116CT6004 Tests Description Test name Description Purpose Package Oriented PC Preconditioning TC Temperature Cycling The device is submitted to a typical temperature profile used for surface mounting devices, after a controlled moisture absorption. The device is submitted to cycled temperature excursions, between a hot and a cold chamber in air atmosphere. As stand-alone test: to investigate the moisture sensitivity level. As preconditioning before other reliability tests: to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. To investigate failure modes related to the thermo-mechanical stress induced by the different thermal expansion of the materials interacting in the die-package system. Typical failure modes are linked to metal displacement, dielectric cracking, molding compound delamination, wire-bonds failure, die-attach layer degradation. 10/10

11 AMG Group RELIABILITY - CASTELLETTO RR000716CS6080 Preliminary General Information Locations Product Line Product Description Product division UK17 Step Down Switching Regulator I&PC Wafer fab location Assembly plant location Package HSOP 8L Silicon process technology BCD5-40NP Reliability assessment Pass ANG MO KIO AMKOR ATP1 PHILIPPINES DOCUMENT HISTORY Version Date Pages Author Comment Feb S.O.Cannizzaro Preliminary release Approved by Giuseppe Capodici Version 1.0 Page 1/13

12 Table of Contents AMG Group RELIABILITY - CASTELLETTO RR000716CS APPLICABLE AND REFERENCE DOCUMENTS RELIABILITY EVALUATION overview Objectives Conclusion Device Characteristics Device description Pin connection Bonding diagram Package outline/mechanical data Traceability Tests results summary Test plan and results summary of UK17 with XD lead frame strip Test plan and results summary of UK17 with HD lead frame strip Tests Description & detailed results Die oriented tests High Temperature Operating Life Early Life Failure Rate Package oriented tests Pre-Conditioning High Temperature Storage Thermal Cycles Autoclave Temperature Humidity Bias Power Temperature Cycling Electrical Characterization Tests Latch-up E.S.D Version 1.0 Page 2/13

13 AMG Group RELIABILITY - CASTELLETTO RR000716CS APPLICABLE AND REFERENCE DOCUMENTS Document reference Short description AEC-Q100 : Stress test qualification for integrated circuits : Reliability tests and criteria for qualifications Version 1.0 Page 3/13

14 AMG Group RELIABILITY - CASTELLETTO RR000716CS RELIABILITY EVALUATION OVERVIEW 2.1 Objectives This report contains the reliability evaluation of UK17 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES in the overall plan of the S08ExpPad lead frame strip change in Amkor. According to Reliability Qualification Plan, below is the list of the trials performed: Package Oriented Tests Preconditioning Temperature Cycling Power Temperature Cycling Autoclave 2.2 Conclusion Taking in account the preliminary results of the trials performed on the UK17 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES a positive judgment can be given out. To complete the evaluation the PTC trial need to be performed. Version 1.0 Page 4/13

15 AMG Group RELIABILITY - CASTELLETTO RR000716CS DEVICE CHARACTERISTICS 3.1 Device description Pin connection Bonding diagram Version 1.0 Page 5/13

16 AMG Group RELIABILITY - CASTELLETTO RR000716CS Package outline/mechanical data Version 1.0 Page 6/13

17 AMG Group RELIABILITY - CASTELLETTO RR000716CS Traceability Wafer fab information Wafer fab manufacturing location ANG MO KIO Wafer diameter 6 inches Wafer thickness 375 µm Silicon process technology BCD5-40NP Die finishing back side Cr/Ni Die size 2770x1980 µm Bond pad metallization layers AlSiCu Passivation PSG+SiON+Polyimide Metal levels 3 Assembly Information Assembly plant location AMKOR ATP1 PHILIPPINES Package description HSOP 8L Die pad size 2.413x3.099 mm Molding compound Ablebond 8290 Wires bonding materials/diameters Au/1.3 mils Die attach material Sumitomo G600 Lead solder material Sn Version 1.0 Page 7/13

18 4 TESTS RESULTS SUMMARY AMG Group RELIABILITY - CASTELLETTO RR000716CS Test plan and results summary of UK17 with XD lead frame strip Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/154 0/154 0/154 PTC Power Temperature Cycling To be On Chip Boards Tj=-40 C 150 C performed h Vcc=36V, Iout=0.7A AC Autoclave PC before 121 C 2atm 0/77 0/77 0/77 96h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/77 0/77 0/ cy Note Version 1.0 Page 8/13

19 AMG Group RELIABILITY - CASTELLETTO 4.2 Test plan and results summary of UK17 with HD lead frame strip RR000716CS6080 Die Oriented Tests Test Method Conditions Failure/SS HTOL ELFR High Temperature Operating Life PC before Tj=150 C Vcc=36V, Iout=3A Early Life Failure Rate Tj=150 C Vcc=32V, Iout=0.4A Package Oriented Tests Lot 1 Lot 2 Lot 3 Duration 0/77 0/77 0/ h h Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/308 0/308 0/308 THB Temperature Humidity Bias PC before Ta=85 C/85%RH 0/77 0/77 0/ h Pdut~0W, Vcc=20V PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C 0/ h Vcc=36V, Iout=0.7A AC Autoclave PC before 121 C 2atm 0/77 0/77 0/77 96h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/77 0/77 0/ cy HTSL High Temperature Storage No bias Tamb=150 C 0/ h Note Note Electrical Characterization Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 ESD Electro Static Discharge Human Body Model +/- 2kV 0/3 - - LU Machine Model +/- 100V 0/3 - - Charge Device - - +/- 1.5kV 0/3 Model Latch-Up Over-voltage and Tamb=125 C 0/6 - - Current Injection Jedec78 All above trials performed on ABA rev. Duration Note Version 1.0 Page 9/13

20 AMG Group RELIABILITY - CASTELLETTO RR000716CS TESTS DESCRIPTION & DETAILED RESULTS 5.1 Die oriented tests High Temperature Operating Life This test is performed like application conditions in order to check electromigration phenomena, gate oxide weakness and other design/manufacturing defects put in evidence by internal power dissipation. Initial Ta=-40 C/25 C/125 C Check at 168 and Ta=25 C Final Testing Ta=-40 C/25 C/125 C Early Life Failure Rate This test is to evaluate the defects inducing failure in early life. The device is stressed in biased conditions at the max junction temperature. Initial Ta=25 C/125 C Final Testing (24 Ta=25 C/125 C Version 1.0 Page 10/13

21 5.2 Package oriented tests AMG Group RELIABILITY - CASTELLETTO RR000716CS Pre-Conditioning The device is submitted to a typical temperature profile used for surface mounting, after a controlled moisture absorption. The scope is to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. Initial Ta=25 C/125 C. Final Ta=25 C/125 C High Temperature Storage The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature. The scope is to investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Thermal Cycles The purpose of this test is to evaluate the thermo mechanical behavior under moderate thermal gradient stress. Initial Ta=125 C. Check at 500 Ta=25 C Final Testing (1000 Ta=125 C TEST CONDITIONS: Ta= -50 C to +150 C(air) Autoclave The purpose of this test is to point out critical water entry path with consequent corrosion phenomena related to chemical contamination and package hermeticity. Initial Ta=25 C. Final Testing Ta=25 C. TEST CONDITIONS: P=2.08 atm Ta=121 C test time= 96 hrs Version 1.0 Page 11/13

22 5.2.5 Temperature Humidity Bias AMG Group RELIABILITY - CASTELLETTO RR000716CS6080 The test is addressed to put in evidence problems of the die-package compatibility related to phenomena activated in wet conditions such as electro-chemical corrosion. The device is stressed in static configuration approaching some field status like power down. Temperature, Humidity and Bias are applied to the device in the following environmental conditions => Ta=85 C / RH=85%. Input pins to Low / High Voltage (alternate) to maximize voltage contrast. Test Duration 2000 h. Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Power Temperature Cycling This test simulates typical power automotive application. The test is addressed mainly to focus die-attach and wire bonding problems in all the temperature stress changes. Combined stress performing an HTOL stress while the ambient temperature is cycling between 40 to +110 C (Tj=150 C) with the DUT switched alternatively ON/OFF (5min. each) in asynchronous mode with respect the ambient temperature change, (1 cycle: stress Temp. / 20 to change Temperature). Initial Ta=25 C/125 C Check at 168, Ta=25 C Final Testing (1000 Ta=25 C/125 C Version 1.0 Page 12/13

23 AMG Group RELIABILITY - CASTELLETTO RR000716CS Electrical Characterization Tests Latch-up This test is intended to verify the presence of bulk parasitic effects inducing latch-up. The device is submitted to a direct current forced/sinked into the input/output pins. Removing the direct current no change in the supply current must be observed. Initial Ta=25 C/125 C Latch-UP Ta=125 C Final Ta=25 C/125 C Stress applied: condition NEG. INJECTION POS. INJECTION OVERVOLTAGE IN low -100mA Inom+250mA 1.5 x VDD or MSV or AMR, whichever is less IN high -100mA Inom+250mA 1.5 x VDD or MSV or AMR, whichever is less E.S.D. This test is performed to verify adequate pin protection to electrostatic discharges. Initial Ta=25 C/125 C ESD Ta=25 C Final Ta=25 C/125 C TEST CONDITIONS: o Human Body Model ANSI/ESDA/JEDEC STANDARD JES001 CDF-AEC-Q o Machine Model JEDEC STANDARD EIA/JESD-A115 CDF-AEC-Q o Charge Device Model ANSI/ESD STM ESDA JEDEC JESD22-C101 CDF-AEC-Q Version 1.0 Page 13/13

24 RR000816CS6080 Preliminary General Information Locations Product Line Product Description Product division UK18 Step Down Switching Regulator I&PC Wafer fab location Assembly plant location Package HSOP 8L Silicon process technology BCD5-40NP Reliability assessment Pass ANG MO KIO AMKOR ATP1 PHILIPPINES DOCUMENT HISTORY Version Date Pages Author Comment May A. Spiezia Original document Approved by Giuseppe Capodici Version 1.0 Page 1/13

25 Table of Contents RR000816CS APPLICABLE AND REFERENCE DOCUMENTS RELIABILITY EVALUATION overview Objectives Conclusion Device Characteristics Device description Pin connection Bonding diagram Package outline/mechanical data Traceability Tests results summary Test plan and results summary of UK18 with XD lead frame strip Generica Data from UK Tests Description & detailed results Die oriented tests High Temperature Operating Life Early Life Failure Rate Package oriented tests Pre-Conditioning High Temperature Storage Thermal Cycles Autoclave Temperature Humidity Bias Power Temperature Cycling Electrical Characterization Tests Latch-up E.S.D Version 1.0 Page 2/13

26 RR000816CS APPLICABLE AND REFERENCE DOCUMENTS Document reference Short description AEC-Q100 : Stress test qualification for integrated circuits : Reliability tests and criteria for qualifications Version 1.0 Page 3/13

27 RR000816CS RELIABILITY EVALUATION OVERVIEW 2.1 Objectives This report contains the reliability evaluation of UK18 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification. According to Reliability Qualification Plan, considering UK18 as circuit rerouting of UK17, below is the list of the trials performed: Package Oriented Tests Preconditioning Temperature Cycling Power Temperature Cycling Electrical Characterization ESD resistance test LATCH-UP resistance test 2.2 Conclusion Taking in account the preliminary results of the trials performed on the UK18 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES a positive judgment can be given out. To complete the evaluation the PTC need to be performed. Version 1.0 Page 4/13

28 RR000816CS DEVICE CHARACTERISTICS 3.1 Device description Pin connection Bonding diagram Version 1.0 Page 5/13

29 3.1.3 Package outline/mechanical data RR000816CS6080 Version 1.0 Page 6/13

30 RR000816CS Traceability Wafer fab information Wafer fab manufacturing location ANG MO KIO Wafer diameter 6 inches Wafer thickness 375 µm Silicon process technology BCD5-40NP Die finishing back side Cr/Ni Die size 2770x1980 µm Bond pad metallization layers AlSiCu Passivation PSG+SiON+Polyimide Metal levels 3 Assembly Information Assembly plant location AMKOR ATP1 PHILIPPINES Package description HSOP 8L Die pad size 2.413x3.099 mm Molding compound Ablebond 8290 Wires bonding materials/diameters Au/1.3 mils Die attach material Sumitomo G600 Lead solder material Sn Version 1.0 Page 7/13

31 4 TESTS RESULTS SUMMARY RR000816CS Test plan and results summary of UK18 with XD lead frame strip Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/77 PTC Power Temperature Cycling To be performed On Chip Boards Tj=-40 C 150 C 1000h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/ cy Note Electrical Characterization Tests Test Method Conditions Failure/SS Lot 1 ESD Electro Static Discharge Human Body Model +/- 2kV 0/3 Charge Device Model +/- 1.5kV 0/3 LU Latch-Up Over-voltage and Tamb=125 C 0/6 Current Injection Jedec78 All above trials performed on ABA rev. Duration Note Version 1.0 Page 8/13

32 4.2 Generica Data from UK17 RR000816CS6080 Die Oriented Tests Test Method Conditions Failure/SS HTOL ELFR Lot 1 Lot 2 Lot 3 Duration High Temperature Operating Life PC before Tj=150 C 0/77 0/77 0/ h Early Life Failure Rate Tj=150 C h Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/308 0/308 0/308 THB Temperature Humidity Bias PC before Ta=85 C/85%RH 0/77 0/77 0/ h PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C 0/ h AC Autoclave PC before 121 C 2atm 0/77 0/77 0/77 96h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/77 0/77 0/ cy HTSL High Temperature Storage No bias Tamb=150 C 0/ h Note Note Version 1.0 Page 9/13

33 RR000816CS TESTS DESCRIPTION & DETAILED RESULTS 5.1 Die oriented tests High Temperature Operating Life This test is performed like application conditions in order to check electromigration phenomena, gate oxide weakness and other design/manufacturing defects put in evidence by internal power dissipation. Initial Ta=-40 C/25 C/125 C Check at 168 and Ta=25 C Final Testing Ta=-40 C/25 C/125 C Early Life Failure Rate This test is to evaluate the defects inducing failure in early life. The device is stressed in biased conditions at the max junction temperature. Initial Ta=25 C/125 C Final Testing (24 Ta=25 C/125 C Version 1.0 Page 10/13

34 5.2 Package oriented tests RR000816CS Pre-Conditioning The device is submitted to a typical temperature profile used for surface mounting, after a controlled moisture absorption. The scope is to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. Initial Ta=25 C/125 C. Final Ta=25 C/125 C High Temperature Storage The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature. The scope is to investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Thermal Cycles The purpose of this test is to evaluate the thermo mechanical behavior under moderate thermal gradient stress. Initial Ta=125 C. Check at 500 Ta=25 C Final Testing (1000 Ta=125 C TEST CONDITIONS: Ta= -50 C to +150 C(air) Autoclave The purpose of this test is to point out critical water entry path with consequent corrosion phenomena related to chemical contamination and package hermeticity. Initial Ta=25 C. Final Testing Ta=25 C. TEST CONDITIONS: P=2.08 atm Ta=121 C test time= 96 hrs Version 1.0 Page 11/13

35 5.2.5 Temperature Humidity Bias RR000816CS6080 The test is addressed to put in evidence problems of the die-package compatibility related to phenomena activated in wet conditions such as electro-chemical corrosion. The device is stressed in static configuration approaching some field status like power down. Temperature, Humidity and Bias are applied to the device in the following environmental conditions => Ta=85 C / RH=85%. Input pins to Low / High Voltage (alternate) to maximize voltage contrast. Test Duration 2000 h. Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Power Temperature Cycling This test simulates typical power automotive application. The test is addressed mainly to focus die-attach and wire bonding problems in all the temperature stress changes. Combined stress performing an HTOL stress while the ambient temperature is cycling between 40 to +110 C (Tj=150 C) with the DUT switched alternatively ON/OFF (5min. each) in asynchronous mode with respect the ambient temperature change, (1 cycle: stress Temp. / 20 to change Temperature). Initial Ta=25 C/125 C Check at 168, Ta=25 C Final Testing (1000 Ta=25 C/125 C Version 1.0 Page 12/13

36 RR000816CS Electrical Characterization Tests Latch-up This test is intended to verify the presence of bulk parasitic effects inducing latch-up. The device is submitted to a direct current forced/sinked into the input/output pins. Removing the direct current no change in the supply current must be observed. Initial Ta=25 C/125 C Latch-UP Ta=125 C Final Ta=25 C/125 C Stress applied: condition NEG. INJECTION POS. INJECTION OVERVOLTAGE IN low -100mA +60mA 1.5 x VDD or MSV or AMR, whichever is less IN high -100mA +100mA 1.5 x VDD or MSV or AMR, whichever is less E.S.D. This test is performed to verify adequate pin protection to electrostatic discharges. Initial Ta=25 C/125 C ESD Ta=25 C Final Ta=25 C/125 C TEST CONDITIONS: o Human Body Model ANSI/ESDA/JEDEC STANDARD JES001 CDF-AEC-Q o Charge Device Model ANSI/ESD STM ESDA JEDEC JESD22-C101 CDF-AEC-Q Version 1.0 Page 13/13

37 RR000916CS6080 General Information Locations Product Line Product Description Product division UT20 Step Down Switching Regulator IPC Wafer fab location Assembly plant location Package HSOP 8L Silicon process technology BCD5-40NP Reliability assessment Pass ANG MO KIO AMKOR ATP1 PHILIPPINES DOCUMENT HISTORY Version Date Pages Author Comment Jan S.O.Cannizzaro Preliminary release May A. Spiezia Final results updated Approved by Giuseppe Capodici Version 1.0 Page 1/13

38 Table of Contents RR000916CS APPLICABLE AND REFERENCE DOCUMENTS RELIABILITY EVALUATION overview Objectives Conclusion Device Characteristics Device description Pin connection Bonding diagram Package outline/mechanical data Traceability Tests results summary Generic data from UK Tests Description & detailed results Die oriented tests High Temperature Operating Life Early Life Failure Rate Package oriented tests Pre-Conditioning High Temperature Storage Thermal Cycles Autoclave Temperature Humidity Bias Power Temperature Cycling Electrical Characterization Tests Latch-up E.S.D Version 1.0 Page 2/13

39 RR000916CS APPLICABLE AND REFERENCE DOCUMENTS Document reference Short description AEC-Q100 : Stress test qualification for integrated circuits : Reliability tests and criteria for qualifications Version 1.0 Page 3/13

40 RR000916CS RELIABILITY EVALUATION OVERVIEW 2.1 Objectives This report contains the reliability evaluation of UT20 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification. According to Reliability Qualification Plan, considering UT20 as circuit rerouting of UK17, below is the list of the trials performed: Package Oriented Tests Preconditioning Temperature Cycling Power Temperature Cycling Electrical Characterization ESD resistance test LATCH-UP resistance test 2.2 Conclusion Taking in account the preliminary results of the trials performed on the UT20 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES can be qualified from a reliability viewpoint. Version 1.0 Page 4/13

41 RR000916CS DEVICE CHARACTERISTICS 3.1 Device description Pin connection Bonding diagram Version 1.0 Page 5/13

42 3.1.3 Package outline/mechanical data RR000916CS6080 Version 1.0 Page 6/13

43 RR000916CS Traceability Wafer fab information Wafer fab manufacturing location ANG MO KIO Wafer diameter 6 inches Wafer thickness 375 µm Silicon process technology BCD5-40NP Die finishing back side Cr/Ni Die size 2770x1980 µm Bond pad metallization layers AlSiCu Passivation USG-PSG-SiON-PIX Metal levels 3 Assembly Information Assembly plant location AMKOR ATP1 PHILIPPINES Package description HSOP 8L Die pad size 2.413x3.099 mm Molding compound Sumitomo G600 Wires bonding materials/diameters Au/1.3 mils Die attach material Ablebond 8290 Lead solder material Sn Version 1.0 Page 7/13

44 4 TESTS RESULTS SUMMARY RR000916CS6080 Test plan and results summary of UT20 with XD lead frame strip Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/77 PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C 0/ h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/ cy Note Electrical Characterization Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 ESD Electro Static Discharge Human Body Model +/- 2kV 0/3 Charge Device Model +/- 750V 0/3 LU Latch-Up Over-voltage and Tamb=125 C 0/6 Current Injection Jedec78 Duration Note Version 1.0 Page 8/13

45 4.1 Generic data from UK17 RR000916CS6080 Die Oriented Tests Test Method Conditions Failure/SS HTOL ELFR Lot 1 Lot 2 Lot 3 Duration High Temperature Operating Life PC before Tj=150 C 0/77 0/77 0/ h Early Life Failure Rate Tj=150 C h Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/308 0/308 0/308 THB Temperature Humidity Bias PC before Ta=85 C/85%RH 0/77 0/77 0/ h PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C 0/ h AC Autoclave PC before 121 C 2atm 0/77 0/77 0/77 96h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/77 0/77 0/ cy HTSL High Temperature Storage No bias Tamb=150 C 0/ h Note Note Version 1.0 Page 9/13

46 RR000916CS TESTS DESCRIPTION & DETAILED RESULTS 5.1 Die oriented tests High Temperature Operating Life This test is performed like application conditions in order to check electromigration phenomena, gate oxide weakness and other design/manufacturing defects put in evidence by internal power dissipation. Initial Ta=-40 C/25 C/125 C Check at 168 and Ta=25 C Final Testing Ta=-40 C/25 C/125 C Early Life Failure Rate This test is to evaluate the defects inducing failure in early life. The device is stressed in biased conditions at the max junction temperature. Initial Ta=25 C/125 C Final Testing (24 Ta=25 C/125 C Version 1.0 Page 10/13

47 5.2 Package oriented tests RR000916CS Pre-Conditioning The device is submitted to a typical temperature profile used for surface mounting, after a controlled moisture absorption. The scope is to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. Initial Ta=25 C/125 C. Final Ta=25 C/125 C High Temperature Storage The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature. The scope is to investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Thermal Cycles The purpose of this test is to evaluate the thermo mechanical behavior under moderate thermal gradient stress. Initial Ta=125 C. Check at 500 Ta=25 C Final Testing (1000 Ta=125 C TEST CONDITIONS: Ta= -50 C to +150 C(air) Autoclave The purpose of this test is to point out critical water entry path with consequent corrosion phenomena related to chemical contamination and package hermeticity. Initial Ta=25 C. Final Testing Ta=25 C. TEST CONDITIONS: P=2.08 atm Ta=121 C test time= 96 hrs Version 1.0 Page 11/13

48 5.2.5 Temperature Humidity Bias RR000916CS6080 The test is addressed to put in evidence problems of the die-package compatibility related to phenomena activated in wet conditions such as electro-chemical corrosion. The device is stressed in static configuration approaching some field status like power down. Temperature, Humidity and Bias are applied to the device in the following environmental conditions => Ta=85 C / RH=85%. Input pins to Low / High Voltage (alternate) to maximize voltage contrast. Test Duration 2000 h. Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Power Temperature Cycling This test simulates typical power automotive application. The test is addressed mainly to focus die-attach and wire bonding problems in all the temperature stress changes. Combined stress performing an HTOL stress while the ambient temperature is cycling between 40 to +110 C (Tj=150 C) with the DUT switched alternatively ON/OFF (5min. each) in asynchronous mode with respect the ambient temperature change, (1 cycle: stress Temp. / 20 to change Temperature). Initial Ta=25 C/125 C Check at 168, Ta=25 C Final Testing (1000 Ta=25 C/125 C Version 1.0 Page 12/13

49 RR000916CS Electrical Characterization Tests Latch-up This test is intended to verify the presence of bulk parasitic effects inducing latch-up. The device is submitted to a direct current forced/sinked into the input/output pins. Removing the direct current no change in the supply current must be observed. Initial Ta=25 C/125 C Latch-UP Ta=125 C Final Ta=25 C/125 C Stress applied: condition NEG. INJECTION POS. INJECTION OVERVOLTAGE IN low -100mA Inom+100mA 1.5 x VDD or MSV or AMR, whichever is less IN high -100mA Inom+100mA 1.5 x VDD or MSV or AMR, whichever is less E.S.D. This test is performed to verify adequate pin protection to electrostatic discharges. Initial Ta=25 C/125 C ESD Ta=25 C Final Ta=25 C/125 C TEST CONDITIONS: o Human Body Model ANSI/ESDA/JEDEC STANDARD JES001 CDF-AEC-Q o Charge Device Model ANSI/ESD STM ESDA JEDEC JESD22-C101 CDF-AEC-Q Version 1.0 Page 13/13

50 RR001016CS6080 General Information Locations Product Line Product Description Product division UD73 Step Down Switching Regulator I&PC Wafer fab location Assembly plant location Package HSOP 8L Silicon process technology BCD5-40NP Reliability assessment Pass ANG MO KIO AMKOR ATP1 PHILIPPINES DOCUMENT HISTORY Version Date Pages Author Comment Jan S.O.Cannizzaro Original document May A. Spiezia Typo corrections Approved by Giuseppe Capodici Version 1.0 Page 1/13

51 Table of Contents RR001016CS APPLICABLE AND REFERENCE DOCUMENTS RELIABILITY EVALUATION overview Objectives Conclusion Device Characteristics Device description Pin connection Bonding diagram Package outline/mechanical data Traceability Tests results summary Test plan and results summary of UD73 with XD lead frame strip Generic data from UK Tests Description & detailed results Die oriented tests High Temperature Operating Life Early Life Failure Rate Package oriented tests Pre-Conditioning High Temperature Storage Thermal Cycles Autoclave Temperature Humidity Bias Power Temperature Cycling Electrical Characterization Tests Latch-up E.S.D Version 1.0 Page 2/13

52 RR001016CS APPLICABLE AND REFERENCE DOCUMENTS Document reference Short description AEC-Q100 : Stress test qualification for integrated circuits : Reliability tests and criteria for qualifications Version 1.0 Page 3/13

53 RR001016CS RELIABILITY EVALUATION OVERVIEW 2.1 Objectives This report contains the reliability evaluation of UD73 device diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification. According to Reliability Qualification Plan, considering UD73 as circuit rerouting of UK17, below is the list of the trials performed: Package Oriented Tests Preconditioning Temperature Cycling Power Temperature Cycling Electrical Characterization ESD resistance test LATCH-UP resistance test 2.2 Conclusion Taking in account the results of the trials performed the UD73 diffused in ANG MO KIO and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES can be qualified from reliability viewpoint. Version 1.0 Page 4/13

54 RR001016CS DEVICE CHARACTERISTICS 3.1 Device description Pin connection Bonding diagram Version 1.0 Page 5/13

55 3.1.3 Package outline/mechanical data RR001016CS6080 Version 1.0 Page 6/13

56 RR001016CS Traceability Wafer fab information Wafer fab manufacturing location ANG MO KIO Wafer diameter 6 inches Wafer thickness 375 µm Silicon process technology BCD5-40NP Die finishing back side Cr/Ni Die size 2770x1980 µm Bond pad metallization layers AlSiCu Passivation PSG+SiON+Polyimide Metal levels 3 Assembly Information Assembly plant location AMKOR ATP1 PHILIPPINES Package description HSOP 8L Die pad size 2.413x3.099 mm Molding compound Ablebond 8290 Wires bonding materials/diameters Au/1.3 mils Die attach material Sumitomo G600 Lead solder material Sn Version 1.0 Page 7/13

57 4 TESTS RESULTS SUMMARY RR001016CS Test plan and results summary of UD73 with XD lead frame strip Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/ PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C 0/ h Vcc=36V, Iout=0.7A TC Temperature Cycling PC before Temp. range: -50/+150 C 0/ cy Note Electrical Characterization Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 ESD Electro Static Discharge Human Body Model +/- 2kV 0/3 - - Charge Device - - +/- 1kV 0/3 Model LU Latch-Up Over-voltage and Tamb=125 C 0/6 - - Current Injection Jedec78 All above trials performed on EEA rev. Duration Note Version 1.0 Page 8/13

58 4.2 Generic data from UK17 RR001016CS6080 Die Oriented Tests Test Method Conditions Failure/SS HTOL ELFR High Temperature Operating Life PC before Tj=150 C Vcc=36V Early Life Failure Rate Tj=150 C Vcc=32V Lot 1 Lot 2 Lot 3 Duration 0/77 0/77 0/ h h Note Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/308 0/308 0/308 THB Temperature Humidity Bias PC before Ta=85 C/85%RH 0/77 0/77 0/ h Pdut~0W, Vcc=20V PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C 0/ h Vcc=36V, Iout=0.7A AC Autoclave PC before 121 C 2atm 0/77 0/77 0/77 96h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/77 0/77 0/ cy HTSL High Temperature Storage No bias Tamb=150 C 0/ h Note Version 1.0 Page 9/13

59 RR001016CS TESTS DESCRIPTION & DETAILED RESULTS 5.1 Die oriented tests High Temperature Operating Life This test is performed like application conditions in order to check electromigration phenomena, gate oxide weakness and other design/manufacturing defects put in evidence by internal power dissipation. Initial Ta=-40 C/25 C/125 C Check at 168 and Ta=25 C Final Testing Ta=-40 C/25 C/125 C Early Life Failure Rate This test is to evaluate the defects inducing failure in early life. The device is stressed in biased conditions at the max junction temperature. Initial Ta=25 C/125 C Final Testing (24 Ta=25 C/125 C Version 1.0 Page 10/13

60 5.2 Package oriented tests RR001016CS Pre-Conditioning The device is submitted to a typical temperature profile used for surface mounting, after a controlled moisture absorption. The scope is to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. Initial Ta=25 C/125 C. Final Ta=25 C/125 C High Temperature Storage The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature. The scope is to investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Thermal Cycles The purpose of this test is to evaluate the thermo mechanical behavior under moderate thermal gradient stress. Initial Ta=125 C. Check at 500 Ta=25 C Final Testing (1000 Ta=125 C TEST CONDITIONS: Ta= -50 C to +150 C(air) Autoclave The purpose of this test is to point out critical water entry path with consequent corrosion phenomena related to chemical contamination and package hermeticity. Initial Ta=25 C. Final Testing Ta=25 C. TEST CONDITIONS: P=2.08 atm Ta=121 C test time= 96 hrs Version 1.0 Page 11/13

61 5.2.5 Temperature Humidity Bias RR001016CS6080 The test is addressed to put in evidence problems of the die-package compatibility related to phenomena activated in wet conditions such as electro-chemical corrosion. The device is stressed in static configuration approaching some field status like power down. Temperature, Humidity and Bias are applied to the device in the following environmental conditions => Ta=85 C / RH=85%. Input pins to Low / High Voltage (alternate) to maximize voltage contrast. Test Duration 2000 h. Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Power Temperature Cycling This test simulates typical power automotive application. The test is addressed mainly to focus die-attach and wire bonding problems in all the temperature stress changes. Combined stress performing an HTOL stress while the ambient temperature is cycling between 40 to +110 C (Tj=150 C) with the DUT switched alternatively ON/OFF (5min. each) in asynchronous mode with respect the ambient temperature change, (1 cycle: stress Temp. / 20 to change Temperature). Initial Ta=25 C/125 C Check at 168, Ta=25 C Final Testing (1000 Ta=25 C/125 C Version 1.0 Page 12/13

62 RR001016CS Electrical Characterization Tests Latch-up This test is intended to verify the presence of bulk parasitic effects inducing latch-up. The device is submitted to a direct current forced/sinked into the input/output pins. Removing the direct current no change in the supply current must be observed. Initial Ta=25 C/125 C Latch-UP Ta=125 C Final Ta=25 C/125 C Stress applied: condition NEG. INJECTION POS. INJECTION OVERVOLTAGE IN low -100mA 100mA 1.5 x VDD or MSV or AMR, whichever is less IN high -70mA 100mA 1.5 x VDD or MSV or AMR, whichever is less E.S.D. This test is performed to verify adequate pin protection to electrostatic discharges. Initial Ta=25 C/125 C ESD Ta=25 C Final Ta=25 C/125 C TEST CONDITIONS: o Human Body Model ANSI/ESDA/JEDEC STANDARD JES001 CDF-AEC-Q o Charge Device Model ANSI/ESD STM ESDA JEDEC JESD22-C101 CDF-AEC-Q Version 1.0 Page 13/13

63 RR001116CS6080 General Information Locations Product Line Product Description Product division UA50 Step Down Switching Regulator IPC Wafer fab location Assembly plant location Package HSOP 8L Silicon process technology BCD6S Reliability assessment Pass CATANIA M5 AMKOR ATP1 PHILIPPINES DOCUMENT HISTORY Version Date Pages Author Comment Feb S.O.Cannizzaro Original document May A. Spiezia Typo corrections Approved by Giuseppe Capodici Version 1.0 Page 1/13

64 Table of Contents RR001116CS APPLICABLE AND REFERENCE DOCUMENTS RELIABILITY EVALUATION overview Objectives Conclusion Device Characteristics Device description Pin connection Bonding diagram Package outline/mechanical data Traceability Tests results summary Test plan and results summary of UA50 with XD lead frame strip Test plan and results summary of UA50 with HD lead frame strip Tests Description & detailed results Die oriented tests High Temperature Operating Life Early Life Failure Rate Package oriented tests Pre-Conditioning High Temperature Storage Thermal Cycles Autoclave Temperature Humidity Bias Power Temperature Cycling Electrical Characterization Tests Latch-up E.S.D Version 1.0 Page 2/13

65 RR001116CS APPLICABLE AND REFERENCE DOCUMENTS Document reference Short description AEC-Q100 : Stress test qualification for integrated circuits : Reliability tests and criteria for qualifications Version 1.0 Page 3/13

66 RR001116CS RELIABILITY EVALUATION OVERVIEW 2.1 Objectives This report contains the reliability evaluation of UA50 device diffused in CATANIA M5 and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES, according to the AEC-Q100 (Grade1) specifications, in the overall plan of the S08ExpPad with XD lead frame strip qualification. According to Reliability Qualification Plan, below is the list of the trials performed: Package Oriented Tests Preconditioning Temperature Cycling Power Temperature Cycling Autoclave 2.2 Conclusion Taking in account the results of the trials performed the UA50 diffused in CATANIA M5 and assembled in HSOP 8L in AMKOR ATP1 PHILIPPINES can be qualified from a reliability viewpoint. Version 1.0 Page 4/13

67 RR001116CS DEVICE CHARACTERISTICS 3.1 Device description Pin connection Bonding diagram Version 1.0 Page 5/13

68 3.1.3 Package outline/mechanical data RR001116CS6080 Version 1.0 Page 6/13

69 RR001116CS Traceability Wafer fab information Wafer fab manufacturing location CATANIA M5 Wafer diameter 8 inches Wafer thickness 280 µm Silicon process technology BCD6S Die finishing back side Cr/Ni/Au Die size 1909x1587 µm Bond pad metallization layers AlCu Passivation TEOS+SiON+Polyimide Metal levels 4 Assembly Information Assembly plant location AMKOR ATP1 PHILIPPINES Package description HSOP 8L Die pad size 2.413x3.099 mm Molding compound Sumitomo G600 Wires bonding materials/diameters Au/1.2 mils Die attach material Ablebond 8290 Lead solder material Sn Version 1.0 Page 7/13

70 4 TESTS RESULTS SUMMARY RR001116CS Test plan and results summary of UA50 with XD lead frame strip Package Oriented Tests Test Method Conditions Failure/SS Lot 1 Lot 2 Lot 3 Duration PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C 0/154 0/154 0/154 PTC Power Temperature Cycling On Chip Boards Tj=-40 C 150 C, Vcc=25V, Iout=0.7A 0/ h AC Autoclave PC before 121 C 2atm 0/77 0/77 0/77 96h TC Temperature Cycling PC before Temp. range: -50/+150 C 0/77 0/77 0/ cy Note Version 1.0 Page 8/13

71 4.2 Test plan and results summary of UA50 with HD lead frame strip Die Oriented Tests Test Method Conditions Sample/ HTOL THB PTC ELFR RR001116CS6080 Number Duration Results Lots of lots High Temperature Operating Life On Chip Boards Tj=150 C, Vcc=20V, Iout=3,5A (Max) h PASSED Temperature Humidity Bias On Chip Boards Ta=85 C 85% RH, Vcc=38V h PASSED Power Temperature Cycling On Chip Boards Tj=-40 C 150 C, Vcc=25V, Iout=0.7A h PASSED Early Life Failure Rate Tj=150 C h PASSED Vcc=25V, Iout=0,35A Package Oriented Tests Test Method Conditions Sample/ Number Duration Results Lots of lots PC Pre-Conditioning: Moisture sensitivity level 3 192h 30 C/60% - 3 reflow PBT 260 C PASSED AC Autoclave PC before 121 C 2atm h PASSED TC Temperature Cycling PC before Temp. range: -50/+150 C cy PASSED HTSL High Temperature Storage Life No bias Tamb=150 C h PASSED Electrical Characterization Tests Test Method Conditions Sample/ ESD LU Number of lots Duration Results Lots Electro Static Discharge Human Body Model +/- 2kV 3 1 PASSED Charge Device Model Latch-Up Over-voltage and Current Injection +/- 500V +/- 750V on corner pins Tamb=125 C Jedec78 Level B 3 1 PASSED 6 1 PASSED Version 1.0 Page 9/13

72 RR001116CS TESTS DESCRIPTION & DETAILED RESULTS 5.1 Die oriented tests High Temperature Operating Life This test is performed like application conditions in order to check electromigration phenomena, gate oxide weakness and other design/manufacturing defects put in evidence by internal power dissipation. Initial Ta=-40 C/25 C/125 C Check at 168 and Ta=25 C Final Testing Ta=-40 C/25 C/125 C Early Life Failure Rate This test is to evaluate the defects inducing failure in early life. The device is stressed in biased conditions at the max junction temperature. Initial Ta=25 C/125 C Final Testing (24 Ta=25 C/125 C Version 1.0 Page 10/13

73 5.2 Package oriented tests RR001116CS Pre-Conditioning The device is submitted to a typical temperature profile used for surface mounting, after a controlled moisture absorption. The scope is to verify that the surface mounting stress does not impact on the subsequent reliability performance. The typical failure modes are "pop corn" effect and delamination. Initial Ta=25 C/125 C. Final Ta=25 C/125 C High Temperature Storage The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature. The scope is to investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding Initial Ta=25 C/125 C Check at 168 and Ta=25 C Final Testing (1000 Ta=25 C/125 C Thermal Cycles The purpose of this test is to evaluate the thermo mechanical behavior under moderate thermal gradient stress. Initial Ta=125 C. Check at 500 Ta=25 C Final Testing (1000 Ta=125 C TEST CONDITIONS: Ta= -50 C to +150 C(air) Autoclave The purpose of this test is to point out critical water entry path with consequent corrosion phenomena related to chemical contamination and package hermeticity. Initial Ta=25 C. Final Testing Ta=25 C. TEST CONDITIONS: P=2.08 atm Ta=121 C test time= 96 hrs Version 1.0 Page 11/13