FINAL PRODUCT/PROCESS CHANGE NOTIFICATION #16230A Generic Copy

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1 Generic Copy Issue Date: 11-Feb-2011 TITLE: Dual Sourcing at Gresham; General Sales Devices PROPOSED FIRST SHIP DATE: 11-May-2011 or earlier at customer request AFFECTED CHANGE CATEGORY(S): Wafer Fab Process FOR ANY QUESTIONS CONCERNING THIS NOTIFICATION: Contact your local ON Semiconductor Sales Office or SAMPLES: Contact your local ON Semiconductor Sales Office ADDITIONAL RELIABILITY DATA: Available Contact your local ON Semiconductor Sales Office NOTIFICATION TYPE: Final Product/Process Change Notification (FPCN) Final change notification sent to customers. FPCNs are issued at least 90 days prior to implementation of the change. ON Semiconductor will consider this change approved unless specific conditions of acceptance are provided in writing within 30 days of receipt of this notice. To do so, contact DESCRIPTION AND PURPOSE: Qualification of ON Semiconductor wafer fab (USGR1) at Gresham, Oregon to source C5 devices. Issue Date: 11-Feb-2011 Rev. 06-Jan-2010 Page 1 of 5

2 RELIABILITY DATA SUMMARY: Intrinsic : Intrinsic Reliability Qualification Plan (Qualification per 12MON20866, , JEDEC JP ) Process & Waferfab : C5, USGR1 Date : 10, Feb, 2010 Prepared by : Eddie Glines Process Status, notes: Transfer from Fab 10 Approved by : Bruce Greenwood ACCELERATED COMPONENT STRESS TESTS Reference Conditions Applicable Device or structure Electromigration or ISEM JESD61, JESD87, Isothermal EM test JESD33A, to calculate Ea. Assume N=2.0. JESD37, JESD63, ASTM: F , EIAJ-986 All unique structures among: Contacts, Metals, Vias, Stacked Vias. min 12 samples per test <0.01% fails in 10 years at use conditions 3 Stress Migration JEP139, JESD87 High temperature storage: 150C, 175C, 200C, 225C, 250C; 1000hrs SM structures At least 40 samples per wafer, 1 wf per condition dr/r<20%, <0.1% defective 3 DC Hot Carrier Injection Voltage Ramp Dielectric Breakdown (VRDB / charge to Breakdown (QBD)) Time-Dependent Dielectric Breakdown Negative Bias Temperature Instability (NBTI) JESD28, JESD60, 1.1*Vd accelerated stress test at EIAJ-987 Isubmax or Vgmax JESD35 EIAJ-988 Vramp to at least 8MV/cm, or calculate VBD from breakdown distribution Vg accelerated stress test; multiple Temps and Voltages. Calculate Ea. 1.1*Vduse 168hrs, 3 Temps, 3 Voltages, DC & multiple frequencies nom gate N & P, long gate N; thin & thick N & P, thin & thick. Gate caps on Nwell, Pwell, and Bulk. PIP, MIM N & P, thin & thick. Gate caps on Nwell, Pwell, and Bulk, PIP, MIM P, thin and thick (N, thin and thick for PBTI) 3 samples per condition, min 4 xtors per voltage size sufficient to resolve D0 criteria Min 20 caps per stress condition nom gate: <10% shift >0.2yr DC, 7yr AC 100ppm lifetime Beta D0 <10 Defect/cm2, P1 D0 < 2 Defect/cm2, P2 D0 < 1 Defect/cm2 0.01% cum fails for 10yrs at 125C min 8 per xtor type Vth<10% shift 3 Issue Date: 11-Feb-2011 Rev. 06-Jan-2010 Page 2 of 5

3 Extrinsic Level : Product Reliability Qualification Plan (Tier 4 Qualification per ) AMIS Product Name : Qual Plan Revision : 1.0 Customer Product Name : ASIC 1A Date : 11/10/2009 Maskset : N/A Prepared by : Richard Tan Die : 2550um x 2530um Approved by : Eddie Glines Process & Waferfab : C5 USGR1 Qual Start Date Forecast : NA Package & Assembly House : 32 TQFP parts required : 3445 A1 Reference Conditions Moisture Preconditioning (PC) J-STD-020 Moisture Soak (MSL = 3) JESD22-A113 Solder Reflow 260 C) ACCELERATED ENVIRONMENT STRESS TESTS per room /735 A2 HAST Biased (HAST) JESD22-A C / 85%RH for 96 hot /237 s preconditioned per test A1 (PC) Encountered HAST boards problem. Use device A3 HAST Unbiased (alt) (UHST) A4 A6 B1 B2 C1 Temperature Cycling (TC) High Temperature Storage (HTS) JESD22-A C/ 85%RH for 96 room JESD22-A C to 150 C for 500 hot JESD22-A C for 1000 hrs Reference Conditions High Temperature Operating Lifetest (HTOL) Early Life Failure Rate ; Burn-in (ELFR) JESD22-A108 Ta = 125 C for 1000 hrs JESD22-A108 Ta = 125 C for 63 hrs AEC Q Reference Conditions Wire Bond Shear (WBS) hot ACCELERATED LIFETIME SIMULATION hot PACKAGE ASSEMBLY INTEGRITY TESTS 30 bonds from 5 parts min; no ball lifting (CPK>1.33) N.A. 30 bonds from 5 parts Cpk > 1.33 Ppk > /239 0/240 0/48 0/236 0/ s preconditioned per test A1 (PC) s preconditioned per test A1 (PC). C2 Wire Bond Pull Strength (WBP) MIL- STD883 Method 2011 Cond. C or D. Minimum pull strength after temperature cycle = 3 grams N.A. 30 bonds from 5 parts Cpk > 1.33 Ppk > Fails after test A4 (TC) 1 5 C3 Solderability (SD) JESD22-B102 N.A. 15 parts > 95% lead coverage 1 15 ESD - Human E2a Body Model (HBM) ESD - Machine E2b Model (MM) ESD - Charged E3 Device Model (CDM) E4 Latch-up (LU) Reference Conditions AEC Q kv AEC Q V AEC Q V corner pins; 500V all other pins AEC Q C ELECTRICAL VERIFICATION hot voltage voltage voltage Issue Date: 11-Feb-2011 Rev. 06-Jan-2010 Page 3 of 5

4 ELECTRICAL CHARACTERISTIC SUMMARY: Wafer Sort: The lot is comparable to the average wafer sort yield. Bin distribution is comparable for both Gresham and Fab10. Wafer Sort Yield No Issue Gresham device yield is comparable to the Fab10 device average yield Bin Distribution No Issue Gresham bins are comparable with the Fab10 device. Final : The FT yield of Gresham lot is comparable with the average FT yield of the Fab10 device. All other parametric tests have cpk above 1.67 at all insertions. FT Yield No issue Gresham lot yield is comparable with Fab10 average FT yield Bin Distribution No issue Top failure mode is comparable to Fab10. CPKs No issue All parametric tests have acceptable cpk at all insertions CHANGED PART IDENTIFICATION: New part number from Gresham Fab is x. Issue Date: 11-Feb-2011 Rev. 06-Jan-2010 Page 4 of 5

5 List of affected General : MPN impact list (Std. Prod.) XTD XTP XTD XTP A5191HRTLG-XTD A5191HRTLG-XTP A5191HRTPG-XTD A5191HRTPG-XTP Issue Date: 11-Feb-2011 Rev. 06-Jan-2010 Page 5 of 5