Transfer Molding Encapsulation of Flip Chip Array Packages

Size: px
Start display at page:

Download "Transfer Molding Encapsulation of Flip Chip Array Packages"

Transcription

1 Intl. Journal of Microcircuits and Electronic Packaging Transfer Molding Encapsulation of Flip Chip Array Packages Louis P. Rector*, Shaoqin Gong, and Tara R. Miles Dexter Corporation 11 Franklin Street Olean, New York Phone: Fax: s: Kevin Gaffney Amkor Technology 1900 South Price Road Chandler, Arizona 8548 Phone: Fax: *Author to whom correspondence should be addressed Abstract Epoxy molding compounds have been developed which can simultaneously underfill and overmold the Flip Chip die in a single transfer molding process. Transfer molding is a well-defined industry process; with suitable mold design, these materials can utilize the currently installed capital base. The ability to apply pressure during the molding process can reduce the void rate under the die as well as achieving production efficiencies which are typical of transfer molding processes. Transfer molding compounds offer enhancements in thermal expansion coefficients and moisture absorption levels relative to traditional liquid underfills as well as low levels of package deformation due to cure shrinkage and thermal mismatch effects. These improvements are achieved through the use of unique resin chemistries and filler package compositions. This paper will provide an overview of molding compounds which are useful as transfer molding underfill/ encapsulant materials. Key words: 1. Introduction and Background Flip Chip, Transfer Molding, Encapsulation, Underfill, and Epoxy Molding Compound. 400 Increases in I/O densities and processing speeds continue to drive the evolution and applicability of Flip Chip packaging for small, lightweight components. 1 To improve solder joint and device reliability, Flip Chip packages are conventionally underfilled with a liquid material capable of filling the small (5-75micron) gap between the chip and the substrate. In the majority of cases, the chip is subsequently protected with either a liquid encapsulant or a transfer molding compound. The liquid underfill process (dispense, flow, and cure) is typically slow and prone to defect formation, such as voids and filler streaking or settling, if the process is not

2 Transfer Molding Encapsulation of Flip Chip Array Packages carefully designed and controlled. Advanced liquid underfill compositions have been developed which mitigate some of these concerns. Alternative underfill technologies continue to be explored and have utility depending on the application. For example, no-flow underfill materials have been investigated extensively. In this case, the undefill layer is deposited before the solder interconnect step. However, reliable interconnect formation during solder reflow and the development of materials with suitably high filler levels may be a technical challenge with the no-flow approach. 3 Employing a single-step transfer molding process to underfill and overmold a Flip Chip device offers a number of technical and process advantages. The initial development of this process has been previously reported, as well as the potential for four fold improvement in rates of production versus a conventional underfill process. 4 Other workers have also reported initial investigations of the molded underfill process 5-6. The application of external pressure to drive the underfill process allows the use of higher filler content materials compared to conventional liquid materials. It is well known that increases in filler content lead to improvements in moisture absorption and thermal expansion coefficients of epoxy molding compounds. Increases in filler content also commonly translate to improved device performance in JEDEC and thermal cycling evaluations. In addition, high performance liquid underfill compounds are also typically expensive in terms of both material cost and floor life. The introduction of an underfilling transfer mold compound can substantially improve the economy of the encapsulation process in high volume applications. The development of a successful transfer molded underfill/ overmold encapsulation material and molding process present a number of technical challenges. The judicious design of the mold and choice of molding parameters are equally critical to the implementation of this technology. These materials have been designed to have the ability to flow significant distances in small channels (5-50µm). The long flash character of these materials and the potential need for vacuum assist present challenges for mold chase and vent design, which must be addressed by development with the mold manufacturer. The performance of the molding compound is also crucial. The filler particle shape, size, and size distribution must be optimized to provide good gap filling capabilities. The choice of the epoxy resin and phenolic hardener is partially governed by the need for low viscosity, which allows maximization of the filler content, while maintaining other properties, such as low warpage. As expected, there are interaction effects present between the various components in a molding compound which influence device reliability. It is the objective of this paper to present material developments of molded Flip Chip (MFC) compounds as well as device reliability results.. Experimental Work Several experimental designs were conducted as part of this development effort. The first such study was a simple lattice mixture design focusing on the performance of three epoxy resin types. In this study, the extremes in composition were prepared (100% of each epoxy), along with two axial blends of each pair (1/3:/3 and /3:1/3 ratios) and the overall midpoint composition (1/3 of each component). Spherical silica (100% sized below 15 µm) was used as the filler. A second study investigated the effect on epoxy molding compound (EMC) properties of the variations in filler composition. Other formulation ingredients (phenolic hardener, flame retardants, stress modifiers, coloring agent, release agents, coupling agents, and catalyst) were also present, the levels of which were held constant. The molding compounds were prepared by initially dry-blending the ingredients followed by melt-mixing. The material was extruded in sheet form, allowed to cool, and ground to a fine powder. Standard transfer molding techniques were used to fabricate various test specimens. In-mold cure times were s at 165 C followed by a four hour post-cure, also, at 165 C. Flexural properties were evaluated in a three-point bending mode on an Instron 406 unit. The flexural testing conformed to ASTM D790-96a. Flexural bar dimensions were 5.0 x 0.5 x 0.5; a cross-head speed of 0.10 in/min was used. To assess moisture uptake, molded disks.0 inches diameter by 0.15 inches in thickness were conditioned in an 85% RH/85ºC environment. The disks were periodically removed, weighed, and returned to the test environment. Shrinkage before and after post-cure was measured on 5.0 x 0.5 x 0.5 bars. The glass transition temperature and thermal expansion coefficients were measured on a Thermal Analysis TA 100/940 unit with a heating rate of 10C /min. Flash and channel flow were measured in industry standard molds. Data analysis was conducted using Design-Expert, a statistical analysis software package produced by Stat-Ease, Inc. 3. Results and Discussion The flow of the molding compound in narrow channels, which has been found to correlate with the ability of the material to underfill a die of corresponding offset from the board, was measured for channel heights of 5 µm, 50 µm, and 75µm. The dependence of 50µm channel flow length upon epoxy composition is shown in Figure 1. In this case, an empirical linear model fits the data quite well (R = ), 50µm channel flow (mm) = 7.65*A *B *C (1) where A, B, and C represent fractions of the three epoxies. The magnitudes of the coefficients trend with the values reported by the material suppliers for the epoxy melt viscosities. For the 5µm 401

3 Intl. Journal of Microcircuits and Electronic Packaging channel flow, interaction effects become significant (Figure ). As might be expected from such a multi-parameter model, the fit is quite good (R = 0.990), 5µm channel flow (mm) = 17.19*A *B * C *A*B *A*C *B*C () A Shrinkage of the molding compound upon post-cure was a second parameter to be optimized, since it can be related to the warpage of the encapsulated package (see, for example References 7,8.) As trends towards packages with larger, thinner die, and thinner, more flexible substrates become more prominent, the minimization of package warpage becomes increasingly important. This is especially critical in array format packaging, where in addition to the above trends, the overmold is becoming larger and thinner as well. The measured warpage is strongly package and cure schedule dependent, as well as being a function of the viscoelastic relaxation character of the encapsulant. As an example of the dependence of warpage on cure schedule, the deformation of a 35mm BGA package was measured as a function of in-mold cure time. The results are summarized in Table 1, where the warpage measured via Shadow Moire is strongly dependent upon in-mold cure time. This is related to the degree of cross-link density achieved prior to the removal of pressure on the system and to relaxation effects which occur at the molding temperature Table 1. Dependence of room temperature warpage (µm) upon in-mold cure time. The two EMCs were used to encapsulate a 35mm BGA Package. B C In-Mold Cure (s) (sec) EMC A EMC B Figure 1. Dependence of 50µm channel flow (in mm) at 165 C on epoxy composition. A The shrinkage measurement was chosen as an initial screening tool to separate the effects of molding compound performance (cure shrinkage and thermal contraction effects) from the effects of package structure. The best fit empirical relation between epoxy composition and shrinkage upon post-cure is given in equation (3), however, the goodness of fit is low (R = ), Shrinkage (%) = *A *B *C (3) 40 B Figure. Dependence of 5µm channel flow (in mm) at 165 C on epoxy composition. C Comparison of the dependencies of shrinkage (to be minimized) and channel flow lengths (to be maximized), a binary blend of resins A and C is preferred. The measurements of other molding compound physical properties not reported in this publication (such as, moisture absorption under conditions of 85%RH/ 85 C, high temperature modulus and strength), support this conclusion.

4 Transfer Molding Encapsulation of Flip Chip Array Packages The physical properties of one of the optimized compositions are summarized in Table. This material has a relatively high Tg and a low modulus. Compared with conventional liquid underfill materials, it also has decreased moisture absorption, due to its higher filler content. As discussed above, the material was formulated with a relatively long flash and good flow characteristics in order to promote uniform package encapsulation. Table. Properties of MFG material (-19A). It is well known that the filler loading level, particle size and distribution, and particle morphology have profound effects on EMC material properties such as viscosity, spiral flow, channel flash, coefficient of thermal expansion, mechanical properties, and moisture absorption. The effects of filler loading on the material properties of a MFC material were reported previously 4. To study the effects of particle size and distribution on MFC performance, three 1 spherical silica fillers A, B, and C with median particle sizes of µm, 0.9 µm, and 0.4 µm, respectively, were selected for the study. 76 Filler System 1 consists of mixtures of fillers A and B; Filler System consists of mixtures of fillers A and C. Both filler systems 7 74 examined ratios of the large filler (A) to the small filler (B or C) 70 ranging from 90:10 to 75:5. The base formulation used for this 68 study had a 61% by volume filler loading. Additional components present in the formulation are identical to the epoxy mixture study % Filler A discussed above. Figure 3 shows the Shimadzu viscosity versus the percentage of Filler A for both filler systems. The viscosity decreases with the Figure 4. Dependence of the maximum packing density for increase of Filler A for both filler systems. The viscosity of Filler the indicated filler systems on filler A level. System is observed to be higher than that of Filler System 1 below the level of 85% of Filler A. To describe the viscosity of a It has been demonstrated that Mooney equation holds for the highly filled dispersion, numerous approaches have been proposed suspension viscosity for a range of volume fractions near the close in the literature. These treatments are efforts to extend Einstein s packing density 1. Mooney s theory predicts that the viscosity of classical analysis of the viscosity of a dilute suspension of rigid the dispersion will decrease with increasing maximum packing spheres in a viscous liquid to suspensions of higher filler concen- density at a given filler loading. For both systems, the viscosity is tration 9. Among these approaches, the semi-empirical equation developed by Mooney has been widely used 10,! =! o exp[k e " f /(1-[" f /" max ]) (4) where! is viscosity of the suspension,! o is the viscosity of the binder, K e is the Einstein s coefficient, " f is the volume fraction of filler, and " max is the theoretical maximum packing density. Viscosity (poise) % Filler A 1 Figure 3. Minimum Shimadzu viscosity for filler systems 1 and at 165 C as a function of filler A (expressed as a percentage of total filler) level. The maximum packing density of the filler system is calculated via a computer algorithm developed by Lee based on the size distribution of the filler. 11 Figure 4 shows the calculated maximum packing density versus the percentage of filler A for both filler systems. In this case, it is seen that the maximum packing density decreases with the amount of filler A in both filler systems. The maximum packing density of Filler System 1 is consistently lower than that of Filler System. These results agree with previous observations of the effects of the volume and diameter ratios of the large to small particles on the maximum packing density. 11,1 Maximum Packing Percentage 403

5 observed to increase with increasing maximum packing density. This is due to the fact that the semi-empirical Mooney equation neglects the effects of particle-medium and particle-particle interactions on the suspension viscosity. For a system with strong interactions, viscosity will increase with increasing surface area or decreasing particle size.10,1 The silica fillers used in the molding compound were treated with epoxy-functional silane which is reactive with the binder system, increasing the particle-medium interactions. Therefore, viscosity is determined by both the maximum packing density factor and the particle surface area/size factor. At a constant filler loading, the larger the maximum packing density or the larger the particle surface area, the lower the viscosity. The BET surface areas of fillers B, and C are 6, and 13 m/g, respectively. The differences in BET surface areas may account for the variation of the viscosity with the amount of the large filler for both filler packages and the difference (below 85% of Filler A) between the two filler systems. These two factors (maximum packing density and BET surface area) compete with each other within the range of this study; the surface area factor appears to be dominant. Figure 5 shows the relationship between spiral flow and the percentage of filler A for both filler systems. For both filler systems, the spiral flow roughly increases with the percentage of filler A, and, therefore, decreases with viscosity. However, spiral flow is a complex rheo-kinetic event, as has been previously reported13, and filler loading effects can be masked by curing effects. Figure 6 shows the dependence of channel flow on the percentage of Filler A for both filler systems. The channel flows of Filler System 1 are consistently higher than that of Filler System, except at 90:10 filler ratio. Other material properties such as the glass transition temperature, thermal expansion coefficient, and flex strength, and modulus (both room temperature and 15 C) have also been measured. No substantial difference has been observed among these samples. The moisture absorption of Filler System 1 after 1 week 85 C/85%RH conditioning is slightly lower than that of Filler System. This effect may be related to the fact that the saturated level of moisture absorption increases with filler specific surface area. Channel Flow (mm) Intl. Journal of Microcircuits and Electronic Packaging µm (1 ) 7 5 µm ( ) 5 0 µm (1 ) 5 0 µm ( ) 5 µm (1 ) µm ( ) 90 % of Filler A Figure 6. Dependence of channel flow length at 165 C filler A level. Filler system is indicated in parentheses. In the epoxy mixture study outlined above, two promising candidates were identified which provided the best balance of properties (such as shrinkage, moisture absorption, channel flow). These candidates (-13A and 19A) were evaluated in two Amkor Technology prototype array format packages. The underfill characteristics of a material similar in composition to that of -13A was evaluated in a previous study using a test die and molding facilities provided by Fico.4 In that study, the capability of this class of compounds to effectively transfer underfill/overmold devices with small gap thicknesses (5-50µm) was demonstrated. The Amkor package characteristics are given in Table 3. In both packages, the die thickness is 0.30mm, the gap height is 40µm, the bump diameter is µm, the soldermask thickness is 0µm, the substrate thickness is 0.mm, and the total mold cap height is 0.6mm. A typical device cross-section is shown in Figure 7 for material 19A. Table 3. Amkor test device characteristics. Package Package Die Dimensions* Dimensions (mm) (mm) I 8 x 8 x x.6 II 17 x 17 x x 10.5 # of Solder Peripheral Bumps 64 (single row) 56 (three rows) # of Die per strip Spiral Flow (cm) *Package dimensions are given without BGA balls attached. 100 silicon µm % Filler A 90 Figure 5. Dependence of spiral flow length at 165 C for the indicated filler systems on filler A level. solder joint soldermask Figure 7. Cross-section of Amkor Package I using material -19A showing complete filling of the Flip Chip gap. 404

6 Transfer Molding Encapsulation of Flip Chip Array Packages There were some voids noted in the package in the moldcap area; the elimination of these voids is a subject of future mold process and materials development. However, both materials are noted to have uniformly underfilled the area beneath the die, demonstrating the feasibility of this concept, although the substrates were mechanically vented. Collaboration with mold chase manufacturers is currently in progress to develop a molding process that would not require a mechanical vent in the substrate. The molded parts were post-cured four hours at 175 C in a stacked configuration with load of approximately Kg on the stack. After substrate singulation, the parts were evaluated by CSAM, then subjected to JEDEC Level 3 preconditioning (30 C, 60%RH, 168 hrs) followed by either a 0 C or 40 C reflow. After preconditioning, the parts were inspected by CSAM. Popcorn failures, which indicate macroscopic delamination, can be identified by black circles on the CSAM images, as in Figure 8. Failure rates for all four package populations are summarized in Table 4. The performance of the -13A material in Package I at both temperatures and in Package II at the 0 C reflow are statistically equivalent. In Package II at 40 C reflow, the failure rate of 13A becomes substantial. The 19A material exhibits no failures in either package type at either reflow temperature. The flatness (warpage) of each population was sampled after preconditioning. The deformation was measured optically by focusing on BGA pads at the corners and one in the center of the BGA matrix. A regression plane was fit to the five data points and the maximum deviation above and below the best fit plane was summed to get the flatness value. The statistical variation among the populations is shown graphically in Figure 9. This warpage data show no difference between the materials for the type I pack- age. However, for the larger package, the coplanarity decreases with respect to the smaller package. The large package with material -13A shows the maximum warpage. Figure 9. Comparison of the flatness measurements for the four material/package combinations. The Tukey-Kramer circles indicate that populations II/13A and II/19A are significantly different from every other population, including each other. However, the Package I populations have the same flatness. 4. Concluding Remarks Figure 8. CSAM images of Package II after JEDEC Level 3 exposure plus 40 C reflow for the A(-13A and B) -19A materials. Note the popcorn failure (large black circle) in image (A). Table 4. Failure levels of Amkor test devices after MRTL3. The technical feasibility of the use of a solid epoxy molding compound to fully encapsulate a Flip Chip device has been demonstrated. Uniform underfill was achieved with accompanying good JEDEC performance. The optimum resin and filler particle compositions have been identified which provide the excellent performance of these molding compounds. Technical challenges remain in the area of suitable mold design which will require the close interaction between mold compound supplier, mold designer, and the component manufacturer. Dexter Package Reflow Popcorn Material Temperature Failures ( C) -13A I 0 0/6-13A I 40 1/8-13A II 0 1/4-13A II 40 5/ -19A I 0 0/8-19A I 40 0/8-19A II 0 0/19-19A II 40 0/18 Acknowledgments The authors would like to acknowledge the assistance of Henk Peters, Walter de Munnik, and Wilfred Gal at FICO in molding and mold design. The authors would also like to acknowledge the efforts of technicians at Dexter Electronic Materials who made this work possible; John Barrett, Pete Parker, and Bill Cochran. Useful discussions with Dr. Do Ik Lee of Dow Chemical are gratefully acknowledged. Finally, the authors appreciate the support of the management teams at Dexter Electronic Materials and Amkor Technology in these studies. 405

7 Intl. Journal of Microcircuits and Electronic Packaging References About the authors 1. R. R. Tummala, E. J. Rymaszewski, and A. Klofenstein, Microelectronics Packaging Handbook, Chapman & Hall, M. Todd, K. Desai, and L. Hoang, Evaluation of Key Underfill Formulation Parameters on the Performance of Flip-Chip Devices, Proceedings of the Pan Pacific Microelectronic Conference, Kaanapali, Hawaii, pp. -6, S. H. Shi and C. P Wong, Recent Advances in the Devlopment of No-Flow Underfill Encapsulants A Practical Approach towards the Actual Manufacturing Application, Proceedings of the 49th IEEE Electronic Components and Technology Conference, ECTC 99, San Diego, California, pp , T. R. Miles, L. P. Rector, S. Gong, and T. LoBianco, Transfer Molding Encapsulation of Flip Chip Array Packages : Technical Developments in Material Design, Semicon West 000, San Jose, California, pp. E1-E6, K. Gilleo, B. Cotterman, and I. A. Chen, Molded Underfill for Flip Chip in Package, HDI, pp. 8-31, June Y. Lin, K. Chai, T. D. Her, and R. Lo, Transfer Molded Underfill for FC-BGA, Proceedings of Semicon Taiwan, pp , September, K. Kuwata, K. Iko, and H. Tabata, Low-Stress Resin Encapsulants for Semiconductor Devices, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 8, No. 4, pp , L. Rector, S. Gong, T. Miles, and J. Zhang, Themoset Encapsulant Performance Requirements for BGA 1C Applications, Proceedings of the 1999 Workshop on Polymeric Materials for Microelectronics and Photonics Applications, Paris, France, EEP, Vol. 7, pp , American Society of Mechanical Engineers Press, D.H.Everett, Basic Principles of Colloid Science, pg. 115, Royal Society of Chemistry, M. Mooney, The Viscosity of a Concentrated Suspension of Spherical Particles, J. Colloid Science, Vol. 6, pp , D. I. Lee, Packing of Spheres and its Effect on the Viscosity of Suspensions, Journal of Paint Technology, Vol. 4, pp , R. K. McGeary, Mechanical Packing of Spherical Particles, Journal of American Ceramic Society, Vol. 44, No. 10, pp , A. Hale, M. Garcia, and C. W. Macosko, Computer Simulation of the Spiral Flow of a Commercial Epoxy Molding Compound, SPE RETEC, pp , Louis Rector is a Research Associate in the Microelectronic Molding Powders Department at Dexter Electronic Materials. He is team leader for molded Flip Chip program and also assesses new materials technologies for Dexter s advanced packaging efforts. He received B.S. Degrees in Chemistry and Chemical Engineering from the University of Illinois at Champaign-Urbana, and he has a M.S. Degree in Manufacturing Engineering, and a Ph.D. Degree in Materials Science, both from Northwestern University. Shaoqin Gong is a Senior Materials Technologist in the Microelectronic Molding Powders Department at Dexter Electronic Materials Division. She received a B. S. Degree in Materials Science and Engineering, a B.S. Degree in Economics and Management, and a Master s Degree in Materials Science and Engineering all from Tsinghua University in China. She also received a Ph.D. Degree in Materials Science and Engineering from The University of Michigan at Ann Arbor. Since joining Dexter, she has been developing molding compounds for advanced BGA and molded Flip Chip applications. Tara Miles is the Product Manager for the electronic formulated liquid and optoelectronic product lines for Dexter Electronic Materials. Prior to assuming this role, she has worked for Dexter as a formulating chemist in the Research and Developement group for eleven years. She has published numerous papers in the electronics industry, focusing on adhesion science and the effects of delamination on device reliability. She received her Bachelor s Degree in Chemistry from Alfred University and a Masters in Business Administration from St. Bonaventure University. Kevin Gaffney is the Sr. Process Development Engineer for Flip Chip CSP products at Amkor Technology s Advanced Product Development Center in Chandler, Arizona. His focus is prototyping Flip Chip assembly processes for a variety of new products including stacked die and System in Package applications. He is also responsible for the introduction of new assembly processes, equipment, and materials for CSP assembly. He received his B.S. Degree in Ceramic Engineering from the University of Illinois at Urbana-Champaign, and his M.S. Degree in Material Science from the University of Illinois at Chicago. 406

PoP/CSP Warpage Evaluation and Viscoelastic Modeling

PoP/CSP Warpage Evaluation and Viscoelastic Modeling PoP/CSP Warpage Evaluation and Viscoelastic Modeling Wei Lin, Min Woo Lee Amkor Technology 19 S Price Rd, Chandler, AZ 85286 wlin@amkor.com Abstract The purpose of this paper was to evaluate the critical

More information

Selection and Application of Board Level Underfill Materials

Selection and Application of Board Level Underfill Materials Selection and Application of Board Level Underfill Materials Developed by the Underfill Materials Design, Selection and Process Task Group (5-24f) of the Assembly and Joining Committee (5-20) of IPC Supersedes:

More information

TRANSFER MOULDING & EPOXY MOULD COMPOUND TECHNOLOGY WORKSHOP

TRANSFER MOULDING & EPOXY MOULD COMPOUND TECHNOLOGY WORKSHOP TRANSFER MOULDING & EPOXY MOULD COMPOUND TECHNOLOGY WORKSHOP TRANSFER MOULDING & EPOXY MOULD COMPOUND TECHNOLOGY WORKSHOP INTRODUCTION This workshop will provide participants with knowledge and understanding

More information

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Henry M.W. Sze, Marc Papageorge ASAT Limited 14th Floor, QPL Industrial Building, 138 Texaco Road, Tseun Wan, Hong

More information

A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate

A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate A Cofired Bump Bonding Technique for Chip Scale Package Fabrication Using Zero X-Y Shrinkage Low Temperature Cofired Ceramic Substrate Minehiro Itagaki, Nobuhiro Hase, Satoru Yuhaku, Yoshihiro Bessho and

More information

Design for Plastic Ball Grid Array Solder Joint Reliability. S.-W. R. Lee, J. H. Lau*

Design for Plastic Ball Grid Array Solder Joint Reliability. S.-W. R. Lee, J. H. Lau* Page 1 of 9 Design for Plastic Ball Grid Array Solder Joint Reliability The Authors S.-W. R. Lee, J. H. Lau* S.-W. R. Lee, Department of Mechanical Engineering, The Hong Kong University of Science and

More information

The Development of a Novel Stacked Package: Package in Package

The Development of a Novel Stacked Package: Package in Package The Development of a Novel Stacked Package: Package in Package Abstract Stacked die Chip Scale Packages (CSPs) or Fine-pitch BGAs (FBGAs) have been readily adopted and integrated in many handheld products,

More information

Recent Advances in Die Attach Film

Recent Advances in Die Attach Film Recent Advances in Die Attach Film Frederick Lo, Maurice Leblon, Richard Amigh, and Kevin Chung. AI Technology, Inc. 70 Washington Road, Princeton Junction, NJ 08550 www.aitechnology.com Abstract: The

More information

Solder joint reliability of cavity-down plastic ball grid array assemblies

Solder joint reliability of cavity-down plastic ball grid array assemblies cavity-down plastic ball grid array S.-W. Ricky Lee Department of Mechanical Engineering, The Hong Kong University of Science and, Kowloon, Hong Kong John H. Lau Express Packaging Systems, Inc., Palo Alto,

More information

Solder joint reliability of plastic ball grid array with solder bumped flip chip

Solder joint reliability of plastic ball grid array with solder bumped flip chip ball grid array with solder bumped Shi-Wei Ricky Lee Department of Mechanical Engineering, The Hong Kong University of Science and, Kowloon, Hong Kong John H. Lau Express Packaging Systems, Inc., Palo

More information

Plasma for Underfill Process in Flip Chip Packaging

Plasma for Underfill Process in Flip Chip Packaging Plasma for Underfill Process in Flip Chip Packaging Jack Zhao and James D. Getty Nordson MARCH 2470-A Bates Avenue Concord, California 94520-1294 USA Published by Nordson MARCH www.nordsonmarch.com 2015

More information

ROOM TEMPERATURE FAST FLOW REWORKABLE UNDERFILL FOR LGA

ROOM TEMPERATURE FAST FLOW REWORKABLE UNDERFILL FOR LGA As originally published in the SMTA Proceedings ROOM TEMPERATURE FAST FLOW REWORKABLE UNDERFILL FOR LGA Mary Liu, Ph.D., and Wusheng Yin, Ph.D. YINCAE Advanced Materials, LLC Albany, NY, USA wyin@yincae.com

More information

High Reliable Non-Conductive Adhesives for Flip Chip CSP Applications

High Reliable Non-Conductive Adhesives for Flip Chip CSP Applications High Reliable Non-Conductive Adhesives for Flip Chip CSP Applications Myung-Jin Yim, Jin-Sang Hwang ACA/F Div., Telephus Co. 25-11, Jang-dong, Yusong-gu,, Taejon 35-71, Korea Tel.: +82-42-866-1461, Fax:

More information

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL 2017 IEEE 67th Electronic Components and Technology Conference SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL YoungRae Kim 1, JaeHun Bae 1, MinHwa Chang 1, AhRa Jo 1,

More information

EFFECTS OF RUBBER-MODIFIED ON THERMAL AND MECHANICAL PROPERTIES OF EPOXY MOLD COMPOUND. U. Mokhtar, R. Rasid, S. Ahmad and A.

EFFECTS OF RUBBER-MODIFIED ON THERMAL AND MECHANICAL PROPERTIES OF EPOXY MOLD COMPOUND. U. Mokhtar, R. Rasid, S. Ahmad and A. EFFECTS OF RUBBER-MODIFIED ON THERMAL AND MECHANICAL PROPERTIES OF EPOXY MOLD COMPOUND U. Mokhtar, R. Rasid, S. Ahmad and A. Jalar Universiti Kebangsaan Malaysia, 43600 UKM Bangi, Selangor, Malaysia. ABSTRACT

More information

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic

More information

Material based challenge and study of 2.1, 2.5 and 3D integration

Material based challenge and study of 2.1, 2.5 and 3D integration 1 Material based challenge and study of 2.1, 2.5 and 3D integration Toshihisa Nonaka Packaging Solution Center R&D Headquarters Hitachi Chemical Co., Ltd., Sep. 8, 2016 Hitachi Chemical Co., Ltd. 2010.

More information

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be

More information

Behaviors of QFN Packages on a Leadframe Strip

Behaviors of QFN Packages on a Leadframe Strip Behaviors of QFN Packages on a Leadframe Strip Eric Ouyang, Billy Ahn, Seng Guan Chow, Anonuevo Dexter, SeonMo Gu, YongHyuk Jeong, JaeMyong Kim STATS ChipPAC Inc 46429 Landing Parkway, Fremont, CA 94538,

More information

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Revision 0 2006 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the

More information

Flip Chip Joining on FR-4 Substrate Using ACFs

Flip Chip Joining on FR-4 Substrate Using ACFs Flip Chip Joining on FR-4 Substrate Using ACFs Anne Seppälä, Seppo Pienimaa*, Eero Ristolainen Tampere University of Technology Electronics Laboratory P.O. Box 692 FIN-33101 Tampere Fax: +358 3 365 2620

More information

Accurate Predictions of Flip Chip BGA Warpage

Accurate Predictions of Flip Chip BGA Warpage Accurate Predictions of Flip Chip BGA Warpage Yuan Li Altera Corporation 11 Innovation Dr, M/S 422 San Jose, CA 95134 ysli@altera.com, (48)544-758 Abstract Organic flip chip BGA has been quickly adopted

More information

Statement of Work (SOW) inemi Packaging TIG SiP Module Moldability Project

Statement of Work (SOW) inemi Packaging TIG SiP Module Moldability Project Statement of Work (SOW) inemi Packaging TIG SiP Module Moldability Project Version #1.0 Date: April 22, 2016 Project Leader: Billy Ahn, STATS ChipPAC Co-Project Leader: Anthony Yang, Moldex3D inemi Staff:

More information

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Li Zheng, Student Member, IEEE, and Muhannad S. Bakir, Senior Member, IEEE Georgia Institute of Technology Atlanta,

More information

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages Michael Hertl 1, Diane Weidmann 1, and Alex Ngai 2 1 Insidix, 24 rue du Drac, F-38180 Grenoble/Seyssins,

More information

EXTRA FINE PITCH FLIP CHIP ASSEMBLY PROCESS, UNDERFILL EVALUATION AND RELIABILITY

EXTRA FINE PITCH FLIP CHIP ASSEMBLY PROCESS, UNDERFILL EVALUATION AND RELIABILITY As originally published in the SMTA Proceedings EXTRA FINE PITCH FLIP CHIP ASSEMBLY PROCESS, UNDERFILL EVALUATION AND RELIABILITY Fei Xie, Ph.D. *, Daniel F. Baldwin, Ph.D. *, Han Wu *, Swapon Bhattacharya,

More information

Compression molding encapsulants for wafer-level embedded active devices

Compression molding encapsulants for wafer-level embedded active devices 2017 IEEE 67th Electronic Components and Technology Conference Compression molding encapsulants for wafer-level embedded active devices Wafer warpage control by epoxy molding compounds Kihyeok Kwon, Yoonman

More information

Study on Effect of Coupling Agents on Underfill Material in Flip Chip Packaging

Study on Effect of Coupling Agents on Underfill Material in Flip Chip Packaging 38 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 24, NO. 1, MARCH 2001 Study on Effect of Coupling Agents on Underfill Material in Flip Chip Packaging Shijian Luo, Member, IEEE, and

More information

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong White Paper Quality and Reliability Challenges for Package on Package By Craig Hillman and Randy Kong Background Semiconductor technology advances have been fulfilling Moore s law for many decades. However,

More information

Qualification of Thin Form Factor PWBs for Handset Assembly

Qualification of Thin Form Factor PWBs for Handset Assembly Qualification of Thin Form Factor PWBs for Handset Assembly Mumtaz Y. Bora Kyocera Wireless Corporation San Diego, Ca. 92121 mbora@kyocera-wreless.com Abstract: The handheld wireless product market place

More information

High Density PoP (Package-on-Package) and Package Stacking Development

High Density PoP (Package-on-Package) and Package Stacking Development High Density PoP (Package-on-Package) and Package Stacking Development Moody Dreiza, Akito Yoshida, *Kazuo Ishibashi, **Tadashi Maeda, Amkor Technology Inc. 1900 South Price Road, Chandler, AZ 85248, U.S.A.

More information

Mechanical Behavior of Flip Chip Packages under Thermal Loading

Mechanical Behavior of Flip Chip Packages under Thermal Loading Mechanical Behavior of Flip Packages under Thermal Loading *Shoulung Chen 1,2, C.Z. Tsai 1,3, Nicholas Kao 1,4, Enboa Wu 1 1 Institute of Applied Mechanics, National Taiwan University 2 Electronics Research

More information

Journal of Science and Technology The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA)

Journal of Science and Technology The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA) The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA) Zainudin Kornain a, Azman Jalar a, Rozaidi Rasid b, a Institute of Microengineering and Nanoelectronics

More information

2ND LEVEL INTERCONNECT RELIABILITY OF CERAMIC AREA ARRAY PACKAGES

2ND LEVEL INTERCONNECT RELIABILITY OF CERAMIC AREA ARRAY PACKAGES 2ND LEVEL INTERCONNECT RELIABILITY OF CERAMIC AREA ARRAY PACKAGES Shingo Sato, Noriyuki Shimizu*, Shin Matsuda, Shoji Uegaki and Sachio Ninomiya Kyocera Corporation Kyoto, Japan Biography Noriyuki Shimizu

More information

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Frank Grano, Felix Bruno Huntsville, AL Dana Korf, Eamon O Keeffe San Jose, CA Cheryl Kelley Salem, NH Joint Paper by Sanmina-SCI Corporation EMS, GTS

More information

Flip Chip - Integrated In A Standard SMT Process

Flip Chip - Integrated In A Standard SMT Process Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical

More information

23 rd ASEMEP National Technical Symposium

23 rd ASEMEP National Technical Symposium THE EFFECT OF GLUE BOND LINE THICKNESS (BLT) AND FILLET HEIGHT ON INTERFACE DELAMINATION Raymund Y. Agustin Janet M. Jucar Jefferson S. Talledo Corporate Packaging & Automation/ Q&R STMicroelectronics,

More information

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly Selection and Parameter Optimization for Reliable TMV Pop Assembly Brian Roggeman, David Vicari Universal Instruments Corp. Binghamton, NY, USA Roggeman@uic.com Martin Anselm, Ph.D. - S09_02.doc Lee Smith,

More information

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION YINCAE Advanced Materials, LLC WHITE PAPER November 2013 2014 YINCAE Advanced Materials, LLC - All Rights Reserved. YINCAE and the YINCAE

More information

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY Steven Perng, Tae-Kyu Lee, and Cherif Guirguis Cisco Systems, Inc. San Jose, CA, USA sperng@cisco.com Edward S. Ibe Zymet, Inc. East Hanover,

More information

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima Novel Materials and Activities for Next Generation Package Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima 1. Activities of Packaging Solution Center 2. Novel Materials for Next Gen.

More information

Application of Spacer Filled Silicone Die Adhesive in Stacked Chip Technology

Application of Spacer Filled Silicone Die Adhesive in Stacked Chip Technology Application of Spacer Filled Silicone Die Adhesive in Stacked Chip Technology Xuan Li, R. Wayne Johnson 200 Broun Hall, Auburn University, Auburn, Alabama 36849 lixuan1@eng.auburn.edu Johnson@eng.auburn.edu

More information

Characterization of Physical Properties of Roadware Clear Repair Product

Characterization of Physical Properties of Roadware Clear Repair Product Characterization of Physical Properties of Roadware Clear Repair Product November 5, 2009 Prof. David A. Lange University of Illinois at Urbana-Champaign Introduction Roadware MatchCrete Clear (MCC) is

More information

S/C Packaging Assembly Challenges Using Organic Substrate Technology

S/C Packaging Assembly Challenges Using Organic Substrate Technology S/C Packaging Assembly Challenges Using Organic Substrate Technology Presented by Bernd Appelt ASE Group Nov. 17, 2009 Overview The Packaging Challenge Chip Substrate Interactions Stiffeners for FC-BGA

More information

IPC -7095C Design and Assembly Process Implementation For BGAs

IPC -7095C Design and Assembly Process Implementation For BGAs IPC -7095C Design and Assembly Process Implementation For BGAs 1 Overview With the introduction of BGA components, things had to change: New design New assembly process New repair process New inspection

More information

Microelectronic Materials CATALOG

Microelectronic Materials CATALOG Microelectronic Materials CATALOG LORD partners with customers to leverage expertise in multiple chemistries and diverse applications to develop customized solutions. Design Without Compromise At LORD,

More information

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Yuci Shen *1, Leilei Zhang ** and Xuejun Fan * * Lamar University, Beaumont, Texas ** NVIDIA Corporation, Santa Clara, California

More information

TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING

TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING Alec J. Babiarz Asymtek Carlsbad, CA, USA ajbabiarz@asymtek.com ABSTRACT Jetting fluids in semiconductor packaging and assembly has become an

More information

JOINT INDUSTRY STANDARD

JOINT INDUSTRY STANDARD JOINT INDUSTRY STANDARD AUGUST 1999 Semiconductor Design Standard for Flip Chip Applications ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES Semiconductor Design Standard for Flip Chip Applications About

More information

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Advanced Packaging Business Development Asia Introduction to Fan-Out WLP Introduction World of mobile gadgetry continues to rapidly evolve

More information

Basic Project Information. Background. Version: 2.0 Date: June 29, Project Leader: Bart Vandevelde (imec) inemi Staff: Grace O Malley

Basic Project Information. Background. Version: 2.0 Date: June 29, Project Leader: Bart Vandevelde (imec) inemi Staff: Grace O Malley inemi Statement of Work (SOW) Packaging TIG Impact of Low CTE Mold Compound on 2nd Level Solder Joint Reliability Project, Phase 2 (Experimental build and testing) Version: 2.0 Date: June 29, 2015 Project

More information

inemi Statement of Work (SOW) inemi Packaging TIG Impact of Low CTE Mold Compound on 2nd Level Solder Joint Reliability Phase 1 & Phase 2

inemi Statement of Work (SOW) inemi Packaging TIG Impact of Low CTE Mold Compound on 2nd Level Solder Joint Reliability Phase 1 & Phase 2 inemi Statement of Work (SOW) inemi Packaging TIG Impact of Low CTE Mold Compound on 2nd Level Solder Joint Reliability Phase 1 & Phase 2 Version: 4.1 Date: March 26, 2014 Project Leader: Bart Vandevelde

More information

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Amkor Technology, Inc. White Paper Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Abstract Expanding its ChipArray Ball Grid Array (CABGA) package form factor miniaturization

More information

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking Hisada et al.: FEM Analysis on Warpage and Stress at the Micro Joint (1/6) [Technical Paper] FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking Takashi Hisada*, Yasuharu Yamada*,

More information

Characterization of Coined Solder Bumps on PCB Pads

Characterization of Coined Solder Bumps on PCB Pads Characterization of Coined Solder Bumps on PCB Pads Jae-Woong Nah, Kyung W. Paik, Won-Hoe Kim*, and Ki-Rok Hur** Department of Materials Sci. & Eng., Korea Advanced Institute of Science and Technology

More information

EVALUATION OF HIGH RELIABILITY REWORKABLE EDGE BOND ADHESIVES FOR BGA APPLICATIONS

EVALUATION OF HIGH RELIABILITY REWORKABLE EDGE BOND ADHESIVES FOR BGA APPLICATIONS As originally published in the SMTA Proceedings. EVALUATION OF HIGH RELIABILITY REWORKABLE EDGE BOND ADHESIVES FOR BGA APPLICATIONS Fei Xie, Ph.D., Han Wu, Daniel F. Baldwin, Ph.D., Swapan Bhattacharya,

More information

Gold to gold thermosonic bonding Characterization of bonding parameters

Gold to gold thermosonic bonding Characterization of bonding parameters Gold to gold thermosonic bonding Characterization of bonding parameters Thi Thuy Luu *1, Hoang-Vu Nguyen 1, Andreas Larsson 2, Nils Hoivik 1 and Knut E.Aasmundtveit 1 1: Institute of Micro and Nanosystems

More information

System Level Effects on Solder Joint Reliability

System Level Effects on Solder Joint Reliability System Level Effects on Solder Joint Reliability Maxim Serebreni 2004 2010 Outline Thermo-mechanical Fatigue of solder interconnects Shear and tensile effects on Solder Fatigue Effect of Glass Style on

More information

Flex Based Chip Scale Packages Meeting the Cost/Performance Challenges

Flex Based Chip Scale Packages Meeting the Cost/Performance Challenges Flex Based Chip Scale Packages Meeting the Cost/Performance Challenges R. D. Schueller, E. A. Bradley, and P. M. Harvey 3M Electronic Product Division Austin, Texas Introduction A number of terms have

More information

Microelectronic Materials. Catalog

Microelectronic Materials. Catalog Microelectronic Materials Catalog LORD partners with customers to leverage expertise in multiple chemistries and diverse applications to develop customized solutions. Design Without Compromise At LORD,

More information

Selective Flux Jetting Plays Key Role In the Optimization of Process Results For Advanced Packaging Applications

Selective Flux Jetting Plays Key Role In the Optimization of Process Results For Advanced Packaging Applications Selective Flux Jetting Plays Key Role In the Optimization of Process Results For Advanced Packaging Applications Written for Advanced Packaging By Fabio Okada Over the past few years, many new production

More information

Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages

Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages Jae-Won Jang* a, Kyoung-Lim Suk b, Kyung-Wook Paik b, and Soon-Bok Lee a a Dept. of Mechanical Engineering, KAIST, 335 Gwahangno

More information

Dam and Fill Encapsulation for Microelectronic Packages

Dam and Fill Encapsulation for Microelectronic Packages Dam and Fill Encapsulation for Microelectronic Packages Steven J. Adamson, Christian Q. Ness Asymtek 2762 Loker Avenue West Carlsbad, CA 92008 Tel: 760-431-1919; Fax: 760-930-7487 Email: info@asymtek.com;

More information

Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging

Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging Y. W. Pok, D. Sujan, M. E. Rahman, S. S. Dol School of Engineering and Science, Curtin University Sarawak Campus, CDT

More information

Chips Face-up Panelization Approach For Fan-out Packaging

Chips Face-up Panelization Approach For Fan-out Packaging Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips

More information

Package Design Optimization and Materials Selection for Stack Die BGA Package

Package Design Optimization and Materials Selection for Stack Die BGA Package Package Design Optimization and Materials Selection for Stack Die BGA Package Rahul Kapoor, Lim Beng Kuan, Liu Hao United Test & Assembly Center Ltd (UTAC) 5 Serangoon North Ave 5, Singapore 554916 Email:

More information

Alternative Approaches to 3-Dimensional Packaging and Interconnection

Alternative Approaches to 3-Dimensional Packaging and Interconnection Alternative Approaches to 3-Dimensional Packaging and Interconnection Joseph Fjelstad SiliconPipe, Inc. www.sipipe.com IC Packaging a Technology in Transition In the past, IC packaging has been considered

More information

Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability

Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability Raghunandan Chaware, Ganesh Hariharan, Jeff Lin, Inderjit Singh, Glenn O Rourke, Kenny Ng, S. Y. Pai Xilinx Inc.

More information

"ewlb Technology: Advanced Semiconductor Packaging Solutions"

ewlb Technology: Advanced Semiconductor Packaging Solutions "ewlb Technology: Advanced Semiconductor Packaging Solutions" by Sharma Gaurav@, S.W. Yoon, Yap Yok Mian, Shanmugam Karthik, Yaojian Lin, Pandi C. Marimuthu and Yeong J. Lee* STATS ChipPAC Ltd. 5 Yishun

More information

INEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D.

INEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D. INEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D. Date (4/10/2014) AEG - WW Microelectronics and Packaging OUTLINE Overview

More information

HOW THE MOLD COMPOUND THERMAL EXPANSION OVERRULES THE SOLDER COMPOSITION CHOICE IN BOARD LEVEL RELIABILITY PERFORMANCE

HOW THE MOLD COMPOUND THERMAL EXPANSION OVERRULES THE SOLDER COMPOSITION CHOICE IN BOARD LEVEL RELIABILITY PERFORMANCE HOW THE MOLD COMPOUND THERMAL EXPANSION OVERRULES THE SOLDER COMPOSITION CHOICE IN BOARD LEVEL RELIABILITY PERFORMANCE AUTHORS: B. VANDEVELDE, L. DEGRENDELE, M. CAUWE, B. ALLAERT, R. LAUWAERT, G. WILLEMS

More information

REDUCTION OF WARPAGE OCCURRENCE STACK-DIE QFN THROUGH FEA AND STATISTICAL METHOD

REDUCTION OF WARPAGE OCCURRENCE STACK-DIE QFN THROUGH FEA AND STATISTICAL METHOD REDUCTION OF WARPAGE OCCURRENCE STACK-DIE QFN THROUGH FEA AND STATISTICAL METHOD I. Abdullah, M. Z. M. Talib, I. Ahmad, M. N. B. C. Kamarudin and N. N. Bachok Faculty of Engineering,Universiti Kebangsaan

More information

Flip-Chip Process Improvements for Low Warpage

Flip-Chip Process Improvements for Low Warpage Flip-Chip Process Improvements for Low Warpage Robert L. Hubbard Lambda Technologies, Inc. Morrisville, NC, USA bhubbard@microcure.com Pierino Zappella*, Pukun Zhu Henkel Corporation Irvine, CA, USA Abstract

More information

Optoelectronic Chip Assembly Process of Optical MCM

Optoelectronic Chip Assembly Process of Optical MCM 2017 IEEE 67th Electronic Components and Technology Conference Optoelectronic Chip Assembly Process of Optical MCM Masao Tokunari, Koji Masuda, Hsiang-Han Hsu, Takashi Hisada, Shigeru Nakagawa, Science

More information

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA)

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Seung Wook Yoon, Yaojian Lin and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 E-mail

More information

Flip-Chip Process Improvements for Low Warpage

Flip-Chip Process Improvements for Low Warpage Flip-Chip Process Improvements for Low Warpage Robert L. Hubbard Lambda Technologies, Inc. Morrisville, NC, USA bhubbard@microcure.com Pierino Zappella*, Pukun Zhu Henkel Corporation Irvine, CA, USA Abstract

More information

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong

More information

Reliability of Interconnects in LED Lighting Assemblies Utilizing Metal Clad Printed Circuit Boards Stefano Sciolè BDM I.M.S.

Reliability of Interconnects in LED Lighting Assemblies Utilizing Metal Clad Printed Circuit Boards Stefano Sciolè BDM I.M.S. Reliability of Interconnects in LED Lighting Assemblies Utilizing Metal Clad Printed Circuit Boards Stefano Sciolè BDM I.M.S. Henkel Electronic Materials Agenda 1. Introduction 2. Motivation 3. Interconnect

More information

TRADITIONALLY, epoxy based encapsulants are filled

TRADITIONALLY, epoxy based encapsulants are filled 54 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 22, NO. 1, FEBRUARY 1999 Comparative Study of Thermally Conductive Fillers for Use in Liquid Encapsulants for Electronic Packaging C. P. Wong, Fellow, IEEE,

More information

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications M. Gonzalez 1, B. Vandevelde 1, Jan Vanfleteren 2 and D. Manessis 3 1 IMEC, Kapeldreef 75, 3001, Leuven,

More information

Wafer/Panel Level Package Flowability and Warpage Project. Call for Sign-up Webinar

Wafer/Panel Level Package Flowability and Warpage Project. Call for Sign-up Webinar Wafer/Panel Level Package Flowability and Warpage Project Call for Sign-up Webinar Project Chair: Renn Chan Ooi, Intel Corporation Tanja Braun, Fraunhofer IZM inemi Staff: Haley Fu Session 2: Thursday,

More information

Next Gen Packaging & Integration Panel

Next Gen Packaging & Integration Panel Next Gen Packaging & Integration Panel ECTC 2012 Daniel Tracy, Sr. Director Industry Research & Statistics SEMI May 29, 2012 Packaging Supply Chain Market Trends Material Needs and Opportunities Market

More information

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Amy Palesko Lujan SavanSys Solutions LLC 10409 Peonia Court Austin,

More information

BGA Package Underfilm for Autoplacement. Jan Danvir Tom Klosowiak

BGA Package Underfilm for Autoplacement. Jan Danvir Tom Klosowiak BGA Package Underfilm for Autoplacement Jan Danvir Tom Klosowiak NIST-ATP Acknowledgment Project Brief Microelectronics Manufacturing Infrastructure (October 1998) Wafer-Scale Applied Reworkable Fluxing

More information

Thermomechanical Response of Anisotropically Conductive Film

Thermomechanical Response of Anisotropically Conductive Film Thermomechanical Response of Anisotropically Conductive Film Yung Neng Cheng, Shyong Lee and Fuang Yuan Huang Department of Mechanical Engineering National Central University, Chung-li, Taiwan shyong@cc.ncu.edu.tw

More information

Processor Performance, Packaging and Reliability Utilizing a Phase Change Metallic Alloy Thermal Interface System

Processor Performance, Packaging and Reliability Utilizing a Phase Change Metallic Alloy Thermal Interface System Processor Performance, Packaging and Reliability Utilizing a Phase Change Metallic Alloy Thermal Interface System Chris G. Macris, Thomas R. Sanderson, Robert G. Ebel, Christopher B. Leyerle Enerdyne Solutions,

More information

Molding materials performances experimental study for the 3D interposer scheme

Molding materials performances experimental study for the 3D interposer scheme Minapad 2014, May 21 22th, Grenoble; France Molding materials performances experimental study for the 3D interposer scheme Y. Sinquin, A. Garnier, M. Argoud, A. Jouve, L. Baud, J. Dechamp, N. Allouti,

More information

CSP Die Shrink Solution for Memory Devices

CSP Die Shrink Solution for Memory Devices CSP Die Shrink Solution for Memory Devices Young G. Kim, Nader Gamini, and Craig Mitchell youngk@tessera.com, 408-894-0700 ngamini@rambus.com, 650-944-7806 craigm@tessera.com, 408-894-0700 Abstract The

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE

GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE Bev Christian, Linda Galvis, Rick Shelley and Matthew Anthony BlackBerry Cambridge, Ontario, CANADA bchristian@blackberry.com ABSTRACT:

More information

Pressure-Assisted Low-Temperature Sintering of Silver Paste as an Alternative Die-Attach Solution to Solder Reflow

Pressure-Assisted Low-Temperature Sintering of Silver Paste as an Alternative Die-Attach Solution to Solder Reflow Pressure-Assisted Low-Temperature Sintering of Silver Paste as an Alternative Die-Attach Solution to Solder Reflow Zhiye (Zach) Zhang and Guo-Quan Lu Center for Power Electronics Systems The Bradley Department

More information

STYCAST 2850 FT Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity

STYCAST 2850 FT Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity Key Feature High thermal conductivity Wide variety of catalysts Low coefficient of thermal expansion Product Description : Benefit Heat dissipation from embedded components Versatility of resin system

More information

STYCAST 2850 FT. Technical Data. Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity

STYCAST 2850 FT. Technical Data. Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity Key Feature High thermal conductivity Wide variety of catalysts Low coefficient of thermal expansion Product Description : Benefit

More information

IBM Research Report. The Over-Bump Applied Resin Wafer-Level Underfill Process: Process, Material and Reliability

IBM Research Report. The Over-Bump Applied Resin Wafer-Level Underfill Process: Process, Material and Reliability RC24851 (W0908-142) August 31, 2009 Other IBM Research Report The Over-Bump Applied Resin Wafer-Level Underfill Process: Process, Material and Reliability Claudius Feger, Nancy LaBianca, Michael Gaynes,

More information

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages by Ming-Che Hsieh STATS ChipPAC Taiwan Co. Ltd. Copyright 2013. Reprinted from 2013 International Microsystems,

More information

Encapsulation Materials Technology For SiP in Automotive

Encapsulation Materials Technology For SiP in Automotive Encapsulation Materials Technology For SiP in Automotive Oct. 17. 2018 Panasonic Corporation Electronic Materials Business Division Our Business Fields Electronic Instruments Networking equipment Smart

More information

STYCAST 2850 FT. Technical Data. Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity

STYCAST 2850 FT. Technical Data. Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity Key Feature High thermal conductivity Wide variety of catalysts Low coefficient of thermal expansion Product Description : Benefit Heat dissipation from embedded components Versatility of resin system

More information

STYCAST 2850 FT Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity

STYCAST 2850 FT Two Component, Versatile Epoxy Encapsulant With High Thermal Conductivity Key Feature High thermal conductivity Wide variety of catalysts Low coefficient of thermal expansion Product Description : Benefit Heat dissipation from embedded components Versatility of resin system

More information

Assembly and Rework of Lead Free Package on Package Technology By: Raymond G. Clark and Joseph D. Poole TT Electronics - IMS Perry, Ohio

Assembly and Rework of Lead Free Package on Package Technology By: Raymond G. Clark and Joseph D. Poole TT Electronics - IMS Perry, Ohio Assembly and Rework of Lead Free Package on Package Technology By: Raymond G. Clark and Joseph D. Poole TT Electronics - IMS Perry, Ohio Abstract: Miniaturization continues to be a driving force in both

More information