Wafer/Panel Level Package Flowability and Warpage Project. Call for Sign-up Webinar

Size: px
Start display at page:

Download "Wafer/Panel Level Package Flowability and Warpage Project. Call for Sign-up Webinar"

Transcription

1 Wafer/Panel Level Package Flowability and Warpage Project Call for Sign-up Webinar Project Chair: Renn Chan Ooi, Intel Corporation Tanja Braun, Fraunhofer IZM inemi Staff: Haley Fu Session 2: Thursday, March 15, 2018 China Time: 9:00-10:00 pm US EDT: 9:00-10:00 pm Recording (available for up to 6 months after webinar):

2 Agenda Introduction of Project Chairs inemi Project Development Process Project Briefing Companies Involved in Planning Background & Objectives Project Scope Project IS/IS Not Work Plan Schedule How to Join Q&A Note: All phones will be on mute until the end of the presentation

3 Introduction of Project Chairs Renn Chan Ooi, Intel Corporation Renn Chan joined Intel Corp since 2005 and is Senior Assembly & Packaging Analyst focusing on encapsulation and assembly technology challenges. Received doctorate degree in Mechanical Engineering from University of Sheffield, UK in Field of interest includes thermo-fluids analysis for assembly processes, imaging processing and assembly flow visualization. Tanja Braun, Fraunhofer IZM Tanja joined Fraunhofer IZM in Recent research is focused on wafer and panel level packaging technologies. She is head of the group Assembly & Encapsulation Technologies since Lead the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin. Received Dr. degree from Technical University of Berlin in Holds several patents in the field of advanced packaging. 3

4 Successful inemi Projects Address knowledge gap(s) of industry: Common problem Best solved by working together Timed success that aligns to business needs Best manifested on complex far reaching issues Often includes reliability testing & verification Requires teamwork across multiple levels of the supply chain: Ensures efficient alignment of goals and investments of the varied team players; Supports the company s commercial interests. Delivers a coordinated industry wide response and capability set. OEM/ODM/EMS/OSATs/Suppliers at multiple levels.

5 inemi Project Development Process - 5 Steps 0 1 INPUT SELECTION We are here DEFINITION PLANNING EXECUTION / REVIEW CLOSURE Initiative Open for Industry input inemi Technical Committee (TC) Approval Required for Execution Project Limited to committed Members

6 inemi Project Management Policy Two governing documents for projects Statement of work (SOW): sets out project scope, background, purpose, benefits, and outlines required resources, materials, processes, project schedule, etc. Project Statement (PS): signed by participating companies to secure commitment on resource and time contributions. inemi Project requires inemi membership Signed membership agreement Commitment to follow inemi By-laws and IP policy 6

7 Project Briefing

8 Companies Contributed to Project Formation

9 Background & Objectives Industry adaptation of wafer size > Φ300mm or panel > 300x300mm 2. Flowability of mold impacts the quality and potentially warpage of the wafer/panel for subsequent processes: Need to identify key processing factors that impacts followability. Establish factors from flowability that impacts warpage. Establish other material factors that impact post mold warpage.

10 Scope 1 - Flowability: Focus and Strategy Granular powder: Low flowability risk from initial members discussion, considered for warpage study. Challenges of the keep out zone (KOZ) at wafer/panel peripherals and the impact to flow and warpage. Liquid dispense: Dispense pattern dictates knit lines/weld lines. Identify risk of flying dies from molding pressure. Understand material behavior of selected candidates. Identify working window and the cliff of failure. Explore opportunities from process parameters to mitigate flow issues. Challenges of the KOZ at wafer/panel peripherals and the impact to flow and warpage. Sheet lamination: Challenges of the KOZ at wafer/panel peripherals and the impact to flow and warpage. Issue of die displacement. Understand material behavior of selected candidates, identify working window and the cliff of failure. Explore opportunities from process parameters to mitigate flow issues. KOZ

11 Scope 2 - Warpage: Focus and Strategy Simulation & Experimental Approach: Understand warpage related material property from material candidates. Prelim warpage simulation to identify feasible range of sample dimensions. Conduct actual molding for model validation and process understanding. Failure analysis (cross section) of mold material behavior. Final simulation DOEs for warpage optimization from process and material aspect. Chemical Shrinkage: Methodology in measuring mold material chemical shrinkage. Capability of incorporating it in warpage modeling explore readiness of simulation software. The need for benchmark material with minimum or almost zero chemical shrinkage.

12 Project Scope: Is/Is Not Analysis This Project IS: This Project IS NOT: To conduct mold material property measurements. To conduct solder joint reliability. To conduct mold flow and warpage simulation to understand key modulating factors. To evaluate RDL processes before/after mold. To conduct molding experiments on test vehicles based on simulation results. To develop specific standard(s). To evaluate flowability of mold process through inspection of void, flow marks, etc. Biased towards specific suppliers, geographies or market segment. To evaluate warpage of mold process through measurement tools.

13 Work Plan Step 1 Step 1 Material characterization and preliminary simulation Task 1: Process & TV finalize and source dummy die, panel, and other collaterals for project Mold first up until de-bonding on metal carrier. Wafer size >300mm and panel size of 400x400~600x600mm2. Dummy die size of 10x10mm with um silicon thickness. Mold thickness range from 00 to 500um. Die to die spacing 1/4 ~1x die size. Silicon die selection: pure silicon, dummy die with bump, etc. Task 2: Mold compound selection Up to 3 or more mold materials to be studied. Task 3: Molding material characterization for flowability and warpage simulation Curing kinetics (Kamal s model). Rheokinetics (Macosko model). TMA, DMA, modulus, Poisson s ratio measurements, etc., for warpage. Task 4: Chemical shrinkage measurement Comparison of chemical shrinkage measurements methodology. Application into curing and warpage simulation (e.g., PVTc models, etc.). Task 5: Conduct preliminary flow simulation to gain further insight Preliminary flow simulation to call out potential flow related risks and aide decision in finalizing/update test vehicle attributes. Task 6: Conduct preliminary warpage simulation with additional focus on chemical shrinkage Preliminary warpage simulation to call out potential CTE mismatch and chemical shrinkage related risks and aide decision in finalizing/update test vehicle attributes. Ack: Moldex3D

14 Work Plan Step 2 Step 2 Molding experiments Task 7: Conduct molding of selected test vehicles Assemble finalized test vehicle and conduct selected molding process. Task 8: Conduct flowability inspection of test vehicles Potential short-shot, visual inspections, post assembly failure analyses, silica particle distributions, etc., for flowability assessment. Flow simulation model fine tuning for flowability prediction. Task 9: Conduct warpage measurements of test vehicles Conduct warpage measurement and post assembly failure analyses. Thermo-mechanical simulation model fine tuning for warpage prediction.

15 Work Plan Step 3 Step 3 Final simulation DOEs Task 10: Finalize flow and warpage simulation DOEs to identify key modulating factors and process optimizations Finalize second round of simulation DOEs based on preliminary simulation and actual unit assembly learnings. Task 11: Conduct final simulation DOEs Conduct second round of simulation DOEs to cover working range and limits of flowability and warpage behavior of test vehicle and technology. Task 12: Data analysis and review for final reporting

16 Schedule Q1 Q2 Q3 Q4 Q5 Task 0: Literature research X X X X X X X X X X X X X Step 1: Material characterization and preliminary simulation Checkpoint 1 Task 1: Finalize process and TV, and source X X dummy die, panel, and other collaterals Task 2: Mold compound selection X Task 3: Mold characterization X X X Task 4: Chemical shrinkage measurement X X X Task 5: Preliminary flow simulation X X Task 6: Preliminary warpage simulation X X Step 2: Molding experiment Checkpoint 2 Task 7: Molding of test vehicles X X Task 8: Flowability inspection of test vehicles X Task 9: Warpage measurements of test vehicles X Step 3: Final simulation Task 10: Finalize the 2nd round simulation DOE X Task 11: Conduct simulation X X Task 12: Data analysis and final reporting X X

17 Expected Project Participants This project looks forward to the participation of epoxy mold compound manufacturers, component suppliers, molding tool manufacturers, mold flow simulation software companies, thermos-mechanical warpage simulation software companies, PCB fabricators, OSATS, foundries, and manufacturing research institutes. 17

18 How to Join

19 Sign-Up Due on April 14, 2018 inemi membership is required to join the project Download SOW and PS from inemi web: Sign the PS Signature of representative of participants Signature of manager approval Send scanned PS to inemi VP of Operations will sign and approve your participation and send you back the completed PS with acceptance Join inemi membership, or questions, contact Haley Fu 19

20 Resource In-kind Contribution Please input "Yes" for those items that your firm plans to provide in-kind support to this project. Specify in detail if need in the bottom cell. The final experimental design and test vehicle design will be decided and agreed by the project team. Area Resource Needed In-kind Contribution Mold compound Dummy silicon die Materials Carrier Substrates Shield fence area and components for assembly Other area of interest/components to be included in the study Simulation Test vehicle assembly Measurement/Test Failure analysis Others Detail description of your in-kind contribution Flow and warpage simulation Assembly facilities or services to build test vehicles Mold material properties Curing kinetics (Kamal s model) Rheokinetics (Macosko model) TMA DMA Modulus Poisson s ratio measurements Chemical shrinkage measurements Flowability inspection Warpage measurement Failure analysis of final assembled test vehicles Other suggested task with associated resource contribution 20

21 Questions?

22 Haley Fu

Warpage Characteristics of Organic Packages, Phase 4

Warpage Characteristics of Organic Packages, Phase 4 Warpage Characteristics of Organic Packages, Phase 4 Chairs: Wei Keat Loh, Intel Ron Kulterman, Flex Call for Sign-up Webinar July 27 th /28 th, 2017 inemi Staff: Haley Fu Agenda Introduction of Project

More information

Chips Face-up Panelization Approach For Fan-out Packaging

Chips Face-up Panelization Approach For Fan-out Packaging Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips

More information

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum IME Technical Proposal High Density FOWLP for Mobile Applications 22 April 2014 Packaging driver for portable / mobile applications Key drivers/needs Smaller form-factor lower profile, substrate-less Higher

More information

PCB/PCBA Material Characterization for Automotive Harsh Environments

PCB/PCBA Material Characterization for Automotive Harsh Environments PCB/PCBA Material Characterization for Automotive Harsh Environments Project Chair: Steve Brown MacDermid Performance Solutions inemi Staff: Steve Payne Agenda Introduction of Project Chair and inemi Project

More information

Approaches to minimize Printed Circuit Board (PCB) warpage in Board Assembly Process to improve SMT Yield

Approaches to minimize Printed Circuit Board (PCB) warpage in Board Assembly Process to improve SMT Yield Approaches to minimize Printed Circuit Board (PCB) warpage in Board Assembly Process to improve SMT Yield Initiative Leaders: Srini Aravamudhan & Chris Combs, Intel; inemi Staff: Haley Fu The Project Development

More information

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C EPRC 12 Project Proposal Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C 15 th August 2012 Page 1 Motivation Increased requirements of high power semiconductor device

More information

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics

More information

Call for Participation In High Speed Signaling Metrology and Standard Reliability Qualification Project Formation

Call for Participation In High Speed Signaling Metrology and Standard Reliability Qualification Project Formation Call for Participation In High Speed Signaling Metrology and Standard Reliability Qualification Project Formation Session 1 Friday, March 14 10:00 am 11:00 am EDT inemi Connectors Interest Survey Background

More information

Panel Discussion: Advanced Packaging

Panel Discussion: Advanced Packaging Dr. Steve Bezuk Senior Director IC Packaging Engineering Qualcomm Technologies, Inc. Panel Discussion: Advanced Packaging PAGE 1 Technical Challenges of Packaging (Mobile Focus) Materials Die materials

More information

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY B. Rogers, C. Scanlan, and T. Olson Deca Technologies, Inc. Tempe, AZ USA boyd.rogers@decatechnologies.com ABSTRACT Fan-Out Wafer-Level Packaging

More information

Packaging Substrate Workshop Wrap Up. Bob Pfahl, inemi

Packaging Substrate Workshop Wrap Up. Bob Pfahl, inemi Packaging Substrate Workshop Wrap Up Bob Pfahl, inemi Warpage Facilitator: Jie Xue, Cisco Presenter: ML Loke, Intel Breakout Session (ends 10:30 am) Introduction & your expectation Issues & Root cause

More information

23 rd ASEMEP National Technical Symposium

23 rd ASEMEP National Technical Symposium THE EFFECT OF GLUE BOND LINE THICKNESS (BLT) AND FILLET HEIGHT ON INTERFACE DELAMINATION Raymund Y. Agustin Janet M. Jucar Jefferson S. Talledo Corporate Packaging & Automation/ Q&R STMicroelectronics,

More information

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Henry M.W. Sze, Marc Papageorge ASAT Limited 14th Floor, QPL Industrial Building, 138 Texaco Road, Tseun Wan, Hong

More information

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Challenges and Solutions for Cost Effective Next Generation Advanced Packaging H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Outline Next Generation Package Requirements ewlb (Fan-Out Wafer

More information

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology by Meenakshi Prashant, Seung Wook Yoon, Yaojian LIN and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

More information

Modelling Embedded Die Systems

Modelling Embedded Die Systems Modelling Embedded Die Systems Stoyan Stoyanov and Chris Bailey Computational Mechanics and Reliability Group (CMRG) University of Greenwich, London, UK 22 September 2016 IMAPS/NMI Conference on EDT Content

More information

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima Novel Materials and Activities for Next Generation Package Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima 1. Activities of Packaging Solution Center 2. Novel Materials for Next Gen.

More information

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan 3D Package Technologies Review with Gap Analysis for Mobile Application Requirements Apr 22, 2014 STATS ChipPAC Japan T.Nishio Contents Package trends and roadmap update Advanced technology update Fine

More information

Project Proposal. Cu Wire Bonding Reliability Phase 3 Planning Webinar. Peng Su June 6, 2014

Project Proposal. Cu Wire Bonding Reliability Phase 3 Planning Webinar. Peng Su June 6, 2014 Project Proposal Cu Wire Bonding Reliability Phase 3 Planning Webinar Peng Su June 6, 2014 Problem Statement Background Work of the inemi Cu wire reliability project identified that bonding quality and

More information

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip EPRC 12 Project Proposal Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip 15 th Aug 2012 Page 1 Introduction: Motivation / Challenge Silicon device with ultra low k

More information

Roundtable 3DIC & TSV: Ready for HVM? European 3D TSV Summit

Roundtable 3DIC & TSV: Ready for HVM? European 3D TSV Summit Roundtable 3DIC & TSV: Ready for HVM? European 3D TSV Summit Infineon VTI Xilinx Synopsys Micron CEA LETI 2013 Yann Guillou Business Development Manager Lionel Cadix Market & Technology Analyst, Advanced

More information

Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3)

Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3) Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3) Wei Keat Loh 1, Ron Kulterman 2, Haley Fu 3, Masahiro Tsuriya 3 1 Intel Technology Sdn. Bhd.

More information

DIELECTRICS FOR EMBEDDING ACTIVE AND PASSIVE COMPONENTS

DIELECTRICS FOR EMBEDDING ACTIVE AND PASSIVE COMPONENTS DIELECTRICS FOR EMBEDDING ACTIVE AND PASSIVE COMPONENTS J. Kress, R. Park, A. Bruderer, and N. Galster Atotech Deutschland GmbH Basle, Switzerland juergen.kress@atotech.com SH Cho Dongyang Mirae University

More information

Package Solutions and Innovations

Package Solutions and Innovations Package Solutions and Innovations with Compression Molding IEEE SVC CPMT Aug 2015 Presented by C.H. Ang Towa USA Company Profile www.cpmt.org/scv 1 Corporate Overview Company: Towa Corp., Kyoto Japan Established:

More information

Innovative Substrate Technologies in the Era of IoTs

Innovative Substrate Technologies in the Era of IoTs Innovative Substrate Technologies in the Era of IoTs Dyi- Chung Hu 胡迪群 September 4, 2015 Unimicron Contents Introduction Substrate Technology - Evolution Substrate Technology - Revolution Glass substrate

More information

Recent Advances in Die Attach Film

Recent Advances in Die Attach Film Recent Advances in Die Attach Film Frederick Lo, Maurice Leblon, Richard Amigh, and Kevin Chung. AI Technology, Inc. 70 Washington Road, Princeton Junction, NJ 08550 www.aitechnology.com Abstract: The

More information

Avatrel Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications

Avatrel Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications Avatrel Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications Ed Elce, Chris Apanius, Jeff Krotine, Jim Sperk, Andrew Bell, Rob Shick* Sue Bidstrup-Allen, Paul Kohl Takashi Hirano,

More information

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs)

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs) 1 Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs) Xi Liu Ph.D. Student and Suresh K. Sitaraman, Ph.D. Professor The George W. Woodruff School of Mechanical Engineering Georgia Institute of

More information

Flip Chip - Integrated In A Standard SMT Process

Flip Chip - Integrated In A Standard SMT Process Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical

More information

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION NCCAVS Joint Users Group Technical Symposium San Jose, June 7 th, 2017 Markus Arendt, SÜSS MicroTec

More information

Selection and Application of Board Level Underfill Materials

Selection and Application of Board Level Underfill Materials Selection and Application of Board Level Underfill Materials Developed by the Underfill Materials Design, Selection and Process Task Group (5-24f) of the Assembly and Joining Committee (5-20) of IPC Supersedes:

More information

Challenges for Embedded Device Technologies for Package Level Integration

Challenges for Embedded Device Technologies for Package Level Integration Challenges for Embedded Device Technologies for Package Level Integration Kevin Cannon, Steve Riches Tribus-D Ltd Guangbin Dou, Andrew Holmes Imperial College London Embedded Die Technology IMAPS-UK/NMI

More information

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION YINCAE Advanced Materials, LLC WHITE PAPER November 2013 2014 YINCAE Advanced Materials, LLC - All Rights Reserved. YINCAE and the YINCAE

More information

3D-WLCSP Package Technology: Processing and Reliability Characterization

3D-WLCSP Package Technology: Processing and Reliability Characterization 3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc. 2012 1 Outline Packaging

More information

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic

More information

Innovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA

Innovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA Innovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA Director, STATS ChipPAC Outline 1 2 3 Introduction of Smart Manufacturing & Wafer Level Packaging

More information

Nano-Processing for High Voltage and High Power Devices. J. Parsey March 21, 2013

Nano-Processing for High Voltage and High Power Devices. J. Parsey March 21, 2013 Nano-Processing for High Voltage and High Power Devices J. Parsey March 21, 2013 Outline Background concepts Two nano ideas: New high voltage, high power FET device designs Application of nano-particles

More information

An Innovative High Throughput Thermal Compression Bonding Process

An Innovative High Throughput Thermal Compression Bonding Process An Innovative High Throughput Thermal Compression Bonding Process Li Ming 2 September 2015 Outline Introduction Throughput improved TCB Process Liquid Phase Contact (LPC) bonding Flux-LPC-TCB under inert

More information

Graser User Conference Only

Graser User Conference Only 2.5D/3D Design Solution Eric Chen & Scott Liu 31/Oct/2014 Roadmap data is provided for informational purposes only and does not represent a commitment to deliver any of the features or functionality discussed

More information

Advancements In Packaging Technology Driven By Global Market Return. M. G. Todd

Advancements In Packaging Technology Driven By Global Market Return. M. G. Todd Advancements In Packaging Technology Driven By Global Market Return M. G. Todd Electronic Materials, Henkel Corporation, Irvine, California 92618, USA Recently, the focus of attention in the IC packaging

More information

Solder joint reliability of cavity-down plastic ball grid array assemblies

Solder joint reliability of cavity-down plastic ball grid array assemblies cavity-down plastic ball grid array S.-W. Ricky Lee Department of Mechanical Engineering, The Hong Kong University of Science and, Kowloon, Hong Kong John H. Lau Express Packaging Systems, Inc., Palo Alto,

More information

"ewlb Technology: Advanced Semiconductor Packaging Solutions"

ewlb Technology: Advanced Semiconductor Packaging Solutions "ewlb Technology: Advanced Semiconductor Packaging Solutions" by Sharma Gaurav@, S.W. Yoon, Yap Yok Mian, Shanmugam Karthik, Yaojian Lin, Pandi C. Marimuthu and Yeong J. Lee* STATS ChipPAC Ltd. 5 Yishun

More information

Statement of Work (SOW) inemi Board Assembly TIG BiSn-Based Low-Temperature Soldering Process and Reliability Project

Statement of Work (SOW) inemi Board Assembly TIG BiSn-Based Low-Temperature Soldering Process and Reliability Project Statement of Work (SOW) inemi Board Assembly TIG BiSn-Based Low-Temperature Soldering Process and Reliability Project Version 1.4 Date: December 1, 2015 Project Leader: Raiyo Aspandiar, Intel Corporation

More information

Chip Packaging for Wearables Choosing the Lowest Cost Package

Chip Packaging for Wearables Choosing the Lowest Cost Package Chip Packaging for Wearables Choosing the Lowest Cost Package Alan Palesko alanp@savansys.com (512) 402-9943 www.savansys.com Slide - 1 Agenda Introduction Wearable Requirements Packaging Technologies

More information

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV. Die Attach Materials Die Attach G, TECH. 2U. TECHNICAL R&D DIV. 2 Topics 3 What it is X 5,000 X 10,000 X 50,000 Si Chip Au Plating Substrate Ag Resin 4 Current Products Characteristics H9890-6A H9890-6S

More information

Close supply chain collaboration enables easy implementation of chip embedded power SiP

Close supply chain collaboration enables easy implementation of chip embedded power SiP Close supply chain collaboration enables easy implementation of chip embedded power SiP Gerald Weidinger, R&D Project Leader, AT&S AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13

More information

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Amkor Technology, Inc. White Paper Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Abstract Expanding its ChipArray Ball Grid Array (CABGA) package form factor miniaturization

More information

System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb)

System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) Steffen Kröhnert, José Campos, Eoin O Toole NANIUM S.A., Vila do Conde, Portugal Outline Short Company Overview NANIUM Introduction

More information

Simulation of Embedded Components in PCB Environment and Verification of Board Reliability

Simulation of Embedded Components in PCB Environment and Verification of Board Reliability Simulation of Embedded Components in PCB Environment and Verification of Board Reliability J. Stahr, M. Morianz AT&S Leoben, Austria M. Brizoux, A. Grivon, W. Maia Thales Global Services Meudon-la-Forêt,

More information

Embedded Cooling Solutions for 3D Packaging

Embedded Cooling Solutions for 3D Packaging IME roprietary ERC 12 roject roposal Embedded Cooling Solutions for 3D ackaging 15 th August 2012 age 1 Technology & ower Dissipation Trends IME roprietary Cannot continue based on Moore s law scaling

More information

Qualification and Application of Pressure-less Sinter Silver Epoxy

Qualification and Application of Pressure-less Sinter Silver Epoxy Qualification and Application of Pressure-less Sinter Silver Epoxy Loh Kian Hwa, Nadzirah Yahya, Chin Siew Kheong, Lee Ken Hok Carsem Technology Centre Carsem (M) Sdn. Bhd S-site. Lot 52986 Taman Meru

More information

IPC-AJ-820A Assembly and Joining Handbook. The How and Why of All Things PCB & PCA

IPC-AJ-820A Assembly and Joining Handbook. The How and Why of All Things PCB & PCA IPC-AJ-820A Assembly and Joining Handbook The How and Why of All Things PCB & PCA 1 Scope To provide guidelines and supporting info for the mfg of electronic equipment To explain the HOW TO and WHY Discussions

More information

RF System in Packages using Integrated Passive Devices

RF System in Packages using Integrated Passive Devices RF System in Packages using Integrated Passive Devices by Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn STATS ChipPAC 1711 W. Greentree Drive, Suite #117, Tempe, AZ 85284, USA Tel: 480-222-1722

More information

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be

More information

Kevin O. Loutfy and Dr. Hideki Hirotsuru

Kevin O. Loutfy and Dr. Hideki Hirotsuru Advanced Diamond based Metal Matrix Composites for Thermal Management of RF Devices By Kevin O. Loutfy and Dr. Hideki Hirotsuru Agenda - Thermal Management Packaging Flange Materials - GaN High Power Densities

More information

Thermo-Mechanical Reliability Assessment of TSV Die Stacks by Finite Element Analysis

Thermo-Mechanical Reliability Assessment of TSV Die Stacks by Finite Element Analysis Thermo-Mechanical Reliability Assessment of TSV Die Stacks by Finite Element Analysis Dr. Roland Irsigler, emens AG Corporate Technology, CT T P HTC Outline TSV SOLID µbump Stacking TSV application FEA

More information

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT YOUR Strategic TECHNOLOGY PARTNER Wafer Back-End OPTO PACKAGING PROCESS DEVELOPMENT CONCEPT FLIP CHIP PROTOTYping ENGINEERING TESTING SMT PRODUCTION CHIP ON BOARD SUPPLY CHAIN MANAGEMENT Next Level 0f

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

Assessing the Risk of Counterfeit Components. Colm Nolan, IBM Martin Huehne, Celestica

Assessing the Risk of Counterfeit Components. Colm Nolan, IBM Martin Huehne, Celestica Assessing the Risk of Counterfeit Components Colm Nolan, IBM Martin Huehne, Celestica Assessing the Risk of Counterfeit Components Agenda Introduction of Presenters Introduction Risk of Counterfeit Use

More information

Flip-Chip Process Improvements for Low Warpage

Flip-Chip Process Improvements for Low Warpage Flip-Chip Process Improvements for Low Warpage Robert L. Hubbard Lambda Technologies, Inc. Morrisville, NC, USA bhubbard@microcure.com Pierino Zappella*, Pukun Zhu Henkel Corporation Irvine, CA, USA Abstract

More information

Flip-Chip Process Improvements for Low Warpage

Flip-Chip Process Improvements for Low Warpage Flip-Chip Process Improvements for Low Warpage Robert L. Hubbard Lambda Technologies, Inc. Morrisville, NC, USA bhubbard@microcure.com Pierino Zappella*, Pukun Zhu Henkel Corporation Irvine, CA, USA Abstract

More information

SEMI MEMS Tech Seminar (Sept 26, Cornaredo, Italy)

SEMI MEMS Tech Seminar (Sept 26, Cornaredo, Italy) SEMI MEMS Tech Seminar (Sept 26, 2013 - Cornaredo, Italy) Opportunities of Wafer Level Embedded Technologies for MEMS Devices T. Braun ( 1 ), K.-F. Becker ( 1 ), R. Kahle ( 2 ), V. Bader ( 1 ), S. Voges

More information

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages by Seng Guan Chow, Yaojian Lin, Bernard Adams * and Seung Wook Yoon** STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

More information

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Yuci Shen *1, Leilei Zhang ** and Xuejun Fan * * Lamar University, Beaumont, Texas ** NVIDIA Corporation, Santa Clara, California

More information

Optimized Cu plating in fan-out wafer-level packaging MultiPlate: a turnkey solution

Optimized Cu plating in fan-out wafer-level packaging MultiPlate: a turnkey solution Optimized Cu plating in fan-out wafer-level packaging MultiPlate: a turnkey solution Cassandra Melvin Global Product Manager, Advanced Packaging Outline 1. Global megatrend IoT 2. Fan-out wafer-level packaging

More information

TSV CHIP STACKING MEETS PRODUCTIVITY

TSV CHIP STACKING MEETS PRODUCTIVITY TSV CHIP STACKING MEETS PRODUCTIVITY EUROPEAN 3D TSV SUMMIT 22-23.1.2013 GRENOBLE HANNES KOSTNER DIRECTOR R&D BESI AUSTRIA OVERVIEW Flip Chip Packaging Evolution The Simple World of C4 New Flip Chip Demands

More information

Plasma for Underfill Process in Flip Chip Packaging

Plasma for Underfill Process in Flip Chip Packaging Plasma for Underfill Process in Flip Chip Packaging Jack Zhao and James D. Getty Nordson MARCH 2470-A Bates Avenue Concord, California 94520-1294 USA Published by Nordson MARCH www.nordsonmarch.com 2015

More information

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong White Paper Quality and Reliability Challenges for Package on Package By Craig Hillman and Randy Kong Background Semiconductor technology advances have been fulfilling Moore s law for many decades. However,

More information

Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging

Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging Wei Sun, W.H. Zhu, Kriangsak Sae Le and H.B. Tan United Test

More information

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip SzePei Lim (Presenter), Jason Chou, Maria Durham, and Dr. Andy Mackie Indium Corporation 1 Outline of Presentation Roadmaps and challenges

More information

Thales vision & needs in advanced packaging for high end applications

Thales vision & needs in advanced packaging for high end applications Thales vision & needs in advanced packaging for high end applications M. Brizoux, A. Lecavelier Thales Global Services / Group Industry Chemnitzer Seminar June 23 th -24 th, 2015 Fraunhofer ENAS - Packaging

More information

Automotive Electronic Material Challenges. Anitha Sinkfield, Delphi

Automotive Electronic Material Challenges. Anitha Sinkfield, Delphi Automotive Electronic Material Challenges Anitha Sinkfield, Delphi Automotive Electronic Material Challenges Project Update About inemi Project Participants Problem Statement Project Details Summary and

More information

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages Bhavesh Varia 1, Xuejun Fan 1, 2, Qiang Han 2 1 Department of Mechanical Engineering Lamar

More information

Package Design Optimization and Materials Selection for Stack Die BGA Package

Package Design Optimization and Materials Selection for Stack Die BGA Package Package Design Optimization and Materials Selection for Stack Die BGA Package Rahul Kapoor, Lim Beng Kuan, Liu Hao United Test & Assembly Center Ltd (UTAC) 5 Serangoon North Ave 5, Singapore 554916 Email:

More information

GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE

GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE Bev Christian, Linda Galvis, Rick Shelley and Matthew Anthony BlackBerry Cambridge, Ontario, CANADA bchristian@blackberry.com ABSTRACT:

More information

FLIP CHIP CHIP ON BOARD SMT ENGINEERING OPTO PACKAGING SUPPLY CHAIN MANAGEMENT TESTING YOUR INNOVATIVE TECHNOLOGY PARTNER PRODUCTION CONCEPT

FLIP CHIP CHIP ON BOARD SMT ENGINEERING OPTO PACKAGING SUPPLY CHAIN MANAGEMENT TESTING YOUR INNOVATIVE TECHNOLOGY PARTNER PRODUCTION CONCEPT YOUR INNOVATIVE TECHNOLOGY PARTNER CHIP ON BOARD OPTO PACKAGING PROCESS DEVELOPMENT CONCEPT FLIP CHIP ENGINEERING TESTING PRODUCTION SMT SUPPLY CHAIN MANAGEMENT PROTOTYPES HIGH-PRECISION ASSEMBLY OF MICRO-

More information

Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)

Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs) Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs) M. Hertl Insidix, 24 rue du Drac, 38180 Grenoble/Seyssins,

More information

3D Wirebondless IGBT Module for High Power Applications Dr. Ziyang GAO Jun. 20, 2014

3D Wirebondless IGBT Module for High Power Applications Dr. Ziyang GAO Jun. 20, 2014 3D Wirebondless IGBT Module for High Power Applications Dr. Ziyang GAO Jun. 20, 2014 1 1 Outline Background Information Technology Development Trend Technical Challenges ASTRI s Solutions Concluding Remarks

More information

Integrated Copper Heat Slugs and EMI Shields in Panel Laminate (LFO) and Glass Fanout (GFO) Packages for High Power RF ICs

Integrated Copper Heat Slugs and EMI Shields in Panel Laminate (LFO) and Glass Fanout (GFO) Packages for High Power RF ICs Integrated Copper Heat Slugs and EMI Shields in Panel Laminate (LFO) and Glass Fanout (GFO) Packages for High Power RF ICs Venky Sundaram, Bartlet Deprospo, Nahid Gezgin, Atomu Watanabe, P. Markondeya

More information

DELO MONOPOX AD286 heat curing, construction adhesive

DELO MONOPOX AD286 heat curing, construction adhesive DELO MONOPOX AD286 heat curing, construction adhesive Base - epoxy resin, construction adhesive - one-component, heat-curing, filled, thixotropic Use - for the bonding of all metal types, temperature-resistant

More information

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website : 9 rue Alfred Kastler - BP 10748-44307 Nantes Cedex 3 - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr February 2012 - Version 1 Written by: Romain FRAUX DISCLAIMER

More information

Copper Wire Packaging Reliability for Automotive and High Voltage

Copper Wire Packaging Reliability for Automotive and High Voltage Copper Wire Packaging Reliability for Automotive and High Voltage Tu Anh Tran AMPG Package Technology Manager Aug.11.2015 TM External Use Agenda New Automotive Environments Wire Bond Interconnect Selection

More information

Behaviors of QFN Packages on a Leadframe Strip

Behaviors of QFN Packages on a Leadframe Strip Behaviors of QFN Packages on a Leadframe Strip Eric Ouyang, Billy Ahn, Seng Guan Chow, Anonuevo Dexter, SeonMo Gu, YongHyuk Jeong, JaeMyong Kim STATS ChipPAC Inc 46429 Landing Parkway, Fremont, CA 94538,

More information

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages Michael Hertl 1, Diane Weidmann 1, and Alex Ngai 2 1 Insidix, 24 rue du Drac, F-38180 Grenoble/Seyssins,

More information

Nondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab

Nondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab Nondestructive Internal Inspection The World s Leading Acoustic Micro Imaging Lab Unmatched Capabilities and Extensive Expertise At Your Service SonoLab, a division of Sonoscan, is the world s largest

More information

Variable Frequency Microwave For Chip-On-Board Glob Top Curing

Variable Frequency Microwave For Chip-On-Board Glob Top Curing Variable Frequency Microwave For Chip-On-Board Glob Top Curing Binghua Pan (Phone: 65-458629 Fax: 65-4565422 e-mail: binghua.pan@delphiauto.com) Chih Kai Nah (Phone: 65-458629 Fax: 65-4565422 e-mail: chih.kai.nah@delphiauto.com)

More information

World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:3, No:11, 2009

World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:3, No:11, 2009 International Science Index, Electronics and Communication Engineering waset.org/publication/5181 Effect of Curing Profile to Eliminate the Voids / Black Dots Formation in Underfill Epoxy for Hi-CTE Flip

More information

Introduction of CSC Pastes

Introduction of CSC Pastes Introduction of CSC Pastes Smart Phones & Conductive Pastes Chip Varistors Chip Inductors LC Filters Flexible Printed Circuit Boards Electronic Molding Compounds ITO Electrodes PCB Through Holes Semiconductor

More information

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes Jason Chou and Sze Pei Lim Indium Corporation Agenda Company introduction Semiconductor assembly roadmap challenges Fine

More information

Underfill Selection for Large Body (50x50mm) Lidded Flip Chip BGA Package with ELK 40nm Pb-free Bumps

Underfill Selection for Large Body (50x50mm) Lidded Flip Chip BGA Package with ELK 40nm Pb-free Bumps Underfill Selection for Large Body (50x50mm) Lidded Flip Chip BGA Package with ELK 40nm Pb-free Bumps by Peng SUN, Vivian ZHANG, Rocky XU, Tonglong ZHANG STATS ChipPAC (Shanghai) Co., Ltd. 188, Huaxu Road,

More information

TSV Interposer Process Flow with IME 300mm Facilities

TSV Interposer Process Flow with IME 300mm Facilities TSV Interposer Process Flow with IME 300mm Facilities Property of Institute of Microelectronics (IME)-Singapore August 17, 2012 Outline 1. TSV interposer (TSI) cross sectional schematic TSI with BEOL,

More information

Lead-Free HASL: Balancing Benefits and Risks for IBM Server and Storage Hardware

Lead-Free HASL: Balancing Benefits and Risks for IBM Server and Storage Hardware Lead-Free HASL: Balancing Benefits and Risks for IBM Server and Storage Hardware November 19, 2009 M.Kelly, P.Eng, MBA Senior Engineer, ECAT Interconnect Technology Lead-Free Server Development Core Team

More information

NanoSystemsEngineering: NanoNose Final Status, March 2011

NanoSystemsEngineering: NanoNose Final Status, March 2011 1 NanoSystemsEngineering: NanoNose Final Status, March 2011 The Nanonose project is based on four research projects (VCSELs, 3D nanolithography, coatings and system integration). Below, the major achievements

More information

Highly Reliable Flip-Chip-on-Flex Package Using Multilayered Anisotropic Conductive Film

Highly Reliable Flip-Chip-on-Flex Package Using Multilayered Anisotropic Conductive Film Journal of ELECTRONIC MATERIALS, Vol. 33, No. 1, 2004 Regular Issue Paper Highly Reliable Flip-Chip-on-Flex Package Using Multilayered Anisotropic Conductive Film MYUNG JIN YIM, 1,3 JIN-SANG HWANG, 1 JIN

More information

Warpage Mechanism of Thin Embedded LSI Packages

Warpage Mechanism of Thin Embedded LSI Packages Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (1/10) [Technical Paper] Warpage Mechanism of Thin Embedded LSI Packages Yoshiki Nakashima*, Katsumi Kikuchi*, Kentaro Mori*, Daisuke Ohshima**,

More information

LAMINATED STRUCTURAL TUBING

LAMINATED STRUCTURAL TUBING Quality fiberglass epoxy backup support components, such as structural tubes, are REK 4-TC REK 300-C REK 200-C REK 250-C REK 250-90 REK 1750-90 an important part of building checking fixtures, vacuum forming

More information

Hitachi Anisotropic Conductive Film ANISOLM AC-8955YW. Issued 2007/03/30

Hitachi Anisotropic Conductive Film ANISOLM AC-8955YW. Issued 2007/03/30 Hitachi Chemical Data Sheet Hitachi Anisotropic Conductive Film ANISOLM AC-8955YW Issued 27/3/3 1. Standard specification, bonding condition, storage condition and characteristic...1 2. Precautions in

More information

SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation

SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation Kevin Yang, Habib Hichri, Ralph Zoberbier SÜSS MicroTec Photonic Systems Inc. June 18, 2015 MARKET DRIVER Mobile

More information

BASE MATERIALS Through Assembly

BASE MATERIALS Through Assembly Thermal Analysis of BASE MATERIALS Through Assembly Can current analytical techniques predict and characterize differences in laminate performance prior to exposure to thermal excursions during assembly?

More information