5 th Quarterly Report EPRI Agreement W July 1- September 30, 1999

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1 5 th Quarterly Report EPRI Agreement W July 1- September 30, 1999 PI: S.J. Pearton, University of Florida (Co-investigators F. Ren, C.R. Abernathy, R.K. Singh, P.H. Holloway, T.J. Anderson, A. Sher, M. Berding S. Krishnamurthy, D. Palmer and G.E. McGuire). Prepared for: Jerry Melcher In this fifth reporting period we produced GaN Schottky rectifiers with V RB >2kV, a world record for this materials system. We also investigated the relative contributions of bulk and surface leakage to the reverse current in diodes and compared our results to state-of-the-art SiC rectifiers. Additional work focussed on process development, including dry etch damage in p-gan and in diodes (and methods of removing this damage), dry etching of SiC, regrowth of GaAs(C) on GaN (Mg) to improve p-contact resistance, the diffusion of O in GaN and growth of GdO x and GaO x as potential gate dielectrics on GaN for MOS-controlled thyristors. The power device maskset was completed and we are currently measuring the effect of different edge termination techniques. Finally, some initial packaging of GaN devices was performed. (a) Schottky Rectifiers Two different types of GaN were grown on c-plane sapphire substrates by Metal Organic Chemical Vapor Deposition using trimethylgallium and ammonia as the precursors. For structures intended for vertical depletion, a 1µm thick n + (3x10 18 cm -3, Si doped) contact layer was grown in a low temperature GaN buffer and then followed with either 4 or 11µm of undoped (n~2x10 16 cm -3 ) GaN. For structures intended for lateral depletion, a 3µm thick resistive (n<10 15 cm -3 ) active region was grown on a low temperature buffer. The mesas were formed by Cl 2 /Ar Inductively Coupled Plasma etching (300W source power, 40W rf chuck power, corresponding to a dc self-bias of 85V) at a rate of 1100Å min -1, using a photoresist mask. The samples were annealed at ~800 o C to remove dry etch damage. Ohmic contacts were formed by lift-off of e-beam evaporated Ti/Al, subsequently annealed at 750 o C for 20 secs under N 2. The rectifying contacts with diameter µm were formed by lift-off of e-beam evaporated Pt/Au. On the lateral diodes, n + contact regions were formed by implantation of Si + followed by annealing at 1150 o C for 10 secs under N 2. The GaN was protected by a dielectric encapsulant during the annealing step. The ohmic and rectifying contacts were formed as described above. Schematics of the two different structures are shown in Figure 1. The current-voltage (I-V) characteristics were recorded on a HP 4145A parameter analyzer. A typical I-V characteristic for the 11µm undoped depletion layer diodes is shown in Figure 2. The V RB for these devices was 550V at 25 o C, with typical V F s of 3-5V (100Å cm -2 ). The specific on-resistance was in the range 6-10 mω cm 2, leading to a figure-of-merit (V RB ) 2 /R ON of 48 MW cm -2. The breakdown voltage is approximately a factor of 3 lower than the theoretical maximum value for this doping and thickness. Secondary Ion Mass Spectrometry showed that the main background impurities present were O (~9x10 17 cm -3 ), C (~10 17 cm -3 ), Si (4x10 17 cm -3 ) and H (3x10 18 cm -3 ). While O and Si can produce shallow donor states, it is clear 1

2 that these impurities have only fractional electrical activation. The surfaces of the material were relatively smooth with root-mean-square roughness of ~0.2nm (1x1µm 2 ) and 1.5nm (10x10m 2 ). Cross-sectional transmission electron microscopy (TEM) views of the structure are shown in Figure 3. The threading dislocation density at the top surface was ~ cm -2, typical of high quality, heteroepitaxial GaN. For the 4µm thick active region structure, the room temperature V RB was 356V, with typical V F s of 3-5V (100Å cm -2 ). The specific on-resistance of these devices was 28 mω cm 2, leading to a value of (V RB ) 2 /R ON of 42 MW cm -2. Once again the breakdown voltage was approximately a factor of 3 lower than the theoretical maximum value. In these diodes we observed a negative temperature coefficient for V RB, with a value of 0.92 V K -1 in the range o C and 0.17 VK -1 in the range o C. If impact ionization were the cause of breakdown, one would expect to observe a positive temperature coefficient for V RB, as has been reported for GaN heterostructure field effect transistors and p + pn + diodes. In analogy with some reports from some SiC Schottky diodes with negative V RB temperature coefficients, we believe the breakdown mechanism in our diodes is defect-assisted tunnelling through surface or bulk states. Figure 4 shows the reverse current density in the 4µm active layer diodes at a low bias (15V) and a bias approximately half of V RB (i.e. 150V). For the low bias condition the current density scales as the perimeter/area ratio, while at the high bias condition the current density is constant with this ratio. This data indicates that at low biases the surface perimeter currents are the dominant contribution, while at higher biases the current is proportional to contact area indicating that bulk leakage is dominant. In SiC devices it has been reported that increases in leakage current in the voltage range approximately half the V RB of the diodes are due to the presence of this interfacial layer (typically as oxide) between the rectifying contact and the semiconductor. This oxide can sustain a voltage drop, but is thin enough for carrier tunnelling. (6) Figure 5 shows reverse recovery current transient waveforms from a diode switched from a forward current density of 500A cm -2 to a reverse voltage of 100V. The recovery time is <0.2µsec, similar to values reported for SiC rectifiers. In all wide bandgap diode rectifiers (both SiC and the GaN reported here), the magnitude of the reverse leakage currents are generally 1-2 orders higher than the theoretical values based on image-force lowering of the Schottky barrier. Our GaN diodes have slightly higher reverse leakage relative to SiC devices at the same biases, which probably reflects the earlier stage of maturity of the former. Figure 6 shows a room temperature I-V characteristic from the 3µm thick structure. The V RB was >2000V (the limit of our test setup), with a best V F of 15V (more typically 50-60V). The specific on-resistance was 0.8Ωcm 2 producing a (V RB ) 2 /R ON value of >15 MW cm -2. For this structure we believe the depletion is lateral, because for the larger thickness and doping a vertical device would breakdown at ~1000V. TEM cross-sections of the structure showed a threading dislocation density of ~3x10 8 cm -2, typical of high quality GaN of this thickness. To place the results in context, Figure 7 shows a plot of specific on-resistance for Schottky diode rectifiers as a function of breakdown voltage. The lines are theoretical values for Si, 4H-SiC, 6H-SiC and GaN and the points are experimental values for SiC and GaN devices. Note that the 356V and 2kV diodes reported here essentially fit on the line expected for perfect Si devices, but the 550V diode has clearly superior performance to Si. However there is still significant improvement required before GaN matches the reported performance of SiC Schottky rectifiers. 2

3 The main conclusions of our study can be summarized as follows: (i) (ii) (iii) (iv) (v) Mesa diodes with V RB equal to planar diodes, but with improved R ON values, have been fabricated in GaN using Cl 2 /Ar dry etching, followed by annealing to remove the plasma damage. V RB values up to 550V with figure-of-merit 48 MW cm -2 have been achieved on mesa diodes fabricated on thick (12µm total) MOCVD GaN. V RB values >2 kv have been achieved in lateral diodes fabricated on resistive GaN grown by MOVCD. For the mesa diodes, the V RB values are approximately a factor of three lower than the theoretical maximum for GaN based on avalanche breakdown. Similarly, the reverse leakage currents are several orders of magnitude higher than the theoretical values. At low reverse biases, the leakage current is dominated by contributions from the surface, while at higher biases bulk leakage dominates. Pt/Au Ti/Al 11 µm GaN Ti/Al 1 µm n + -GaN Al 2 O 3 substrate Ni/Au Pt/Au Ni/Au 3 µm undoped (n cm -3 ) GaN 0.3 µm undoped GaN buffer Al 2 O 3 substrate Figure 1. Schematic of mesa and planar GaN dio 3

4 Figure 2. I-V characteristic at 25 o C from mesa diode with 11µm thick blocking layer. 4

5 Current (A) Voltage (V) Figure 3. TEM cross-sections of the MOCVD-grown structure with 11µm thick blocking layer GaN Schottky Diodes 10-4 J R (A cm -2 ) V R = 150V V R = 15V Perimeter/Area Ratio (cm -1 ) Figure 4. Reverse current density in GaN mesa diodes (4µm thick blocking layer) as a function of perimeter-to-area ratio, at two different reverse biases. 5

6 Current Density (A/cm 2 ) Time (µs) Figure 5. Reverse recovery current transient waveform measured for GaN rectifier (550µm diameter) at 25 o C. The device was switched from a forward current density of 500A cm -2 to a reverse voltage of 100V Currnet (A) Voltage (V) Figure 6. I-V characteristic at 25 o C from planar diode with 3µm thick blocking layer. 6

7 10 0 GaN-UF Diode Rectifiers Specific Resistance (ohm-cm 2 ) H-SiC 4H-SiC GaN-UF SiC-ABB GaN-Caltech SiC-Purdue GaN-UF Si SiC-NCSU SiC-RPI GaN Breakdown Voltage (V) Figure 7. Specific on-resistance versus blocking voltage for SiC and GaN Schottky diode rectifiers. The performance limits of Si, SiC and GaN devices are shown by the solid lines. 7

8 (b) High Power Device Mask-set Schematics of the mask design for edge termination of diode rectifiers are shown in Figures We will be comparing the effectiveness of guard rings, metal overlays, field rings and junction-barrier control for optimized high field performance of our GaN devices. Figure 8. View of High Breakdown Rectifier Design 8

9 Schottky Contact Schottky Contact Ohmic contact SiO 2 GaN layer p-implant n + -implant Figure 9. View of Rectifier Fingers 9

10 KT m + s J ln( 2 q 2d AT ( x ( m t)( m + s) s 2d) m + s 2d FC i V FS = φ B + ) + ρ ln( ) + + J FC Where: V FS is the forward voltage drop of the JBS rectifier J L = 2d ( ) AT m + s 2 qφ B q exp[ ( )]exp( kt kt qe 4πε S Where: J L is the reverse leakage current of the JBS rectifiers SiO 2 Schottky Contact Ohmic contact p- GaN layer n + - Figure 10. View of Junction Barrier Controlled Schottky (JBS) Rectifiers 10

11 Extend the depletion boundary along the surface of dielectric layer and reduce the electric field crowing at the edge V ffr = 2qN A 2 WS S V qn a + ε 2ε A S W S SiO 2 Schottky Contact Ohmic contact Where: V ffr is the potential of the floating field ring N A is the doping concentration ε S is permittivity W S is the floating field ring spacing Va is the applied Schottky bias p- GaN layer n + - Figure 11. View of Rectifiers with Floating Field Ring Termination 11

12 SiO 2 Schottky Metal Ohmic contact Proper Design of the edge termination is critical for both obtaining a high breakdown voltage and reducing the onstate voltage drop and the switching times P + Guard Ring: Place a P-type diffused guard ring at the edge of the Schottky barrier metal Metal Overlap: Extend the Schottky barrier metal over an oxide layer at the edge p- GaN layer n- Figure 12. View of Rectifiers with Edge Termination 12

13 (c) Cl 2 /Ar Plasma Damage in GaN Schottky Diodes Diodes were fabricated on nominally undoped (n cm -3 ) GaN layers 3µm thick grown on an n + (10 18 cm -3 ) GaN buffer on a c-plane Al 2 O 3 substrate. Ohmic contacts were formed with lift-off Ti/Au subsequently annealed at 600 C, followed by evaporation of the 250 µm diameter Pt(250Å)/Au(1500Å) Schottky contacts through a stencil mask. The samples were briefly exposed ( 10secs controlled by the system software) to 10Cl 2 /5Ar (total gas load 15 standard cubic centimeters per minute) ICP discharges in a Plasma Therm 790 reactor. During the ignition stage of the discharge, the dc self-bias takes 2 secs to reach its final value. From limited measurements we found that damage saturates in this time frame. The gases were injected directly into the source through electronic mass flow controllers, and the 2MHz source power was varied from W. The samples were placed on an rfpowered (13.56MHz, 5-300W), He backside-cooled chuck. Process pressure was hold constant at 2 m Torr. The current-voltage (I-V) characteristics of the diodes were recorded on a HP 4145A parameter analyzer. Barrier heights(φ B ) and ideality factors (n) accurate to ±5% were obtained from the forward I-V characteristic according to the relationship: 2 eφ B ev J = A **T exp( )[exp( -1)] kt nkt Where J is the current density, A** the effective Richardson constant, T the measurement temperature (25 C), e the electronic charge and k is Boltzmann s constant. The reverse breakdown voltage (V B ) was defined as the voltage at which the current density was ma/cm 2 (i.e. a current of 15mA). Some diodes were annealed at temperatures up to 800 C for 30secs under N 2 after plasma exposure, while others were treated in UV-ozone at 25 C for period up to 20 minutes in a Jelight 200S system, followed by rinsing in HCl solutions. Auger Electron Spectroscopy (AES) was performed in some cases on blanket (unmetallized) samples. Figure 13 shows some typical I-V characteristics from GaN diodes after exposure to the ICP Cl 2 /Ar discharges at fixed ICP source power and varying rf power. The latter parameter controls the average energy of ions (predominantly Ar + and Cl + 2 in this case) incident on the samples. There is a clear degradation in V B as this rf chuck power is increased. Control diodes not exposed to the plasma had I-V characteristics that were similar to curves 1 and 2, with V B of 38V and φ B of 0.82eV. The dependence of V B and φ B on rf chuck power is shown in the upper part of Figure 14. Both of these parameters, at least initially, decrease with increasing power. The φ B values saturate beyond 50W. The main effect on φ B is from damage created around the contact periphery. This would expected to saturate once a N 2 -deficient region is created because much of the resultant φ B is still determined by the unexposed region under the contact metal. Under these conditions, the dc chuck self-bias increases from 105 V at 50 W to 275 V at 200 W. The average ion energy is roughly the sum of this voltage plus the plasma potential which is V in this system under these conditions. After plasma exposure, the diode ideality factor was always 2, which is a further indication of the degradation in electrical properties of the structures. The results are consistent with creation of an ion damaged, non-stoichiometric GaN surface region. This region exists in the plasma-exposed area outside the metal contacts. Note that the GaN etch rate increases monotonically with rf chuck power (lower part of the Figure 14), 13

14 but this more rapid removal of material is not enough to offset the greater amount of damage caused by the higher-energy ion bombardment. We believe the GaN must be non-stoichiometric and hence more n-type at the surface because of the sharp decreases observed in V B. In the case of semiconductors such as GaAs where ion bombardment creates more resistive material by introduction of deep compensating levels rather than shallow donor states, the breakdown voltage is generally found to increase with exposure to plasmas. The dependence of V B and φ B on ICP source power is shown in Figure 15 (top). While φ B continues to decrease as the ion flux increases, V B initially degrades but shows less of a decrease at higher source powers (Figure 15, bottom). This is most likely a result of the continued decrease in the self-bias at higher source power. This also leads to a decrease in GaN etch rate above 500 W. The results of Figure 14 and 15 show that both ion energy and ion flux are important in determining not only the GaN etch rate, but also the amount of residual damage in the diodes. As mentioned previously, past measurements on ICP damaged GaN surfaces have established the damage depth as being of order 500 Å. One method for trying to remove the damaged material between the contacts is by oxidizing it by UV/ozone (O 3 ) exposure, followed by stripping of the oxide. Figure 16 shows the dependence of V B and φ B on UV ozone treatment time. In each case after the oxidation, a 1:20, HCl: H 2 O solution was used for removal of the oxidized material. While there is some improvement in both parameters up to 5 min, there is no further improvement for longer times. We assume the oxidation distance is diffusion-controlled (i.e. dependent on t ), and from preliminary measurements we believe that only 30 Å of GaN is oxidized and removed for 5 minute UV ozone exposure. Therefore the process would have to be repeated approximately times to remove the damaged region of the GaN, assuming the oxidation rate remains the same deeper into the material. Use of a stronger HCl solution improves the V B value compared to use of the 1:20 solution (Figure 17), but there is no improvement in φ B. We emphasize that the damaged GaN is the exposed region outside the contact area. This will lead to reductions in V B by increasing the surface conductivity and degrade φ B by increasing leakage current at the contact periphery. Figure 18 shows the effect of anneal temperature on the recovery of V B and φ B. There is a clear improvement in V B for anneals in the range C, and little change thereafter and it remains lower than the unetched control value. However, φ B changes very little with annealing. These results are somewhat different than in the case where the surface is exposed to the ICP discharge, annealed and then the Schottky contact is deposited. For that sequence, essentially full recovery of the electrical characteristics was obtained for 750 C annealing. In the present case where the contact is in place we believe the metal begins to react with the GaN at 600 C, accounting for the lack of recovery of φ B at higher temperatures. The effect of annealing time at fixed temperature (700 C) on V B and φ B is shown in Figure 19. The improvement in both parameters is saturated beyond 60 secs. It would be expected that the recovery mechanism should be most critically dependent on temperature since most defect annealing processes involve dissociation and diffusion of defects and their complexes. In this case, the recovery would be dependent on the square root of annealing time and exponentially on temperature. To establish the chemical state of the GaN surface at different stages, AES was performed on an unmetallized sample. Figure 20 shows surface scans before (top) and after (lower) exposure to a 500 W source power, 50 W chuck power Cl 2 /Ar discharge. The main 14

15 change is a reduction in the N 2 signal in the latter sample (by 20%), confirming the preferential loss of this element during dry etching. Subsequent annealing at 700 C in N 2 restored some of this deficiency (Figure 20, bottom). The main points of our study may be summarized as follows: 1. ICP Cl 2 /Ar discharges degrade the performance of GaN Schottky diodes, with ion energy and ion flux both playing important roles. 2. The degradation mechanism appears to be creation of a conducting, non-stoichiometric (N 2 - deficient) near-surface region on the GaN. 3. UV ozone oxidation of the surface and subsequent dissolution of the oxidized region in HCl provides some restoration of the electrical properties of the GaN. 4. Annealing at C also restores some of the initial reverse breakdown voltage characteristics, but little change in φ B for Pt/Au contacts on GaN. Current (A) : 50W rf, 300W ICP 2: 100W rf, 300W ICP 3: 150W rf, 300W ICP 4: 200W rf, 300W ICP Voltage (V) Figure 13. I-V characteristics from GaN diodes after Cl 2 /Ar plasma exposure (300W source power, 2m Torr) with different rf chuck powers V B (V) dc self-bias (V) control V B V B φ B etch rate dc bias 300W ICP Cl 2 /Ar control φ B φ B (ev) GaN etch rate (A / min) Figure 14. Rf chuck power dependence of V B and φ B in Cl 2 /Ar plasma exposed GaN diodes (top) and of dc chuck selfbias and GaN etch rate under the same conditions (bottom) rf Power (W) 15

16 control V B 35 V B 0.9 control φ B φ B V B (V) dc self-bias (V) ICP Cl / Ar W rf etch rate dc bias φ B (ev) GaN etch rate (A/min) Figure 15. ICP power dependence of V B and φ B in Cl 2 /Ar plasma exposed GaN diodes (top) and of dc chuck self-bias and GaN etch rate under the same conditions (bottom) ICP Power (W) 40 control value (unetched) 30 O 3 +HCl (1 min) V B (V) control value (unetched) Figure 16. UV ozone oxidation time dependence of V B (top) and φ B (bottom) in Cl 2 /Ar plasma exposed GaN diodes. After oxidation, the samples were rinsed in 1HCl: 20H 2 O for 1 min. φ B (ev) O 3 Time (min.) 16

17 0.9 control value (unetched) 0.8 φ B (ev) V B (V) control value (unetched) 1: as etched 2: O3 (5min) 3: O3 (5min) +HCl (1:20, 1 min) Figure 17. Dependence of V B (top) and φ B (bottom) on process condition in Cl 2 /Ar plasma exposed GaN diodes. After UV ozone oxidation, the samples were rinsed in 1HCl: 20H 2 O for 1 min or aqueous HCl (35-38%) for seconds. 20 4: O 3 (5min.)+HCl(1:20, 1min.) +HCl(35-38%, 30sec.) 5: O 3 descum(5min.)+hcl(1:20, 1min.) +HCl(35-38%,60sec.) Sample No. 40 control value (unetched) V B (V) sec anneal as etched Control value (unetched) Figure 18. Annealing temperature dependence of V B (top) and φ B (bottom) in Cl 2 /Ar plasma exposed GaN diodes. Anneal time was 30 sec at each temperature. φ B (ev) ) as etched Anneal Temperature (C) 17

18 40 Control value (unetched) V B ( V ) C anneal as etched Control value (unetched) Figure 19. Annealing time dependence (at 700 C) of V B (top) and φ B (bottom) in Cl 2 /Ar plasma exposed GaN diodes. φ B ( ev ) as etched Anneal Time (min) E Figure 20. AES surface scans from GaN (top) or after (center) Cl 2 /Ar plasma exposure, and subsequent annealing at 700 C for 60 seconds (bottom). Kinetic Energy (ev) 18

19 (d) Growth of Oxide Gate Dielectrics A number of GaN field effect transistors (FETs) and AlGaN/GaN heterostructure FETs have been reported showing excellent device breakdown characteristics. To date however all show evidence of performance degradation due to the presence of high parasitic resistances which arise from the unique processing limitations imposed by the physical characteristics of GaN. These problems can be overcome by using a metal oxide semiconductor FET (MOSFET) approach of the type recently reported for GaAs and InGaAs. In the Ga 2 O 3 (Gd 2 O 3 )/GaAs MOSFET, a mid-gap surface state density of 2 x cm -2 ev -1 was obtained. As a result, both n- and p-type enhancement mode MOSFETs could be demonstrated. This method has recently been applied to GaN as well, resulting in demonstration of the first GaN MOSFET. While preliminary device results are encouraging, little is yet known about the optimum oxide composition, structure and deposition method. A number of investigators have explored oxidation of III-V surfaces in general and more recently of GaN. Invariably this leads to the formation of a poly-crystalline Ga 2 O 3 layer which typically exhibits poor surface or interface smoothness and poor capacitor performance. A more successful approach, and the one responsible for the MOSFETs referenced above, has been deposition of the oxide films using e- beam evaporation from a single crystal of gadolinium gallium garnet (GGG) in an MBE chamber. This has been reported to yield amorphous Ga 2 O 3 films with trace amounts of Gd which are not uniform in the growth direction. Deposition of the oxide from individual sources of Ga and oxygen would of course eliminate this contamination. Promising results were obtained by Callegari et. al. using an RF oxygen plasma to produce GaO x films, though possible damage to the semiconductor surface induced by the high energy plasma remains a potential limitation to this approach. In this section the feasibility of using individual sources of metal and oxygen to deposit both Ga 2 O 3 and Gd 2 O 3 films has been investigated using a low energy electron cyclotron resonance (ECR) plasma source to minimize potential surface damage. Samples were grown in a Riber MBE 2300 on n-gan (0.5 µm)/sapphire samples prepared by MOCVD or on n-si substrates. Substrate temperature was monitored using the substrate thermocouple. Si substrates were cleaned ex-situ by dipping in buffered oxide etch (BOE) for 30 seconds. The n-gan was cleaned ex-situ by etching in HCl for 3 min. and then exposing the sample to UV/O 3 for 25 min. Prior to deposition of the oxide layer, the GaN is heated to 650 C under ECR nitrogen plasma and then cooled to the oxide deposition temperature. Solid Ga was heated in a standard effusion oven to temperatures of 883 C to 1100 C while solid Gd was heated to 1200 C. All of the oxide layers were grown under an oxygen plasma obtained from a Wavemat MPDR 610 electron cyclotron resonance (ECR) plasma source operating at 200W forward power. Films were characterized using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (XTEM), atomic force microscopy (AFM), Auger electron spectroscopy (AES) and electrically via capacitance voltage and I-V analysis. Capacitors for electrical characterization were fabricated by Pt/Au (300Å/1500Å) top contact metallization and In solder for backside ohmic contact. Using the ECR-MBE system, diodes fabricated from oxides deposited from elemental Ga and the oxygen plasma were fabricated on both Si and GaN. As expected, AES indicates that the Oxygen/Gallium ratio in the oxide layers is a sensitive function of a) Ga cell temperature, b) oxygen flux and c) deposition temperature, as shown in Figure 21. The deposition rate decreases as the cell temperature, and hence Ga flux, is reduced. For a given oxygen flux, this reduction results in an increase in the amount of oxygen in the film. Surprisingly, decreasing the substrate 19

20 temperature dramatically increases the Ga uptake rate for a given flux, and hence decreases the oxygen concentration in the film. In most cases, the amount of oxygen in the films is higher than that reported for e-beam derived films, 1.5 and higher than that observed from Ga 2 O 3 powder. This suggests that the oxygen flux reaching the surface is more than sufficient to deposit stoichiometric material. While the deposition rates can be varied over a wide range, µm/hr, the lower deposition rates give the highest oxygen concentrations and smoothest films as determined by stylus profilometry and SEM. Similarly, lower deposition temperatures tend to produce the best surface morphologies when the deposition rate is corrected for the enhanced Ga uptake, as shown in Figure 22. In fact the smoothest films have been obtained at the lowest temperature tested, 300 C. Even at 300 C however, the films appear quite rough in both the SEM and AFM, Figure 23, with an RMS roughness of 21.6nm on Si and 32.1nm on GaN. Diodes fabricated on p-gan using GaO x deposited at 400 C show significant leakage when analyzed by CV and low breakdown voltage. The low breakdown has been traced to voids in the dielectric which arise from islanding during deposition. When metallized, the metal penetrates through the voids to the semiconductor. Annealing of these structures in hydrogen improved the C-V characteristics significantly. This suggests that much of the leakage is due to defects within the dielectric. While powder X-ray diffraction shows no evidence of crystalline diffraction peaks, there may be small regions of crystallinity. The leakage might then be due to dangling bonds at the surfaces of these small regions. By contrast to the GaO x, GdO x layers deposited from elemental Gd and the ECR oxygen plasma exhibit excellent surface morphology, as shown in Figure 24. The surface roughness as measured by AFM is only nm and is not apparent at an SEM magnification of 10,000x. Also unlike GaO x, the deposition rate did not appear to be a function of substrate temperature, with a rate of 0.1Å/sec for a Gd cell temperature of 1200 C. Similarly, the O/Gd ratio did not appear to change significantly with substrate temperature and like the GaO x gave an oxygen level higher than that observed for Gd 2 O 3 powder. XTEM analysis of the layers shows the material to be poly-crystalline with a columnar grain structure, as in Figure 25. Diodes were fabricated on n-gan using GdO x deposited at 300 C. These diodes show significant leakage when analyzed by CV and low breakdown voltage. Diodes were also fabricated on n-si using GdO x deposited at 300 C and 500 C. The 300 C deposited GdO x on n- Si showed similar results to those on n-gan. The structure deposited at 500 C, however, shows a breakdown field of 0.55MV/cm (measured at 0.5mA/cm 2 ) and a flatband voltage shift of V when measured at 1kHz. Steps have been taken to study the deposition and properties of GaO x and GdO x from elemental Gallium and Gadolinium and an ECR Oxygen plasma. The GdO x exhibits excellent surface morphologies and maintains stoichiometry over a range of deposition temperatures. The GaO x, however, shows poor surface morphologies and a range of compositions dependent on deposition temperature and source fluxes. Diodes fabricated on n-si using GdO x deposited at 500 C show a breakdown field of 0.55MV/cm and a flatband voltage shift of -0.38V. 20

21 2.0 Deposition Rate (Å/min) C O/Ga Ratio 400 C O/Ga Ratio 540 C Deposition Rate 400 C Deposition Rate 7.2x x x x x x10-4 Reciprocal Ga Cell Temperature (K -1 ) O/Ga Ratio (Arbitrary Units) Figure 21. GaO x deposition rate and O/Ga ratio as a function of Ga cell temperature for two different p-si substrate temperatures. Dashed line represents O/Ga ratio determined from powder sample of Ga 2 O 3. De pos itio n Rat e (A/ mi n) 100 T Ga = 1090C: Dep Rate T Ga = 1082C: Dep Rate T Ga = 883C: Dep Rate Roughness Roughness Roughness Ro ugh nes s x x x10-3 1/T sub (K -1 ) Figure 22. Effect of substrate temperature on GaO x deposition rate and surface roughness for various Ga cell temperatures. Layers were deposited on n-si substrates. 21

22 Figure 23. Surface morphology of GaO x deposited on p-gan at 300 C as measured by AFM (at left) and SEM (at right). SEM scale marker represents 5 microns. a b c d Figure 24. Surface morphology as measured by AFM (a,b,c) and SEM (d) of GdO x films deposited at a) 300 C on Si, b and d) 500 C on Si and c) 300 C on GaN. The RMS roughness values were a) 0.6 nm, b) 0.5 nm and c) 0.8nm. Layer thickness is ~31.0 nm. 22

23 Figure 25. XTEM image of GdO x layer deposited on n-si at 300 C (top) and 500 C (bottom). (e) Plasma Damage in p-gan The layer structure consisted of 1µm of undoped GaN (n~5x10 16 cm -3 ) grown on a c- plane Al 2 O 3 substrate, followed by 0.3 µm of Mg doped (p~10 17 cm -3 ) GaN. The samples were grown by rf plasma-assisted Molecular Beam Epitaxy. Ohmic contacts were formed with Ni/Au deposited by e-beam evaporation, followed by lift-off and annealing at 750 o C. The GaN surface was then exposed for 1 min to ICP H 2 or Ar plasmas in a Plasma-Therm 790 System. The 2MHz ICP source power was varied from W, while the MHz rf chuck power was varied from W. The former parameter controls ion flux incident on the sample, while the latter controls the average ion energy. Prior to deposition of 250µm diameter Ti/Pt/Au contacts through a stencil mask, the plasma exposed surfaces were either annealed under N 2 in a rapid thermal annealing system, or immersed in boiling NaOH solutions to remove part of the surface. As reported previously it is possible to etch damaged GaN in a self-limiting fashion in hot alkali or acid solutions. The current-voltage (I-V) characteristics of the diodes were recorded on an HP 4145A parameter analyzer. A schematic of the final test structures is shown in Figure 26. The unetched control diodes have reverse breakdown voltages of ~2.5-4 V depending on the wafer these values were uniform (±12%) across a particular wafer. Figure 27 shows the I-V characteristics from samples exposed to either H 2 (top) or Ar (bottom) ICP discharges (150 W rf chuck, 2 mtorr) as a function of source power. In both cases there is an increase in both the reverse breakdown voltage and the forward turn-on voltage, with these parameters increasing monotonically with the source power during plasma exposure. 23

24 Figure 28 shows this increase in breakdown voltage as a function of source power, and also the variation of the chuck dc self-bias. As the source power increases, the ion density also increases and the higher plasma conductivity suppresses the developed dc bias. Note that the breakdown voltage of the diodes continues to increase even as this bias (and hence ion energy, which is the sum of this bias and the plasma potential) decreases. These results show that ion flux plays an important role in the change of diode electrical properties. The other key result is that Ar leads to consistently more of an increase in breakdown voltage, indicating that ion mass is important rather than any chemical effect related to removal of N 2 or NH 3 in the H 2 discharges. The increase in breakdown voltage on the p-gan is due to a decrease in hole concentration in the near-surface region through the creation of shallow donor states. The key question is whether there is actually conversion to an n-type surface under any of the plasma conditions. Figure 29 shows the forward turn-on characteristics of the p-gan diodes exposed to different source power Ar discharge at low source power (300 W), the turn-on remains close to that of the unexposed control sample However there is a clear increase in the turn-on voltage at higher source powers, and in fact at 750 W the characteristics are those of an n-p junction. Under these conditions the concentration of plasma-induced shallow donors exceeds the hole concentration and there is surface conversion. In other words the metal-p GaN diode has become a metal-n GaN-p GaN junction. We always find that plasma exposed GaN surfaces are N 2 - deficient relative to their unexposed state, and therefore the obvious conclusion is nitrogen vacancies create shallow donor levels. This is consistent with thermal annealing experiments in which N 2 loss from the surface produced increased n-type conduction. The influence of rf chuck power on the diode I-V characteristics is shown in Figure 30 for both H 2 and Ar discharges at fixed source power (500 W). A similar trend is observed as for the source power experiments, namely the reverse breakdown voltage increases, consistent with a reduction in p-doping level near the GaN surface. Figure 31 plots breakdown voltage and dc chuck self-bias as a function of the applied rf chuck power. The breakdown voltage initially increases rapidly with ion energy (the self bias plus ~25 V plasma potential) and saturates above ~100 W probably due to the fact that sputtering yield increases and some of the damaged region is removed. Note that these are very large changes in breakdown voltage even for low ion energies, emphasizing the need to carefully control both flux and energy. We should also point out that our experiments represent worsecase scenarios because with real etching plasma chemistries such as Cl 2 /Ar, the damaged region would be much shallower due to the much higher etch rate. As an example, the sputter rate of GaN in a 300 W source power, 40 W rf chuck power Ar ICP discharge in ~40Å min -1, while the etch rate in a Cl 2 /Ar discharge under the same conditions is ~1100Å min -1. An important question is the depth of the plasma-induced damage. We found we were able to etch p-gan very slowly in boiling NaOH solutions, at rates that depended on the solution molarity (Figure 32) even without any plasma exposure of the material. This enabled us to directly measure the damage depth in plasma exposed samples in two different ways. The first method involved measuring the etch rate as a function of depth from the surface. Defective GaN resulting from plasma, thermal or implant damage can be wet chemically etched at rates much faster than undamaged material because the acid or base solutions are able to attack the broken or strained bonds present. Figure 33 shows the GaN etch rate as a function of depth in samples exposed to a 750 W source power, 150 W rf chuck power Ar discharge. The etch rate is a strong function of the depth from the surface and saturates between ~ Å. Within this depth range the etch rate is returned to the bulk value characteristic of undamaged p-gan. 24

25 The second method to establish damage depth of course is simply to measure the I-V characteristics after removing different amounts of material by wet etching prior to deposition of the rectifying contact. Figure 34 (top) shows the I-V characteristics from samples exposed to 750 W source power, 150 W rf chuck power (-160 V dc chuck bias) Ar discharges and subsequently wet etched to different depths using 0.1 M NaOH solutions before deposition of the Ti/Pt/Au contact. Figure 34 (bottom) shows the effect of the amount of material removed on the diode breakdown voltage. Within the experimental error of ± 12%, the initial breakdown voltage is re-established in the range Å. This is consistent with the depth obtained from the etch rate experiments described above. These values are also consistent with the damage depths we established in n-gan diodes exposed to similar plasma conditions. The other method of removing plasma-induced damage is annealing. In these experiments we exposed the samples to the same type of plasma (Ar, 750 W source power, 150 W rf chuck power) and then annealed under N 2 at different temperatures. Figure 35 (top) shows the I-V characteristics of these different samples, while Figure 35 (bottom) shows the resulting breakdown voltages as a function of annealing temperature. On this wafer, plasma exposure caused an increase in breakdown voltage from ~2.5 to ~18 V. Subsequent annealing at 400 o C initially decreased the breakdown voltage, but higher temperature produced a large increase. At temperatures above 700 o C, the diodes characteristics returned toward their initial values and were back to the control values by 900 o C. This behavior is similar to that observed in implantisolated compound semiconductors where ion damage compensates the initial doping in the material, producing higher sheet resistances. In many instances the damage site density is larger than that needed to trap all of the free carriers, and trapped electrons or holes may move by hopping conduction. Annealing at higher temperatures removes some of the damage sites, but there are still enough to trap all the conduction electrons/holes. Under these conditions the hopping conduction is reduced and the sample sheet resistance actually increases. At still higher annealing temperatures, the trap density falls below the conduction electron or hole concentration and the latter are returned to their respective bands. Under these conditions the sample sheet resistance returns to its pre-implanted value. The difference in the plasma exposed samples is that the incident ion energy is a few hundred ev compared to a few hundred kev in implant-isolated material. In the former case the main electrically active defects produced are nitrogen vacancies near the surface, whereas in the latter case there will be vacancy and interstitial complexes produced in far greater numbers to far greater depths. In our previous work on plasma damage in n-gan we found that annealing at ~750 o C almost returned the electrical properties to their initial values. If the same defects are present in both n- and p-type material after plasma exposure, this difference in annealing temperature may be a result of a Fermi level dependence to the annealing mechanism. The main conclusions of this study may be summarized as follows: 1. The effect of either H 2 or Ar plasma exposure on p-gan surfaces is to decrease the net acceptor concentration through creation of shallow donor levels, most likely N V. At high ion fluxes or ion energies there can be type conversion of the initially p-type surface. The change in electrical properties is more pronounced with Ar than with H 2 plasmas under the same conditions. 2. Two different techniques for measuring the damage depth find it to be in the range Å under our conditions. After removing this amount of GaN, both the breakdown voltage and wet chemical etch rates are returned to their initial values. 3. Post-etch annealing in N 2 at 900 o C restores the initial breakdown voltage on 25

26 plasma exposed p-gan. Annealing at higher temperatures degraded the electrical properties, again most likely due to N 2 loss from the surface. Ni/Au Ti/Pt/Au Ni/Au 0.3 µm Mg-doped (p~10 17 cm -3 ) GaN 1 µm undoped GaN Al 2 O 3 substrate Figure 26. Schematic of p-gan Schottky diode structures. 100 H 2 plasma 150 W rf Current (µa) 50 0 Current (µa) Voltage (V) Ar plasma 150 W rf control 300 W ICP 500 W 750 W 1000 W 1400 W Figure 27. I-V characteristics from samples exposed to either H 2 (top) or Ar (bottom) ICP discharges (150W rf chuck power) as a function of ICP source power prior to deposition of the Ti/Pt/Au contact Voltage (V) 26

27 Breakdown Voltage (V) ICP Power (W) Ar H 2 Ar H Self-dc Bias (V) Figure 28. Variation of diode breakdown voltage in samples exposed to H 2 or Ar ICP discharges (150 W rf chuck power) at different ICP source powers prior to deposition of the Ti/Pt/Au contact. The dc chuck self-bias during plasma exposure is also shown Current (A) control 300 W ICP 750 W ICP 1400 W ICP p-gan diode 150 W rf Ar plasma exposed Figure 29. Forward turn-on characteristics of diodes exposed to ICP Ar discharges (150 W rf chuck power) at different ICP source powers prior to deposition of the Ti/Pt/Au contact Reverse Bias (V) 27

28 100 Current (µa) 50 0 H 2 plasma 500 W ICP control 20 W rf 40 W 100 W 150 W 250 W Voltage (V) 100 Current (µa) 50 0 Ar plasma 500 W ICP Voltage (V) Figure 30. I-V characteristics from samples exposed to either H 2 (top) or Ar (bottom) ICP discharges (500W source power) as a function of rf chuck power prior to deposition of the Ti/Pt/Au contact. 28

29 Breakdown Voltage (V) rf Power (W) Ar H 2 Ar H Self-dc Bias (V) Figure 31. Variation of diode breakdown voltage in samples exposed to H 2 or Ar ICP discharges (500 W source power) at different rf chuck powers prior to deposition of the Ti/Pt/Au contact. The dc chuck self-bias during plasma exposure is also shown. 35 Etching Rate (Å/min) p-gan in Boiling NaOH Figure 32. Wet etching rate of p-gan in boiling NaOH solutions as a function of solution molarity Solution molarity (M) 29

30 10 4 Etching Rate (Å/min) Ar plasma exposed p-gan in boiling 0.1 M NaOH Depth (Å) Figure 33. Wet etching rate of Ar plasma exposed (750 W source power, 150 W rf chuck power) GaN as a function of depth into the sample. 30

31 100 Current (µa) 50 0 control as-exposed 150 Å 300 Å 400 Å 600 Å Voltage (V) 20 Breakdown Voltage (V) control as-exposed Depth Removed (Å) Figure 34. I-V characteristics from samples exposed to ICP Ar discharges (750 W source power, 150 W rf chuck power) and subsequently wet etched to different depths prior to deposition of the Ti/Pt/Au contact (top) and breakdown voltage as a function of depth removed (bottom). 31

32 100 Current (µa) control as-exposed 400 o C 500 o C 550 o C 650 o C 750 o C 800 o C 900 o C Voltage (V) 50 Breakdown Voltage (V) as-exposed 0 control Annealing Temperature ( o C) Figure 35. I-V characteristics from samples exposed to ICP Ar discharges (750 W source power, 150 W rf chuck power) and subsequently annealed at different temperatures prior to deposition of the Ti/Pt/Au contact (top) and breakdown voltage as a function of annealing temperature (bottom). 32

33 (f) Oxygen Diffusion into GaN Epitaxial layers of GaN consisting of 1µm undoped (n~10 16 cm -3 ) followed by 0.3µm of Mg-doped (hole concentration, p ~9x10 17 cm -3 ) were grown on c-plane Al 2 O 3 substrates by rf plasma activated MBE. These layers were capped with 1800Å of SiO 2 grown by Inductively Coupled Plasma Chemical Vapor Deposition (ICP-CVD) at 50 o C using SiH 4 and 17 O-enriched (50%) O 2 in a Plasma-Therm 790 reactor. The ICP source power was 300W (2 MHz), while the sample position was biased at 5V using 5W of 13.56MHz power. Under these conditions there is minimal change in the electrical or optical properties of the GaN as measured by Hall and cathodoluminescence measurements, due to the low energy of the incident ions (< 30eV). Sections of these samples were annealed for 5 mins at 500, 700 or 900 o C under N 2 in a Heatpulse 610 furnace. SIMS measurements were performed on the as-deposited and annealed samples both before and after removal of the SiO 2 in buffered HF solution at 25 o C. Figure 36 shows SIMS depth profiles of the as-deposited structure. There is a high concentration of 17 O in the SiO 2 film and the interface with the GaN is abrupt. Samples annealed up to 900 o C showed no change in the profiles of the lattice elements, including the Mg in the GaN. The SiO 2 was selectively removed in buffered HF and there was little difference in its etch rate before and after annealing, indicating that there was little densification resulting from the high temperature process. Figure 37 shows SIMS profiles of 17 O in the GaN after different annealing temperatures. Note that there is the usual high concentration, near-surface ( 200Å) signal characteristic of SIMS profiling through a surface or interface and which is basically an artifact of the measurement. In the as-deposited sample the 17 O signal is returned to the background level of ~10 17 cm -3 at a distance of Å. By sharp contrast, in the samples annealed prior to removal of the SiO 2, the 17 O concentration and depth of incorporation show clear increases for higher annealing temperatures. The 17 O clearly diffuses from the SiO 2 into the GaN during annealing. There is no indication of pairing of oxygen with Mg to form Mg-O complexes, which should be evident as a plateau in the O profile. There are some obvious implications of these results: Firstly, the use of SiO 2 masks for ELO of GaN could produce n-type autodoping of the material by oxygen incorporation. Secondly, SiO 2 is not a suitable choice as an encapsulant or annealing of implanted GaN, for the same reason. The 17 O diffusion profiles in Figure 37 clearly do not follow an erfc distribution and the fact the logarithm of the concentration is almost linear in penetration depth is a clear signature of pipe diffusion. The expanded regions around threading dislocations provide an easy path for diffusion of impurities, with an activation energy typically half that for diffusion in the bulk of the material. In a simple picture one can consider the bulk and pipe diffusion to be independent, with the square of the diffusion distance given by X 2 = 2Ddt + 2Dbt where D d, b are the diffusivities in the dislocations or bulk, respectively and t is the diffusion time. If D d > >D b and the oxygen-dislocation binding energy forward partitioning to the dislocation then the overall mass transport of the oxygen would be dominated by the pipe diffusion. Since this appears to be the case from Figure 37, we can obtain a rough estimate of 33

34 2 X Dd from, where X is the depth at which the oxygen concentration falls to cm -3 and t = 2t 300 secs. Figure 38 shows the resulting values of D in Arrhenius form. At least squares fit to the data yielded the relationship 12 D = 4.5 ± 2.2x 10 exp ( 0.23 ± 0.12eV / kt ) where k is Boltzmann s constant. The activation is approximately half that expected for diffusion of interstitials in bulk material. We do not know the final lattice position of the oxygen, but can estimate that <30% is substitutional based on the fact that we could not measure any change in the carrier concentration, obtained by Hall effect using a two band model (28) in the 900 o C diffused sample. The diffusion behavior of oxygen originating from SiO 2 encapsulant layers is obviously quite different from implanted oxygen. In the latter situation the high vacancy concentration created by the implanted O + ions may enhance the occupation probability of substitutional sites, i.e. there is a higher efficiency for creation of O N. There are still many unanswered questions concerning the effect of strain induced in the near-surface region by the SiO 2 cap (which is known to enhance point defect diffusion in other compound semiconductor systems) (29) and of the exact role of threading dislocations in the GaN on the diffusivity of oxygen. The latter can be answered by repeating the experiments in bulk substrates when they become available, while the former will require comparison of diffusion profiles from SiO 2 films of varying stress. In summary, the use of isotopically labeled O 2 for deposition of SiO 2 layers on GaN has allowed the unambiguous observation of oxygen diffusion into the GaN during annealing in the range o C, which are typical contact alloying temperatures. Based on the measured activation energy for the oxygen diffusivity, it migrates in interstitial form along dislocations. In addition to the more widely recognized ability of atomic hydrogen to migrate rapidly into GaN at moderate temperatures, our results show that one must also be aware of the possibility of oxygen indiffusion during thermal treatments. CONCENTRATION (atoms/cc) O 16 O 18 O SiO 2 /GaN Si (counts) GaN (counts) SECONDARY ION INTENSITY (cts/sec) Figure 36. SIMS profiles of asdeposited SiO 2 layer on GaN DEPTH (Angstroms)

35 10 7 CONCENTRATION (atoms/cc) O in GaN GaN (counts) 500 o C 700 o C 900 o C as deposited SECONDARY ION INTENSITY (cts/sec) DEPTH (Angstroms) 10 0 Figure 37. SIMS profiles of 17 O in GaN annealed at different temperatures for 5 mins prior to removal of the SiO 2 layer O in GaN D (cm -2 s -1 ) /T (K -1 ) Figure 38. Arrhenius plot of 17 O diffusivity in p-gan. 35

36 (g) GaAs(C ) Regrowth as a Contact Layer to p-gan(mg) A serious drawback of p-n junction GaN electronic and photonic devices is the high contact resistance between p-type GaN and its contact metal, which increases turn-on voltages and produces heating of the device. Many different metal schemes have been examined, and generally it is found that contact metals with large work functions can reduce turn-on voltages. Ni/Au remains the standard metallization employed for most light-emitting diodes and laser diodes. The problem is even more acute for electronic devices such as heterojunction bipolar transistors, where a specific contact resistance in the 10-7 Ω cm 2 range is desirable, far smaller than the desired values (10-5 Ωcm 2 ) for photonic devices and well below the typical values obtained experimentally with Ni/Au ( Ω cm 2 ). One possible approach to reducing the contact resistance is growth of an overlayer of a smaller gap semiconductor. A well-known example of this is use of In x Ga 1-x As contact layers on n-gaas. Due to the heterojunction band discontinuity at the interface of InAs/GaAs, which creates a barrier for transport of electrons, it is generally necessary to grade the interface from GaAs to InAs using In x Ga 1-x As. In the case of growth of GaAs on GaN, there is a large valence band offset, generally reported to be between 1.8 and 2.0eV. It would therefore be desirable to incorporate graded layers of GaAsN, but it is only possible to achieve N in GaAs or As in GaN concentrations of a few per cent. However, since it is possible to achieve extremely high hole concentrations (>10 20 cm -3 ) in carbon-doped GaAs, it seems like a valuable exercise to measure the contact resistance of GaAs(C)/GaN(Mg) structures. In this section we report that while good specific contact resistances can be obtained to the individual GaAs(C) and GaN(Mg) layers, there is still relatively poor hole transport across the interface between the two materials. The starting material was ~1µm of p + GaN(Mg) grown on sapphire by rf plasma activated Molecular Beam Epitaxy. The room temperature hole concentration was ~10 17 cm -3. Layers of GaAs(C) with thicknesses of Å were grown either by Metal Organic Chemical Vapor Deposition (MOCVD) or Metal Organic Molecular Beam Epitaxy (MOMBE) at 650 o C or 525 o C, respectively. The source chemicals were trimethylgallium and arsine in both cases. Hall measurements showed hole concentrations in the GaAs of 1 1x10 20 cm -3 for the MOCVD sample and 1 3x10 19 cm -3 for the MOMBE sample. E-beam deposited TiPtAu was used as a contact metallization for the GaAs and NiAu for the GaN. Both were patterned by lift-off to produce a transmission line method (TLM) grid. The pad spacings were 2, 4, 8, 16 and 32µm, with the pads being 100x150µm 2. Mesas were formed in the GaAs by NH 4 OH:H 2 O 2 wet etching to prevent current spreading. A scanning electron micrograph (SEM) of the complete structure is shown in Figure 39. Pieces of the samples were also annealed at o C for 15 secs under a N 2 ambient in a Heatpulse 610T system. Figure 40 shows a schematic of the band diagram for the p-gaas(c)/p-gan(mg) structure. Most of the bandgap difference is taken up by the valence band offset. We assume there will also be a high density of interface states because of the lattice and bonding mismatches. With this band alignment, the use of GaAs overlayers on GaN should provide excellent n-type contacts, but provide a high barrier to hole transport. However a recent report by Horita et.al. found that GaAs interlayers modified the band alignment at a metal/n-gan interface. In their case they only grew about 4 monolayers of GaAs, which was found to grown epitaxially in a (111) orientation on the (0001) p-gan. Such thin layers are probably not robust 36

37 enough for practical devices that must undergo thermal processes. This is why we chose to grow thicker GaAs layers. To examine the chemical and structural characteristics we performed Secondary Ion Mass Spectrometry (SIMS) and Transmission Electron Microscopy (TEM) analysis. Figure 41 shows SIMS profile of the MOMBE-grown structure. The GaAs/GaN interface is quite sharp and the carbon concentration is ~2x10 19 cm -3. In correlating the carbon and hole concentrations we can see that the active fraction is high, indicating that the electrical properties of the GaN are not much degraded by the growth on a lattice-mismatched substrate. Figure 42 shows a crosssectional TEM micrograph of the MOCVD-grown structure. There is a high concentration of threading dislocations (~5x10 10 cm -2 ) due to the lattice mismatch between the Al 2 O 3 substrate and the p-gan. These dislocations continue into the overgrown GaAs layer. A summary of the electrical results is shown in Table I. For unannealed contacts on GaAs(C) we obtained values of specific contact resistance between 9-14x10-6 ohm.cm 2, with the lower values obtained for the higher doped MOCVD material. After the 800 o C anneal, these values were reduced by factors of 2-3. Clearly the contact resistance to the GaAs is quite low. Similarly for the GaN(Mg), values typical of state-of-the-art Ni/Au contacts were obtained, i.e. in the ohm-cm 2 range. The contact resistance of the GaAs/GaN structure is better than that of GaN alone, but was still in the 10-3 Ωcm 2 range. Clearly the abrupt GaAs/GaN interface has too large a valence band offset even for tunnelling from a GaAs layer doped to metallic levels to overcome. Much better hole transport would be obtained if the composition of the carbon-doped layer could be graded from GaN to GaAs, but this is not possible given the large miscibility gap of this system. Approaches involving piezo-induced accumulation of holes are difficult to envision for vertical current transport structures, while various types of superlattices are not attractive for the reason one still needs a small gap material that can be heavily doped p- type and remain thermally stable. There has also been little success achieving p-type doping of high-in content InGaN alloys. At this stage, reduced acceptor compensation in the GaN and use of reacted contact metallizations might be the most promising approaches. GaAs overlayers with high p-type doping levels were grown on p-gan. While good specific contact resistances were obtained for the GaAs and GaN layers individually, hole transport through the GaAs/GaN interface was still relatively poor due to the large valence band offset. Table I. Specific Contact Resistance of Ni/Au p-ohmic Contacts (Measured at 250 o C) Material ρ c(ohm cm 2 ) - unannealed ρ c(ohm cm 2 ) 800 o C p-gaas(c) 9-14x x10-6 p-gan(mg) 8x10-2 4x10-3 p-gaas( C)/p-GaN(Mg) 7x10-3 2x

38 Figure 39. SEM micrograph of TLM pattern on GaAs/GaN structure. Metal p-gaas (C) p-gan (Mg) 3.4 ev 1.43 ev ÄE C ~ 0.2eV Interface states E F ÄE V ~ 1.8eV Figure 40. Schematic of band diagram for GaAs/GaN structure. 38

39 CONCENTRATION (atoms/cc) As (counts) C GaAs/GaN O GaN (counts) SECONDARY ION INTENSITY (cts/sec) DEPTH (Angstroms) 10 0 Figure 41. SIMS profiles for GaAs/GaN structure grown by MOMBE. Figure 42. TEM cross-section of GaAs/GaN structure grown by MOCVD. 39

40 (h) Deep Mesa Etching in SiC Bulk 4H-SiC substrates (Al doped; p = 6x10 18 cm -3 ) with Si face (0001) orientation were cleaved into 5x5 mm 2 sections. In etch rate experiments, part of each sample was masked with Apiezon wax, and the etch depths obtained from stylus profilometry measurements. In investigation of potential mask materials, Si wafers were deposited with 1 µm thick Al or Ni (plated in both cases) or ITO (sputtered), and sections from these samples were also masked with Apiezon wax for etch rate experiments. The etching was performed in a Plasma Therm 790 system, in which the ICP source operates at 2 MHz and powers from W. The samples were thermally bonded to the rf powered (13.56 MHz, W) chuck. Ion flux is basically controlled by the ICP source power, while ion energy is the sum of plasma potential (~ -25 ev) and dc chuck self-bias. In the initial experiments, four different F 2 -based gas chemistries were compared in terms of the SiC etch rates they produced. The gases (SF 6, NF 3, PF 5 or BF 3 ) were introduced into the ICP source through mass flow controllers at a fixed rate of 15 standard cubic centimeters per minute (sccm). Based on those results we chose NF 3 as the gas producing the fastest SiC etch rate, and then examined mask selectivity in NF 3 /O 2 discharges. The O 2 was added in an attempt to reduce mask erosion rate through formation of surface oxides with low volatility. Figure 43 shows the etch rate (top) and etch yield (bottom) for 4H-SiC in ICP discharges as a function of source power with the four different plasma chemistries. In these experiments the rf chuck power was held constant at 250 W, corresponding to dc self-biases of roughly 290 V at 250 W source power, to 200 V at 1500 W source power. Clearly, NF 3 and SF 6 produce the fastest rates, and this correlates to the relative dissociation of these gases in the ICP source. Optical emission spectroscopy showed very intense atomic fluorine lines in the range nm for both NF 3 and SF 6, while the intensities of these lines were much lower for BF 3 and PF 5. The etch rates are also in good correlation with the average bond energies for the feedstock gases, i.e. BF kcal/mol, PF kcal/mol, SF kcal/mol and NF kcal/mol. The lower the bond energy, the more effective is the dissociation in the ICP source to form atomic fluorine neutrals which are the active etchant species. The etch products are probably SiF x and CF x species (x would not necessarily have to reach its fully coordinated value of 4 under ionassisted conditions), although we did not have adequate sensitivity in our OES system to detect them during the etching process. In the case of BF 3 the SiC etch rate decreases slightly at high source powers, which might be related to the fall-off in ion energy under those conditions or to desorption of the reactant fluorine before it can form etch products with the SiC. Figure 44 shows the rf power dependence of SiC etch rate at a fixed ICP source power of 750 W. The dc self-bias increases almost linearly with chuck power, as shown in the lower part of Figure 44. In NF 3, SF 6 and PF 5 there is a general trend for increasing etch rate as rf chuck power is increased. This could be related to increased Si-C bond-breaking efficiency at higher ion energies, allowing more etch products to form. In the case of BF 3 the etch-limiting step is probably the supply of atomic fluorine because of the lower efficiency in dissociating this gas. Polished SiC surfaces often have relatively rough morphologies due to residual mechanical damage. This is evident in the Atomic Force Microscope (AFM) scan of a control sample (Figure 45), showing a root-mean-square (RMS) roughness of 2.5 nm. After dry etching with any of the different plasma chemistries, the surface roughness improves to values in the range nm. This smoothing of initially rough surfaces is commonly observed in iondriven etch processes, and originates in the angular dependence of ion mill rates. This leads to 40

41 faster removal rates for high aspect ratio features and creates a smoother morphology. Figure 46 shows the dependence of RMS surface roughness in ICP source power in the four different plasma chemistries. Under virtually all conditions the etched surfaces are smoother than the unetched control samples. We chose standard conditions of 750 W source power 250 W rf chuck power and 2 mtorr for NF 3 discharges, and added O 2 to the chemistry in order to examine its effect on etch selectivity of SiC to the different mask materials. Figure 47 shows the etch rates (top) and resultant selectivities for SiC over the masks (bottom) for NF 3 /O 2 discharges, as a function of NF 3 percentage of the gas load (15 sccm). The etch rates increase with NF 3 composition for SiC and the mask materials. At high O concentrations there is actually net deposition on Al as it oxidizes, so that the SiC selectivity over Al is infinite. However the requirement for via hole etching is that the SiC etch rate be > 4000 Å-min -1. Maximum selectivities were > 20 over Ni and ~7 over Al. Note that there were unacceptably low selectivities for SiC over ITO. The influence of ICP source power on the etch rates and selectivities are shown in Figure 48 for 10 NF 3 /5O 2 discharges with fixed chuck power (250 W) and process pressure (2 mtorr). The ITO shows unacceptably high etch rates, while the oxidation of Al produces infinite selectivities for SiC over Al at high source powers. The maximum selectivity for SiC over Ni at these conditions was ~5. Figure 49 shows the dependence of etch rates and selectivities on rf chuck power for 10NF 3 /5O 2 discharges at fixed source power (750 W) and pressure (2mTorr). The ITO once again has the poorest selectivities, while the SiC/Al selectivity is infinite at higher chuck powers. It appears under these conditions that the oxidation rate of the Al is enhanced. To demonstrate the feasibility of via hole etching, we patterned SiC with Al masks with openings down to 25 µm in diameter. ICP discharges of pure NF 3 with 750 W source power and 250 W rf chuck power were used to etch the SiC to a depth of ~13 µm. This depth was limited only by the fact we wanted to be conservative, given the limited quantity available of SiC with thick Al masks. Figure 8 shows scanning electron micrographs of 25 µm diameter (top) and 35 µm diameter (bottom) features. The mask survives quite well and the sidewall profile is suitable for subsequent metallization. The etching of via holes in SiC substrates in practical time frames appears feasible, using the combination of ICP NF 3 or SF 6 discharges and thick metal masks. Addition of O 2 to the plasma chemistry increases etch selectivity for SiC over Al under some conditions, due to oxidation of the Al. Etch rates in excess of 8,000 Å-mim -1 have been achieved for 5x5 mm 2 samples of SiC, with ~50% of this area exposed to the plasma. The etch rates for larger samples will be less due to loading effects. Based on our experience with other materials, the fall-off is likely to be of the order of 20-30% when scaling to 3 diameter wafers with ~10% of the area exposed to the plasma. The SiC etch rates with PF 5 and BF 3 are much lower than with NF 3 and SF 6, which is a result of their lower dissociation efficiency in the ICP source. 41

42 Etch Rate (Å/min) PF 5 BF 3 SF 6 NF 3 250W rf, 2 mtorr, 15 sccm ICP-Power (W) Etch Yield (atom/ion) PF 5 BF 3 SF 6 NF 3 250W rf, 2 mtorr, 15 sccm ICP-Power (W) Figure 43. Etch rate (top) and etch yield (bottom) as a function of ICP source power for SiC in pure NF 3, SF 6, PF 5 or BF 3 discharges (250W rf chuck power, 2 mtorr). 42

43 7000 Etch rate (Å/min) PF 5 BF 3 SF 6 NF PF 5 rf-power (W) dc self-bias (-V) BF 3 SF 6 NF 3 750W ICP rf-power (W) Figure 44. Etch rate (top) and dc self-bias (bottom) as a function of rf chuck power for SiC in pure NF 3, SF 6, PF 5 or BF 3 discharges (750W source power, 2 mtorr). 43

44 SiC Control : RMS = 2.5 nm PF 5 : RMS = 2.0 BF 3 : RMS = W Source Power 250 W rf chuck power 1 minute SF 6 : RMS = 1.4 NF 3 : RMS = 0.6 nm Figure 45. AFM scans for SiC surfaces before and after etching in pure NF 3, SF 6, PF 5 or BF 3 discharges (1500W source power, 250W rf chuck power). 44

45 4 PF 5 BF 3 3 SF 6 RMS (nm) 2 1 Control NF 3 Figure 46. RMS surface roughness of SiC surfaces as a function of ICP source power after etching in pure NF 3, SF 6, PF 5 or BF 3 discharges (250W rf chuck power, 2 mtorr) ICP-Power (W) Etch Rate (µm/min) 1.0 SiC Al Ni 0.5 ITO Etching Deposition 750W ICP 250W rf 2mTorr Selectivity 21 SiC/Al Infinite 18 SiC/Ni SiC/ITO %NF 3 (Total flow NF 3 /O 2 is 15 sccm) Figure 47. Etch rates (top) and selectivity for SiC over various mask materials (bottom) as a function of % NF 3 in ICP NF 3 /O 2 discharges (750W source power, 250W rf chuck power). 45

46 2 Selectivity Etch Rate (µm/min) NF 3 /5O 2 250W rf 2mTorr SiC Al Ni ITO Etching Deposition Infinite Figure 48. Etch rates (top) and selectivity for SiC over various mask materials (bottom) as a function of source power in ICP 10 NF 3 /5O 2 SiC/Al SiC/Ni SiC/ITO discharges (250W rf chuck power, 2 mtorr) ICP Power (W) Etch Rate (µm/min) Etching SiC Al Ni ITO Deposition 10NF 3 /5O 2 750W ICP 2mTorr -1 Selectivity Infinite SiC/Al SiC/Ni SiC/ITO Figure 49. Etch rates (top) and selectivity for SiC over various mask materials (bottom) as a function of rf chuck power in ICP 10 NF 3 /5O 2 discharges (750W source power, 2 mtorr) rf Power (W) 46

47 Figure 50. SEM micrographs of features etched into Al-masked SiC samples. 47

48 (h) Packaging Tasks (a) Plan Adapt U of FL mask designs to MCNC processes Fabricate masks for device passivation clear and substrate fab Clear device passivation layer Coordinate substrate fabrication Assemble devices (b) Packaging Task Progress Device mask Clear passivation layer for bump attachment (See Figure 51) Substrate mask set Bumping service by Unitive Electronics, Inc. (Research Triangle Park,NC) (See Figure 52) Solder bumps over Au metallization on alumina Joining (See Figures 53 and 54) Aligner/bonder Solder reflow 48

49 Figure 51. GaN Device Silicon nitride passivation layer cleared to accept solder bumps Au pads exposed on GaN device 49

50 Figure 52. Flip-Chip Substrate Solder bump processing by Unitive Electronics, Inc. ( 80 µm solder bumps on metallized alumina Substrate passivation layer cleared for wafer probing of FET device Solder bumps provide electrical contact to device Substrate provides probe contact and connection to ground 50

51 Figure 53. Device Assembly Flip Chip Aligner Placement and alignment Temporary tacking Solder reflow Testing Rework 51

52 Figure 54. Assembled Device Solder bumps reflowed for device attachment to substrate Gap is approximately 50 mm 52

53 (c) Power Electronic Packaging COTS Components Chip coolers from Polycool, Inc. Thermal Management Systems Air-cooled (composite fins, chip coolers) Water-cooled (micromechanical heat pump) Thermal Interfaces Thermoelectric coolers Conformable, thermally conductive material Thermal adhesives and gels Technology Demonstrations Assembled prototypes Thermal testing (acoustic imaging, thermal test chip) Thermoelectric cooling system from Tellurex, Inc. 53