Thermo-Mechanical Challenges in Stacked Packaging

Transcription

1 Heat Transfer Engineering ISSN: (Print) (Online) Journal homepage: Thermo-Mechanical Challenges in Stacked Packaging Dereje Agonafer, Abhijit Kaisare, Mohammad M. Hossain, Yongje Lee, Bhavani P. Dewan-Sandur, Terry Dishongh & Senol Pekin To cite this article: Dereje Agonafer, Abhijit Kaisare, Mohammad M. Hossain, Yongje Lee, Bhavani P. Dewan-Sandur, Terry Dishongh & Senol Pekin (2008) Thermo-Mechanical Challenges in Stacked Packaging, Heat Transfer Engineering, 29:2, , DOI: / To link to this article: Published online: 07 Oct Submit your article to this journal Article views: 1313 View related articles Citing articles: 15 View citing articles Full Terms & Conditions of access and use can be found at Download by: [ ] Date: 19 December 2017, At: 07:43

2 Heat Transfer Engineering, 29(2): , 2008 Copyright C Taylor and Francis Group, LLC ISSN: print / online DOI: / Thermo-Mechanical Challenges in Stacked Packaging DEREJE AGONAFER, 1 ABHIJIT KAISARE, 2 MOHAMMAD M. HOSSAIN, 3 YONGJE LEE, 4 BHAVANI P. DEWAN-SANDUR, 2 TERRY DISHONGH, 3 and SENOL PEKIN 3 1 Electronics, MEMS, and Nanoelectronics Systems Packaging Center, University of Texas at Arlington, Arlington, Texas, USA 2 Mechanical and Aerospace Engineering Department, University of Texas at Arlington, Arlington, Texas, USA 3 Intel Corporation, Chandler, Arizona, USA 4 Samsung Electronics, Seoul, Korea The convergence of computing and communications dictates building up rather than out. As consumers demand more functionality in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. In this paper, a review of thermo-mechanical challenges for stacked die packaging is discussed. INTRODUCTION As the demand for more functionality in electronic systems continues to grow, more effort is focused on the development of system-in-a-chip devices. For years, an economical way to add more functions to an electronic system was to integrate more functions into the individual chips themselves. However, cost and yield issues can prevent such integration from being economically feasible. Furthermore, some chip sets that logically belong together to form a system or subsystem cannot be integrated into a single dice due to differences in the die materials. High-density packaging technologies have advanced to the point where intentionally splitting a single chip system into multiple dice can provide both performance and cost advantages. In 2-D integrated circuits, the reduction of transistor features over time ( Moore s Law ) provides ever greater densities of transistors and faster clock rates, but is now leading to circuits where the spatial domain of signal propagation between clock edges is smaller than the total chip area. A decrease in this span of signal synchronicity is leading to a paradigm shift in microarchitectures. Access to the third dimension will significantly Address correspondence to Dr. Dereje Agonafer, Electronics, MEMS, and Nanoelectronics Systems Packaging Center, University of Texas at Arlington, Arlington, Texas agonafer@uta.edu simplify chip-scale communications and the transfer of information among the processing elements and also provide rapid access to memory and configurable logic. The active devices are confined to a plane in the upper surface of a semiconductor crystal with several layers of fixed interconnects separated by dielectrics above. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation [1]. 3-D technology would enable extremely dense solid-state memory to be arrayed within a few microns of the processing elements, which reduces access times. The 3-D arrangement also provides opportunities for new circuit architectures based on the geometrical ability to have greater numbers of interconnections among multi-layer active circuits. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration. True 3-D integrated circuits can operate at higher clock rates and can consume less power over their 2-D implementations, as the 3-D arrangement minimizes the length of circuit interconnects [1]. Over the past few years, die stacking has emerged as a powerful tool for satisfying challenging IC packaging requirements. Die stacking (3-D packaging) can be done using two or more die within a single package, or by stacking and connecting 134

3 D. AGONAFER ET AL. 135 Figure 1 Stacked packages from Amkor and Intel. completed packages. A 3-D package has significant advantages over conventional packaging regarding size (40 50% reduction), volume (5 6 times reduction compared to MCM), weight (2 13 times reduction compared to MCM), silicon efficiency (100% as compared to 20 90% in the case of MCM), delay, noise, power consumption reduction, and speed [2]. 3-D packaging offers several benefits, include smaller, thinner packages; more silicon functions per cm 2 of board space and per cm 3 of application space; significant size and weight reductions; reduced packaging costs and components; reduced system level cost for System in Package (SiP) vs. System on Chip (SoC) approach; and system level size reduction. Figure 1 shows stacked packages from Amkor and Intel. Die stacking has evolved to include three-or-four-die stacks and side-by-side combinations of stacked and unstacked die within a package. The die are typically mounted to a substrate, which is bumped to create either a chip scale package (CSP) or ball grid array (BGA) as the final package. Die stacking was traditionally carried out with die of different sizes so the top die was always smaller than the bottom die to permit wire bonding of both. Figure 2 shows the die stacking trend. Currently, it is common to see the stacking of same-size die or a larger dice overasmaller one. One way to accommodate a larger or samesize dice on top is to place a spacer (a dummy piece of silicon) between the two. Then, the spacer lifts the top die just enough to allow wire bonding to the bottom die or substrate. However, the larger the overhang on the top and the thinner the die, the harder it becomes to wire bond to the top die. From a technical point of view, just how many die can be stacked depends on the thickness of the final package and the Figure 2 Chip stacking trend [3]. thickness of each layer within the package. These include the substrate, die, spacers (if required), and BGA ball diameter. Substrate thickness is in turn influenced by the number of chip I/Os, which determines the number of substrate layers necessary. BGA ball diameter follows BGA ball pitch. In the past, a package height of 1.4 mm was the standard for stacked-chip packages in these applications. Now demand is shifting to 1.2- and 1.0-mm high packages, and even 0.8 mm is a possibility. It is currently possible to build over three die stacks into 1.4-mm packages [4]. One classification of a system-in-a-package (SiP) solution gaining wider acceptance is the stacked-die package, where the main advantage is saving space. In addition, stacking allows the packaging of heterogeneous devices. Cell phones and other applications have created the need for more innovative chip-scale packaging (CSP) solutions. The wiring restrictions on PWBs and package interposers dictate that 0.50 or 0.40 mm is the minimum practical pitch for CSP, making it increasingly difficult to achieve higher package density in X and Y. System designers are now forced to pursue 3-D package alternatives, exploiting the Z dimension, for cell phones and most other compact consumer products. Evolution from cell phones with only a base-band processor and limited memory to today s high-end phones with an additional applications processor and memory has driven the industry to 3-D packaging solutions. Portable electronics, in which size is such an important attribute and where modularity of configuration counts heavily, are a perfect application for stacked die. All the major manufacturers of cell phones use stacked CSP for Flash and SRAM devices in their leadingedge phones, and in Japan, all cell phone manufacturers employ stacked technology in virtually all of their products. As a reference, there were 393M cell phones sold in 2001, and the analysis targets somewhere between 785M and 1140M in This market will dominate 3D manufacturing. Some other applications besides cell phones and wireless PDAs that are emerging for stacked die are set top boxes, network devices, logic, and DRAM [5]. Aggravating the packaging is the highly non-uniform power in high density microprocessors. The non-uniform power distribution occurs when the central processing unit (CPU) or core processor region of the die dissipates a significant fraction of the total power while the other regions of the die such as cache dissipate little or no power. This non-uniformity of power distribution results in a large die temperature gradient, with localized hot spots that are expected to affect the processor performance, product reliability as well as yield. The integrity of solder joints is a major reliability concern in modern microelectronic packages. Temperature fluctuations caused by either power transients or environmental changes, along with the resulting thermal expansion mismatch between the various package materials, results in time- and temperaturedependent creep deformation of solder. This deformation accumulates with repeated cycling and ultimately causes solder joint fatigue cracking and interconnect failure. To minimize development costs and maximize reliability performance, advanced analysis is a necessity during the design and development phase

4 136 D. AGONAFER ET AL. of a microelectronic package. This requires the utilization of a life prediction methodology that is based on the damage mechanisms experienced in a field operation environment. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the stacked die package. Because plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. This paper discusses the analysis methodologies as implemented in a finite element simulation software tool and the corresponding results for the solder joint fatigue life. Simulated accelerated temperature cycling is performed to obtain the plastic work due to thermal expansion mismatch between the various materials. Accumulated plastic strains were incorporated to predict the fatigue life. The model incorporates time-dependent and time-independent plasticity (i.e., creep) for the solder materials. Solder joint fatigue life is calculated for three different die configurations and compared for optimum stacking architecture. Several finite element-based analysis methodologies have been proposed that predict solder joint fatigue life. Of all these methodologies, Darveaux s methodology seems to be the most popular due to the ease of implementation. It links laboratory measurements of low-cycle fatigue crack initiation and crack growth rates to the plastic work of the solder. It is a strain energybased approach, where the work term consists of time-dependent creep and time-independent plasticity. This inelastic behavior is captured in ANSYS using Anand s constitutive model [6]. The modeling methodology utilizes finite element analysis to calculate the viscoplastic strain energy density accumulated per cycle during thermal or power cycling. The strain energy density is then utilized with crack growth data to calculate the number of cycles to initiate a crack and the number of cycles for the crack to propagate across a solder joints diameter. Darveaux s methodology has been previously presented in the successful analyses of various electronic assemblies from multiple industry sources. In many of these sources, the authors have presented reliability test data that validates the accuracy of Darveaux s methodology within ±2X, which is considered state of the art for this type of complex physical analysis [7]. This energy-based model is used in this study to predict the solder joint life of the Stacked CSP. MODELING PROCEDURE (THERMAL ANALYSIS) A molded Ball Grid Array [BGA] stacked package is considered for the analysis. The substrate is mm and 0.21 mm thick. A fully populated solder ball matrix with a ball count of 399 and a pitch of 0.6 mm is used. The stand off height after reflow is 0.2 mm. The mold cap is 0.90 mm thick and has the same dimensions as the package substrate. Both memory and logic processor modules were stacked on the same substrate. Table 1a gives package dimensions and material properties used in this analysis. Table 1 Component Package details Dimension (mm) A. Package dimensions used in thermal analysis Memory: die stack Memory - Bottom Die Logic Die Die Attach Thickness Mold Cap Substrate Substrate Mask Thickness Solder Ball Diameter 0.35 Stand-off Height (After reflow) 0.2 Solder Ball Pitch 0.6 PCB Material Thermal conductivity [W/m C] B. Material properties used in thermal analysis Die 120 Die attach [non-conductive] 0.3 Substrate mask 250 Substrate core 0.3 Molding compound 0.88 Solder 50.6 PCB core [FR4] 0.18 Copper 393 Parameter Dimension (mm) C. Package used in thermo-mechanical analysis PCB Substrate Mold compound 1.2 Solder pitch 0.8 Solder ball diameter 0.33 Three different package architectures were modeled: rotated stack, staggered stack utilizing redistribution pads, and stacking with spacers. The memory module was made up of four dice. Three non-volatile die (dice 1, dice 2, and dice 3) measuring 4 6 mm, with a thickness of 0.1 mm, form the stack. The bottom volatile memory is made of a die measuring 9 10 mm, with a thickness of 0.1 mm. The logic dice measures mm with a thickness of 0.1 mm, and is placed below the memory dice. In the rotated stack, dice 2 was placed at 90 to dice 1 and dice 3. In the staggered stack, dice 2 was offset by 1 mm in the X and Yaxesofdie 1 and 3. For the spacer stack, three dummy silicon die measuring 3 5mmwith a thickness of 0.03 mm were placed in between die 1, 2, and 3. The overall package thickness was not to exceed 1.5 mm. The dimensions are not specific to a particular package. They are based on values found in present market (i.e., a typical molded BGA stack package). The printed circuit board (PCB) for the 5-Die molded BGA stack package was modeled according to the Joint Electron Device Engineering Council (JEDEC) standard EIA/JESD51 5. It is made up of two signal and two power layers (2S2P). The four layered PCB includes mm thick upper and lower trace layers, mm thick internal power planes, and 0.45 mm thick

5 D. AGONAFER ET AL. 137 Figure 3 Detailed view of package and PCB (mold cap hidden). core layers. The mm BGA package was positioned at the center of the mm 2S2P PCB. The detailed view of one of the configurations is as shown in Figure 3 [7, 8]. The geometries were modeled as parts using Pro/E WildFire TM 2.0 as a CAD tool. Then, an assembly was created for each of the stacking architectures. This ensured accurate material property assigning and material continuity of each component. Figures 4a c show the CAD models of the individual architectures in the package for different stacked architectures. The thermal resistance model of the assembly is shown in Figure 5. There are two paths for heat dissipation to the ambient. One is from the die stack, through the mold cap to the ambient. Figure 5 Thermal resistance model [9]. The second is from the die stack to the substrate, through the solder balls to the PCB, and through the PCB layers to the ambient. (There are additional paths that are not that significant; for example, through the wirebonds.) About 80% of the heat dissipation is through the latter path, as shown in Figure 6. This is because of high thermal resistance of the interface between the die mold cap and the mold cap ambient, which are given as R dice,r datch,r ovrmld, and R subs. The efficiency of heat dissipation is largely dependent on the thermal resistance of the interface of the package PCB (includes Figure 4 Different stacked combination with PCB and mold cap hidden: (a) rotated stack, (b) staggered stack, (c) spacer stack

6 138 D. AGONAFER ET AL. Increasing the thermal conductivity (k) of the PCB core to 0.8 W/m C from 0.18 W/m C: increased PCB k. Introducing underfill (k = 0.8 W/m C) for the solder balls: underfill. Introducing a copper spreader with the mold compound: Cu spreader. Figure 6 Heat dissipation path [9]. Additionally, the die attach on the logic die was changed to a conductive die attach, with value of k = 3W/m C [11]. This did not have a significant impact on the temperature distribution, and thus, not included in this paper. thermal resistance of the interface for PCB-ambient). This can be represented as: T j = P (R pckg + R pcb ) + T a (1) R pckg = (R dice, R datch, R ovrmld, R subs ) (2) Given the maximum junction temperature, [Tj] max, the maximum power that can be dissipated through the package and the PCB to the ambient air is determined by P max = ([T j ] max T a )/(R pckg R pcb ) (3) This implies that in order to reduce the junction temperature or to dissipate more power from the package, the thermal resistances of the interface between the package PCB and the PCB-ambient have to be minimized. Thermal resistance of the package is determined by the package size and materials [10]. For each of the stacking architecture, steady-state thermal simulation was carried out as a baseline study to determine the maximum junction temperature using Ansys WorkBench TM 10.0 as a finite element analysis (FEA) tool. The CAD models were imported into Ansys WorkBench TM Material properties were already assigned during CAD modeling. Initial analysis resulted in nodes greater than that allowed by the Academic License of Ansys WorkBench TM {>128K nodes}. Hence, a mapped face mesh with an edge size of one division was introduced. This reduced the number of nodes to fewer than 30,000. Baseline study further considers an application of an effective heat transfer co-efficient of 5 W/m 2 Contop and bottom surfaces of the PCB, and on top of the mold cap. All of the other properties held constant. The ambient temperature Ta was assumed to be 25 C. Even though the ambient temperature was 25 C, it resulted in a high junction temperature. It should be noted that in real world applications, the ambient temperature can be greater than or equal to 50 C. Based on the maximum junction temperature, the following thermal management strategies were investigated: MODELING PROCEDURE (THERMO-MECHANICAL ANALYSIS) For thermo-mechanical analysis, four die architectures were considered. Figure 7a d shows the basic structure of four different die stack architectures (spacer-stack, pyramid, rotated, and staggered) of the package for structural analysis. The original stacked die applications placed a smaller die on top of the larger die to create a pyramid stack. To improve assembly yield, it is recommended that the bottom die be at least 0.5 mm larger than the top die to ensure that the combination of the die attach placement error and die attach epoxy bleed-out do not impact wire bond ball and loop formation on the bottom die. The two die can be wire bonded in a single pass process to achieve optimum productivity. The second stacked die package is the same-size die package. In this package, an interposer or spacer die, typically made of Increasing the effective heat transfer coefficient on top of the mold cap to 20 W/m 2 C, keeping the effective heat transfer coefficient on top and bottom surfaces of the PCB constant (5 W/m 2 C): higher h. Figure 7 Basic structure of (a) spacer 3 die, (b) pyramid 5 die, (c) rotated 7 die, (d) staggered 3 die.

7 D. AGONAFER ET AL. 139 Table 2 Dimensions for various stacking configurations Parameter (mm) 3-Die 5-Die 7-Die A. Spacer die Die size Spacer size Die thickness Spacer thickness Paste thickness Rotated Die Staggered Die Parameter (mm) 3-Die 5-Die 7-Die 3-Die 5-Die 7-Die B. Rotated and staggered die Die size Die thickness Paste thickness Die 5-Die 7-Die Parameter (mm) Bottom Top Bottom Top Bottom Top Die size C. Pyramid die Die thickness Paste thickness silicon to match the coefficient of thermal expansion of the die, is placed on top of the bottom die to provide clearance for the wire bond loops that were made to the bottom die. The thickness of the interposer combined with the bond line thickness provides the clearance for the loops that have been bonded on the bottom die. As a guideline, the combined interposer and bond line thickness should be at least 50 µ greater than the maximum specified loop height of the wire bonds on the bottom die. After wire bonding the bottom die, a second die is then mounted on top of the interposer using a conventional die attach process. Stacking multiple die creates complexities in the overall package. As the number of die stacking increases, critical issues to address can be classified in three categories: material selection, design guideline issue, and assembly issues. Proper material needs to be selected for non-bleeding die attach to avoid thermal degradation, void and warpage-free mold compound, and substrate with good adhesion with mold compound and die attach. Design guidelines should be properly selected to minimize the die attach and other related parameters. Assembly processes need to be optimized such as wire bonding to reduce wire-to-wire shorting and wafer thinning. In general, the package has to meet the JEDEC standards, requirements for the PWB technology, underfilling, flip-chip rework, and the second-level assembly and reliability aspects. Critical parameters include challenges in assembly technology such as die attach selecting, wire bonding, wafer thinning, wire-to-wire shorting, and overmolding. For design reliability, it is desirable to reduce stress level at different parts of the packages, including die-to-die distance, substrate layer stack up, amount of encapsulant filling, elastomer layer thickness, die-to-die vertical attach material, and minimization of package to package interactions. FATIGUE MODEL DESCRIPTION A typical CSP package is considered for the simulation. A generic 9 9mm 2 (depopulated 5 5inthe middle) plastic CSP module on a one-layer PWB is adopted in the model study. SMD pads are used for the package, and NSMD pads are used on the PWB. The four different stacked package architectures evaluated were pyramid, rotated, staggered, and stacking with spacers. 3-die, 5-die and 7-die configurations were chosen for the three different architectures. The dimensions are given in Table 1a. The dimensions of the other parameters for spacer, pyramid, and rotated and staggered die configurations are given in Table 2. Studies have been done by changing the die cross-section to square and rectangular configuration with same package dimension for spacer and pyramid die stacking. Figure 8 shows the quarter symmetry finite element model for three different die stacking configurations: die stacking with spacers, pyramid stacking, and rotated stacking. Figure 9 shows the diagonal symmetry finite element model for staggered die configuration. Figure 8 Finite element model for three different die configuration: (a) stacked 5 die, (b) pyramid 5 die, (c) rotated 5 die.

8 140 D. AGONAFER ET AL. Figure 9 Finite element model for staggered 3 die configuration. MATERIAL PROPERTIES The accuracy of the FE model depends on the accuracy of the materials properties and proper meshing. Linear and non-linear, elastic and plastic, and time- and temperature-independent and -dependent material properties were incorporated in the finite element model, as displayed in Table 3. Thermo-mechanical properties used are Young s Modulus, coefficient of thermal expansion (CTE), and Poisson s ratio. The solder material was modeled with modified Anand s rate-dependent plasticity model. Anand s constitutive model incorporates viscoplasticity, a time-dependent plasticity phenomenon, where the development of plastic strains is dependent on the rate of loading [12]. Darveaux has presented solder constitutive relations based on Anand s model for rate dependent plasticity. Linear orthotropic material properties were used for the printed wire board and the BT (Bismaleimide Triazine) laminate substrate. Linear and non-linear, elastic and plastic, and time- and temperature-independent and -dependent material properties were incorporated in the FE models. Solder ball materials are meshed with Visco107 and all other package materials are meshed using the SOLID185 elements. To get stable results, mesh sensitivity is required. Because the simulation time is highly dependent on the number of elements and nodes, mesh sensitivity was done to compromise between the solving time Figure 10 Thermal cycle profile used for analysis. and stable data. By changing the model nodes, the plastic work accumulation and the solder joint fatigue life changes within a range of 5%. SOLUTION AND POST PROCESSING For evaluating the component reliability, a 60-minute thermal cycle, ranging from 40 to 125 C and consisting of 15-minute ramps and 15-minute dwell, was used. Figure 10 shows the thermal cycles used for the simulations. Nonlinear, diagonal, quarter, global models were used with ANSYS finite element solver. According to the fundamental mechanism, the models proposed for predicting the fatigue life of solder joints can be divided into five major categories: stress-based, plastic strain-based, creep strain-based, energy-based, and damage accumulationbased [13]. An energy-based fatigue life prediction model was used in this paper, as it is the most widely used model available for Pb-Sn solder. The combined probabilistic and optimization study deals with scalar parameters and can be incorporated in any failure model, especially for the case of lead-free solder where the use of energy based model is still under consideration. ANSYS APDL script was used for incorporating an energy-based fatigue life Table 3 Material properties for various package materials used in the finite element analysis [5] Component (material) Elastic moduli (MPa) Shear moduli (MPa) CTE (1/K) Poisson ratio Ball (63Sn37Pb) T N/A 24.5e Chip (silicon) N/A T T T 3 Conductor (copper) N/A T 0.34 Epoxy film (proprietary) T N/A < Tg, 288K Tg, 288K Mold cap (mold) N/A PCB core (FR4) T (XY) T (XY) (XY) 0.39 (XZ & YZ) T (Z) T (YZ & XZ) (Z) 0.11 (XY) PCB mask (dry film) 4137 N/A Substrate core (BT) N/A (XY) Substrate mask (dry film) 4137 N/A

9 D. AGONAFER ET AL. 141 The characteristic solder joint fatigue life (number of cycles to 63.2% probability of failure) can be calculated by summing the cycles to crack initiation with the number of cycles it takes for the crack to propagate across the entire solder joint pad diameter a. α is given by Figure 11 (a) Basic thermal architecture, (b) attachment used in the paper. model to predict solders joint fatigue life. The element interface thickness utilized in all models discussed herein was mm (1 ml). The layer of elements having maximum plastic work density is included in the calculation of the weighted average plastic work density, W ave : Element i=1 W i V i W ave = Elements (4) i=1 V i where W i designates the plastic work density in the ith element and V i is the volume of that element. A thermal cycle to crack initiation No is given by: N o = K 1 W K 2 ave (5) Crack propagation rate per thermal cycle da/dn : da dn = K 3 W K 4 ave (6) where W ave is the element volumetric average of the stabilized change in plastic work within the controlled eutectic solder element thickness.k 1, K 2, K 3, and K 4 are crack growth constants, which depend on geometry, loading, and the finite element analysis method. Crack growth [10] correlation constants K 1, K 2, K 3, and K 4 are respectively cycles/psi, 1.62, 3.34e-07, and α = N o + a (7) da dn Using this equation to assess the 63.2% failure probability lifetime is based on the assumption that the solder joint fatigue life follows an exponential distribution [10]. MODELING PROCEDURE (NON-UNIFORM POWER DISTRIBUTION) To model the optimization of maximum junction temperature on a given silicon chip with non-uniform power dissipation using a commercial FEM code, the different specific cases of power maps that will be used are 4 4, 5 5, 6 6, 8 8, 10 10, 12 12, and In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a given matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. Schematic diagram of a flip chip package shown in Figure 11 is used for the analysis. It has a heat sink of attached to the spreader of to the silicon die with the help of TIM I and TIM II with a thickness of Geometry is created using given dimensions for die, spreader, heat sink and TIMs. Die is divided into a matrix of the above mentioned power maps to study the optimization of given power maps as Figure 12 Divided die for various different cases of power maps: (a) 4 4 case, (b) 6 6 case, (c) case, (d) case.

10 142 D. AGONAFER ET AL. Figure 13 Different test cases with (a) functional blocks of 4, 6 and 12 design variables for a 6 6power map, (b) functional block with 16 design variables for a4 4power map [2]. described. A steady-state thermal analysis is carried out to calculate the maximum junction temperature (Tj) for given power maps for both the cases. Mesh sensitivity analysis is carried out with temp varies in the range of ± 1 C; coarse meshing is used for the analysis. Parameters such as thicknesses of TIM I and TIM II, thermal conductivities of TIMs, and convective transfer coefficient are calculated to satisfy the given package conditions. All of the material properties are applied as per the material property data. Total power of 115 W is applied over a dice as per the Figure 14 Temperature profile of the various stacking configurations: (a) rotated stack, (b) staggered stack, (c) spacer stack.

11 D. AGONAFER ET AL. 143 Figure 15 Stack architecture vs. maximum temperature of the four strategies evaluated. (A higher h provides the best performance.) given power maps. An (h) of 1200 W/m 2 Cisused on the top of package for the analysis. This (h) is an effective heat transfer coefficient applied per unit area of the heat sink base (equal to the fin average h times the fin/base area ratio). Once baseline cases for given non-uniform power maps are carried out, an optimization study is carried out to see the effect of non-uniform power on the maximum junction temperature. Percentage variation in the optimized temperature is plotted against baseline temperature. Design guideline will then be suggested for any number of power maps. Tool Ansys Workbench is used for the analysis and optimization study. Figure 12a d shows the divided die for different cases of power maps, such as 4 4, 6 6, 10 10, and Figure 13a and b show the test cases used for optimization for 6 6 and 4 4power maps. RESULTS AND DISCUSSION Thermal Analysis Baseline For the baseline simulation, an effective heat transfer coefficient of 5W/m 2 Cwas applied on top of the mold cap, and the top and bottom surfaces of the PCB. This resulted Figure 16 Stack architecture vs. percentage temperature reduction. in the maximum junction temperature of around 112 C. The baseline simulation temperature profiles of the three architectures (PCB and mold cap are hidden) are shown in Figure 14a c. The temperature contours are from 80 C to 115 C. Higher h Increasing the heat transfer coefficient (h = 20 W/m 2 C), representative of forced convection condition, on top of the mold resulted in a decrease in the maximum temperature by nearly 7% in all the three architectures. Of these, the spacer architecture showed more improvement because the maximum temperature occurs near the top of the mold cap. The higher heat transfer rate on top of the mold cap provides the necessary cooling advantage. It should be noted that in particular systems, like cellular phones, the implementation of forced convection will not be viable from reliability and economic considerations. Increased PCB k Increasing the thermal conductivity of the PCB core thermal conductivity to 0.8 W/m C from 0.18 W/m C results in a Table 4 Result summary for the stack package with spacer die Spacer die configuration, Spacer die configuration, mm mm 2 Data description 3-Die 5-Die 7-Die 3-Die 5-Die 7-Die Ball/substrate solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Ball/PCB solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Model size and run time information Total model nodes Total model elements CPU run time (h)

12 144 D. AGONAFER ET AL. Table 5 Result summary for the stack package with pyramid die configuration Pyramid (square-die configuration) Pyramid (rectangular-die configuration) Data description 3-Die 5-Die 7-Die 3-Die 5-Die 7-Die Ball/substrate solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Ball/PCB solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Model size and run time information Total model nodes Total model elements CPU run time (h) Figure 17 Accumulated plastic work in the solder. reduction of around 3% of the maximum temperature in each of the architectures. This is because majority of the heat generated by the package is dissipated via the PCB to the ambient. Underfill An underfill (k = 0.8 W/m C) was introduced for the solder balls. Using an underfill may be required for improving the solder ball joint reliability. This was evaluated to access its effect on the overall thermal profile of the package. There was no significant decrease in temperature. Cu Spreader Introducing a copper spreader on top of the mold compound resulted in a decrease of 1.2% for the spacer architecture, while it did not improve the performance of the other two architectures. This is because the top die surface is closest to the mold cap-ambient interface in the spacer configuration. The higher Table 6 Result summary for the stack package with rotational die configuration Rotated die configuration Data description 3-Die 5-Die 7-Die Figure 18 Vertical displacement due to thermal cycling. Ball/substrate solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Ball/PCB solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Model size and run time information Total model nodes Total model elements CPU run time (h)

13 D. AGONAFER ET AL. 145 Table 7 Result summary for the stack package with staggered die configuration Staggered die configuration Data description 3-Die 5-Die 7-Die Ball/substrate solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Ball/PCB solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Model size and run time information Total model nodes Total model elements CPU run time (h) thermal conductivity of the copper spreader provides the necessary cooling advantage. Because these packages are used in a cost-competitive market, adding a copper spreader would not be viable economically either. Figure 15 shows the temperature comparison between the three architectures and the five cases evaluated, and Figure 16 shows the temperature reduction percentage for different architectures with different strategies. Thermo-Mechanical Analysis Fatigue Model Results A total of nine package quarter models were created to evaluate corresponding solder joint fatigue effects using three different die configurations for three different types of package geometry. Die stack geometries for different die configurations also varied to see the parametric effect on plastic deformation of the solder joint under accelerated thermal cyclic condition. Accelerated thermal cycling was performed on the modeled CSP using finite element analysis. Temperature variation was from 40 to 125 C with 15 minutes ramps and 15 minutes dwells (one-hour cycle). ANSYS APDL code was used to obtain the stress strain relationship and post-processing information. Quarter symmetry model is used for the FE simulation. Table 9 Result summary for different die thickness, die for die stack with spacer die Spacer die configuration, mm 2 Data description 3-Die 3-Die 3-Die Die thickness Spacer thickness Paste thickness Total mold thickness Ball/substrate solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Ball/PCB solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) To stabilize the plastic work, the number of cycles was varied from two to five cycles. The computer used for running the simulations was an Intel duel core 3GHz processor with 4GB DDR2 RAM. Simulation time varied from two to four hours. After successive thermal load cycles, maximum plastic work/volume information were documented along with the stress strain information for solder ball. Figure 17 shows the accumulated plastic work in the solder joints from the finite element analysis. Figure 18 shows the vertical displacement due to thermal cycling. Vertical displacement varies with different die stacking. Tables 4 7 indicate the detailed simulation results. Fatigue life calculated for substrate and PWB solder joint and also the plastic work accumulated in the solder joint. The number of nodes/elements and CPU run time also added to these tables below. It is seen from Tables 5 and 6 that plastic work increases with the number of die, which indicates risk for a solder joint reliability. As we lower die numbers, which means more mold compound material (higher CTE than die) and a higher package, mean CTE (e.g., higher mold compound CTE) enhances the solder joint reliability. For 3-die and 5-die stacked packages, spacer-die architecture shows better characteristic life over the other two packages. For a 7-die stacked package, rotated-die architecture shows better characteristic life over the other two packages. Table 8 Result summary for different size die stack with spacer die Spacer die configuration mm mm mm mm mm 2 Data description 3-Die 3-Die 3-Die 3-Die 3-Die Ball/substrate solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles) Ball/PCB solder joint Delta plastic work/cycle (MPa) Characteristic life (cycles)

14 146 D. AGONAFER ET AL. Figure 19 Temperature distribution for a 6 6 power map case: (a) original power map, (b) optimized power map. Figure 20 Graph showing power distribution for a 6 6 power map case: (a) original power map, (b) optimized power map. Figure 21 Maximum junction temperatures (base and optimized) for different power maps. heat transfer engineering Figure 22 Percentage variation changes in optimized temperature for different cases of power maps. vol. 29 no

15 D. AGONAFER ET AL. 147 While considering the square die size for spacer and pyramid stack die architecture, simulation results indicate better solder joint performance for the spacer-die stack. Square die provides the best solder joint characteristic fatigue life performance over the rectangle sizes for spacer and pyramid stack die architecture. Table 7 shows little difference in the characteristic life for staggered die configuration. Further studies have been done for the spacer-die architecture by changing the die size and die thickness. Table 8 shows simulation result for three die stack with spacer die by changing the die size. Die size (cross-section) has an impact on solder joint plastic work and the fatigue life. Increasing the die size reduces the joint life of the package with the same mold height and cross-section, as shown in Table 8. Smaller die size increases the fatigue life, as the die edge is further away from the critical solder ball, resulting in less local CTE mismatch [13]. Table 9 shows the simulation result for three stacked spacer die by changing the die thickness of the square size die. Die thickness in stacked packages have a significant effect on fatigue life. Thinner die reduces solder joint performance due to die warpage, which becomes an issue as die gets larger and thinner. Plastic strain accumulation and the worst solder joint location vary with various die stacking configurations. Die stresses in various die stacking configuration also vary, and the worst case is found with the pyramid 7 die stacking. This means that die stacking in stack packages surely has an effect on solder joint reliability and on ball architecture. Non-Uniform Power Distribution Figure 19a and b shows temperature plots for 6 6power maps before and after optimization. Figure 20a and b shows graphical distribution of non-uniform power before and after optimization for 6 6power map case. Figures 21 and 22 show percentage variation changes in optimized temperature for different cases of power maps used in the analysis. Initially, a parametric study and thermal management strategy was conducted on a five-die stacked package, which included both memory and logic processor on the same substrate. Three different configurations (i.e., rotated, staggered, and spacer) were evaluated. Temperature profiles of the overall package were evaluated with a focus on maximum junction temperature. Four different thermal management strategies were assessed from the design and boundary condition point of view. Of the three architectures evaluated, the spacer architecture was the easiest to improve. However, none of the thermal management strategies evaluated offered a significant improvement in performance. This implies that the root cause for the elevated temperature profiles is the high power buildup in the package die stack (i.e., memory and logic dice). The three stack architectures evaluated assume that all the dice are functioning simultaneously the worst case scenario. However, in practice, the various die do not function simultaneously. The degree of functionality of each die, especially the memory die, is determined by the bus architecture. The thermal management strategies evaluated in this paper have demonstrated the significance of system design. Efforts must be concentrated on the system design processes (placement of components on the PCB, bus architecture, etc.) to improve the overall performance of the package. Thus it is clear from the study that thermal issues are not of a concern for low power applications (i.e., lower density interconnects). As shown by thermo-mechanical analysis, mechanical issues have a significant effect on package architecture for low-density interconnects, as shown by the study. In the future, there will be a need to stack logic and other types of devices for high-density interconnect applications. This will be a significant thermal challenge because of the impact of non-uniform power in high-powered micro-architecture. NOMENCLATURE h heat transfer coefficient, W/m 2 C k thermal conductivity, W/m C K crack growth constant P power dissipation, W Q heat flux, W/m 2. R thermal resistance, C/W T temperature, C W i plastic work density Subscripts A J ambient junction CONCLUSIONS REFERENCES [1] Defense Advanced Research Projects Agency, Microsystems Technology Office. [2] Al-sarawi, S. F., Abbott, D., and Franzon, P. D., A Review of 3-D Packaging Technology, Components, Packaging, and Manufacturing Technology, vol. 9, no. 4, pp. 2 14, February [3] Cooling Zone. [4] Kada, M., and Smith, L., Advancements in Stacked Chip Scale Packaging (S-CSP) Provides System in a Package Functionality for Wireless and Handheld Applications, Pan Pacific Microelectronics Symposium, Conference, Meus, Hawaii, January [5] Anand, L., Constitutive Equations for the Rate-Dependent Deformation of Metals at Elevated Temperatures, Trans. ASME J. Eng. Materials Tech., vol. 104, no. 1, pp [6] Akhter, R., Sandur, B. P. D., Hossain, M., Kaisare, A., Agonafer, D., Lawrence, K., Pekin, S., and Dishongh, T., Thermal Comparison of Die Stacking Architectures for Flash Memory Applications,

16 148 D. AGONAFER ET AL. Proceedings of IMECE, HT , Joint Electron Device Engineering Council (JEDEC), San Francisco, CA, USA, [7] Rencz, M., Thermal Issues in Stacked Die Packages, IEEE SEMITHERM Proceedings, PCB Design and SMT Assembly/ Rework Guidelines for MCM-L Packages, Application Notes, pp , Available at: [8] ZipCURE TM Die Attach Adhesive Datasheet. Polysciences, Inc., Warrington, Pennsylvania, USA. Available at: polysciences.com. [9] Pro/E WildFire TM 2.0 Reference Manual.Parametric Technology Corporation, Needham, Massachusetts, USA. [10] Ansys WorkBench TM 10.0 Reference Manual. ANSYS, Inc., Canonsburg, Pennsylvania, USA. [11] Zhan, B. A., Finite Element Based Solder Joint Fatigue Life Predictions for a Same Die Stacked Chip Scale Ball Grid Array Package, Proceedings SEMI Technology Symposium, IEMT Symposium. San Jose, California, 2002, pp [12] Anand, L., Constitutive Equations for the Hot Working of Metals, I, Journal of Plasticity, vol. 1, pp , [13] Darveaux, R., Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction, Journal of E. Packaging, vol. 124, p. 147, Dereje Agonafer after 15 years at IBM, joined the University of Texas at Arlington (UTA) in 1999 as professor and director of the Electronics, MEMS, and Nanoelectronics Systems Packaging Center. He is also the director of the Industrial Assessment Center at UTA. The research at the UTA center is multidisciplinary and focuses on a variety of research related to thermo/mechanical issues in microelectronics, MEMS and nanoelectronics, with broad applications including computers, telecommunications and bio-fluidics. Dr. Agonafor currently advises 16 graduate students, including seven PhDs. Since joining UTA in 1999, he has graduated two Ph.D.s and 43 M.S. students. Professor Agonafer is a fellow of the American Society of Mechanical Engineers International and The American Association for the Advancement of Science. He is currently on a leave of absence at MIT Mechanical Engineering Department. Abhijit D. Kaisare received his bachelor s degree in mechanical engineering from the University of Pune, India, in 1997 and master s degree in mechanical engineering from the University of Texas at Arlington in 2002, where he is currently a Ph.D. candidate in mechanical engineering. He is currently involved in the development of analytical and numerical models for thermalbased optimization for a first-level package with non-uniformly powered micro-architecture. His research interests are in the area of thermal management, mechanical reliability and characterization for electronic packaging, and MEMS applications. Mohammad Masum Hossain received his bachelor s degree from Bangladesh University of Engineering in 1997 and master s degree from South Dakota School of Mines and Technology in He started his Ph.D. with the Electronics, MEMS and Nano Systems Packaging Center at the University of Texas at Arlington and received his degree in His field of research includes lead-free solder material testing and characterization and also mechanical and thermo-mechanical reliability of the lead-free solder interconnect for electronic packaging and MEMS applications. Currently he is working at Intel Corporation as a quality and reliability engineer. Yongje Lee received his bachelor s degree in mechanical engineering from Han-Kuk Aviation University, Korea, and master s degree in mechanical engineering from the University of Texas at Arlington in His research interests are in electronic packaging and electronic cooling system. He is currently working with Samsung Electronics in Korea. Bhavani Prasad Dewan-Sandur received his bachelor s degree in mechanical engineering from RV College of Engineering, Bangalore, India, in 2002 and master s degree in mechanical engineering from the University of Texas at Arlington in His research interests include the design and thermal management of electronic systems/packages, as well as computer architecture and networking. He intends to pursue a career in electronic packaging, electronic thermal management, and computer networking, focusing on system design and research and development. Terrance (Terry) J. Dishongh received his bachelor s and master s degrees from the University Tennessee, Knoxville, and his Ph.D. from the University of Arizona. He is currently the principle engineer and lead technologist in Intel s Digital Health Research and Innovation Group. His current duties at Intel Corporation include projections of technology trends in ubiquitous computing, research and development of sensors for those with cognitive decline, and contextual awareness and design of new radio technology for ubiquitous computing. He has designed, developed, and prototyped various sensors and sensor network using Z-wave, Zigbee, X10, mote based systems and Bluetooth technology. Dr. Dishongh has held faculty positions at the University of Maryland, College Park, and the State University of New York at Buffalo. He has chaired the National Electronic Manufacturers Institution s roadmap for desktop computer systems for the past five years, and for four years he authored the NEMI Healthcare sector roadmap. Senol Pekin received his BSc and MSc from Technical University of Istanbul, Turkey; his Ph.D. from the University of Illinois at Urbana- Champaign; and his MBA from Saint Mary s College. He currently works at Intel Corporation on package architecture and feasibility demonstration. His packaging experience covers ASIC, flash, RF, and CPU products from 130 to 32 nm nodes for communications, mobility, desktop, and server markets. He has lead the development of various technologies, such as selection and qualification of bumping technologies, optimization of flip chip design rules, low-stress 3D die stacking, various substrate technologies, SIP for RF applications, and reduced pitch LGA, PGA, and BGA. Before joining Intel Corporation, he worked at LSI Logic and was an adjunct faculty member at San Jose State University. He generated the data that is still in use in the industry on bump reliability and electromigration.