Fabrication and Characterization of Electrical Interconnects and Microfluidic Cooling for 3D ICS

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1 Heat Transfer Engineering ISSN: (Print) (Online) Journal homepage: Fabrication and Characterization of Electrical Interconnects and Microfluidic Cooling for 3D ICS With Silicon Interposer Hanju Oh, Yue Zhang, Li Zheng, Gary S. May & Muhannad S. Bakir To cite this article: Hanju Oh, Yue Zhang, Li Zheng, Gary S. May & Muhannad S. Bakir (2016): Fabrication and Characterization of Electrical Interconnects and Microfluidic Cooling for 3D ICS With Silicon Interposer, Heat Transfer Engineering, DOI: / To link to this article: Accepted author version posted online: 25 Sep Published online: 14 Jan Submit your article to this journal Article views: 20 View related articles View Crossmark data Full Terms & Conditions of access and use can be found at Download by: [Georgia Tech Library] Date: 02 February 2016, At: 06:11

2 Heat Transfer Engineering, 00(00):1 9, 2016 Copyright C Taylor and Francis Group, LLC ISSN: print / online DOI: / Fabrication and Characterization of Electrical Interconnects and Microfluidic Cooling for 3D ICS With Silicon Interposer HANJU OH, YUE ZHANG, LI ZHENG, GARY S. MAY, and MUHANNAD S. BAKIR School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA Heat generation in high-performance three-dimensional integrated circuits (3D ICs) is a significant challenge due to limited heat removal paths and high power density. To address this challenge, this paper presents an embedded microfluidic heat sink (MFHS) for such high-performance 3D ICs. In the proposed 3D IC system, each tier contains an embedded MFHS, along with high-aspect-ratio (23:1) through-silicon vias (TSVs) routed through the MFHS. In each tier, solder-based electrical and fluidic inputs/outputs are co-fabricated with wafer-level batch fabrication. Moreover, microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. INTRODUCTION Three-dimensional integrated circuit (3D IC) technology has been extensively explored in recent years. By significantly shortening the interconnect length, as well as enabling heterogeneous integration of logic, memory, microelectromechanical systems, and optoelectronics, 3D ICs may reduce system power and footprint and improve performance [1, 2]. However, a key challenge for high-performance 3D applications is the significant amount of power dissipated within the stack. The reason is that both the power density of a 3D stack and the thermal resistance of the dice within the stack increase as the number of tiers increases. The latter is due to the fact that the inner dice do not have direct access to a heat sink (Figure 1a). To address this issue, innovative interlayer microfluidic cooling has been proposed for 3D ICs [3]. Due to advancements in microfabrication, more complex microstructures for improved heat sink performance have been Address correspondence to Hanju Oh, School of Electrical and Computer Engineering, Georgia Institute of Technology, 791 Atlantic Dr. NW, Pettit Bldg., Atlanta, GA 30332, USA. hanju.oh@gatech.edu Color versions of one or more of the figures in the article can be found online at fabricated and may outshine the performance of the plain microchannels proposed in [3]. Examples of more complex microfluidic heat sink structures include enhanced microchannels [5], inline micropin-fins [6], staggered micropin-fins [8 13], and pearl chains [6]. Among the various heat sink designs, the micropin-fin heat sink design has been of interest since it offers a large coolant contact area compared to other heat sink structures. Table 1 summarizes some of the micropin-fin heat sink designs used in the literature along with their performance. However, none of the aforementioned designs take into account the electrical and microfabrication constraints that through-silicon vias (TSVs) impose on microfluidic cooling. Of important consideration is chip thickness: Too thick silicon chips provide thermal resistance and hydraulic pressure drop advantages for the microfluidic heat sink (MFHS) design, but may greatly complicate TSV fabrication and degrade TSV performance (electrical parasitics are a function of length, via aspect ratio, and pitch); too thin silicon chips will greatly ease TSV fabrication and improve the electrical performance, but at the expense of making very short MFHS, which can degrade both thermal resistance (due to smaller convective surface area) and pressure drop (due to smaller hydraulic diameter). As such, the integration of a MFHS may present a number challenges to TSV technology (fabrication and electrical performance). One prior study has demonstrated the integration of TSVs with 1

3 2 H.OH ETAL. Figure 1 Schematics of (a) conventional air-cooled heat sink and (b) the proposed 3D system featuring microfluidic cooling embedded within an interposer package, high-aspect-ratio TSVs, and microbumps for electrical I/Os. micropin-fins [14]. However, that effort demonstrated only a single TSV per micropin-fin due to the large TSV diameter. Given the thickness of silicon dice with embedded microfluidic cooling, high-aspect-ratio (i.e., high height-to-diameter ratio) TSVs become necessary in such 3D ICs. Prior work [15] showed preliminary progress in the integration of multiple TSVs in a microfluidic heat sink; however, the TSVs were not electrically isolated, and were not completely etched through the wafer due to innate difficulty in high-aspect-ratio silicon etching and copper filling in a thick silicon substrate. To address the challenges, this paper presents a 3D IC technology featuring embedded microfluidic cooling, high-aspectratio TSVs, and wafer-level batch fabricated and flip-chip compatible fluidic inlets and outlets (Figure 1b). HIGH-ASPECT RATIO TSVs EMBEDDED IN MICROPIN-FIN HEAT SINK In general, embedding a microfluidic heat sink requires a die to be relatively thick since the height of the heat sink is strongly related to its cooling ability. In previous publications on microfluidic cooling [4 13], a die with an embedded MFHS is several times thicker than the thickness of dice in a 3D stack (based on the International Technology Roadmap for Semiconductors Table 1 Geometry and specification of a micropin-fin heat sink used in the literature projects [16]). This not only degrades electrical performance due to increased electrical parasitics of the TSVs (capacitance), but also limits the number of TSVs between tiers because the aspect ratio of TSVs is typically limited by fabrication. Thus, we seek to develop high-aspect-ratio TSVs to enable their integration within the MFHS and preserve the electrical benefits. In this section, we demonstrate the fabrication of TSVs with 13 μm diameter, 24 μm pitch, and 300 μm height (aspect ratio of 23:1). A four-by-four array of TSVs is integrated in micropin-fins with a diameter of 150 μm and a height of 270 μm. Fabrication Figure 2 summarizes the proposed process flow of TSV and MFHS integration. The fabrication of TSVs within micropinfins begins with a dual-side-polished silicon wafer. Silicon dioxide is deposited and patterned on the wafer as a mask during silicon etching. High-aspect-ratio vias ( 23:1) are etched using the Bosch process. Thermal oxide ( 1 μm) is then grown in a furnace to isolate the subsequent TSVs from the substrate. Titanium and copper are deposited to form a seed layer at the back side of the wafer. Next, using direct current electroplating, via holes are pinched off to form a seed layer for copper via filling. Using this newly formed layer, pulsed bottom-up Literature Heat sink diameter (μm) Heat sink height (μm) Thermal resistance (K/W) Pressure drop (kpa) Peles et al. [9] 100/ Kosar et al. [8] 50/ N/A 80/20 Liu et al. [12] 445/ / /2.6 Brunschwiler et al. [6] 50/100/200 97/ Wan et al. [10] N/A Prasher et al. [13] 55/ / /3 This work / /44.6 Normalized thermal resistance to the 1-cm 2 area. In-line micropin-fin with a pitch of 200 μm and a height of 200 μmataflow rate of 100 ml/min. Round staggered micriopin-fins of RP 1 and RP 3 at a flow rate of 100 ml/min. Fabrication process flow of high-aspect-ratio TSVs within micropin- Figure 2 fins.

4 H. OH ET AL. 3 Figure 3 A4 4 array of the fabricated high-aspect-ratio TSVs: cross-sectional view (left) and top view (right). Figure 4 SEM images of micropin-fins with high-aspect-ratio TSVs: angled view (left) and cross-sectional view (right). electroplating is performed using an Enthone DVF electroplating solution to fill the vias with copper. Over-electroplated copper (on the opposite side of the wafer) is removed using chemical mechanical polishing (CMP). Figure 3 illustrates optical images of fully filled TSVs (cross-section and top views). Following CMP, silicon is etched around the TSVs using the Bosch process to form 150-μm-diameter and 270-μm-tall micropin-fins (these dimensions were chosen based on prior thermal design consideration in which the target thermal resistance and pressure drop are 0.2 K/W and 60 kpa, respectively, at a flow rate of 80 ml/min [17]). The fabricated TSVs are 13 μm indiameter and 300 μm deep. Angled and cross-sectional views of the fabricated TSVs within the micropin-fins are shown in Figure 4. standard deviation. The theoretical TSV resistance is 32.7 m, which matches the experimental results well. ELECTRICAL AND FLUIDIC I/O FABRICATION, ASSEMBLY, AND TEST Fabrication and Assembly The fabrication process for silicon die with electrical and fluidic microbumps and embedded micropin-fin heat sinks is Electrical Measurements The resistance of the fabricated TSVs is measured using the four-point Kelvin technique. For the resistance measurements, gold pads (50 μm 20 μm) are deposited using an e-beam evaporator, as shown in Figure 5. The average resistance value for 61 measurements (Figure 6) is m with 2.72 m Figure 5 Electrical resistance measurements of TSVs using four-point Kelvin technique.

5 4 H.OH ETAL. Figure 6 Electrical resistance measurement results of the TSVs. Figure 7 Fabrication process flow of microbumps with fluidic heat sink. illustrated in Figure 7. As previously noted, the process begins with a dual-side-polished silicon wafer. A silicon dioxide layer of 3 μm is deposited on one side of the wafer using plasma-enhanced chemical vapor deposition. Next, fluidic vias and micropin-fins are etched on the other side of the wafer using two Bosch etch steps. The fluidic vias are etched halfway ( 100 μm deep etch) during the first etch step. In the second etch step, the vias are etched through (additional 200 μm of depth), while simultaneously etching the micropin-fins. Following the silicon etching steps, a titanium/copper (25 nm/250 nm) layer is sputtered on the silicon dioxide as a seed layer for electroplating. Next, copper pads for electrical and fluidic microbumps and fine-pitch interconnects are electroplated, followed by electroplating of nickel and solder on the pads. After electroplating copper, nickel, and solder, the seed layer is removed, and the oxide membrane suspended over the fluidic vias is opened. Figure 8 illustrates the fabricated electrical and fluidic microbumps, micropin-fins, and fluidic vias with dimensions. After fabrication, the silicon die is flip-chip bonded onto a silicon interposer using a flip-chip bonder. Verification by Electrical and Fluidic Tests Following assembly, electrical and fluidic tests are conducted to verify the bonding and the sealing quality. The resistance of a single electrical microbump is measured using the four-point Kelvin technique. Figure 9 illustrates the resistance of eight electrical microbumps. The average resistance is approximately 13.5 m Ω. Next, the sealing quality of the fluidic microbumps is tested. First, the micropin-fin heat sink is capped with a glass cover (to facilitate visual inspection), as shown in Figure 10. Next, manifolds and tubes are attached to the back side of the interposer, and the pressure drop between the inlet and outlet ports is measured. During testing, distilled water is pumped into the die continuously for 4 h at flow rates of 30 and 50 ml/min. Figure 8 SEM images of the fabricated micropin-fins, electrical microbumps, fluidic microbumps, and fluidic vias.

6 H. OH ET AL. 5 Table 2 Die and bonding parameters Parameter Value Die size 1cm 1cm Number of fluidic microbumps 42 (21 each row) Number of electrical microbumps 22,500 ( ) Temperature ramp rate 2 C/s Peak temperature 230 o C Peak temperature duration 15 s Bonding force 7N MICROFLUIDIC TESTING OF A MICROPIN-FIN HEAT SINK WITH EMBEDDED TSVs Figure 9 Electrical resistance measurement results of an electrical microbump. The measured pressure drop at each flow rate is very stable, as shown in Figure 11. No obvious pressure drop change occurs and no leakage was visually observed, which indicates stable fluidic sealing. The bonding profile and die parameters of the assembled test chip are summarized in Table 2. Figure 10 Capping the micropin-fin heat sink and attaching inlet/outlet ports and tubes for fluidic testing. The critical design dimensions of the micropin-fins are shown in Figure 12: Diameter (D), transverse pitch (P t ), and lateral pitch (P l ) are shown, respectively. In our experiments, the micropin-fins are fabricated in a staggered pattern, since this results in improved cooling due to the obstruction to fluidic flow [6]. Figure 13 shows an SEM image of the staggered micropinfin array with a pictorial depiction of fluid flowing across the Figure 12 Layout of the staggered micropin-fin array; diameter (D), transverse pitch (Pt), and lateral pitch (Pl) are shown. Figure 11 Fluidic test results (continuous distilled water pumping for 4 h at flow rates of 30 and 50 ml/min). Figure 13 SEM image of the staggered micropin-fin array with a pictorial depiction of fluid flowing across the array.

7 6 H.OH ETAL. Figure 14 Assembly of the fabricated sample for thermal measurements. fabricated micropin-fins. To emulate chip power dissipation and enable temperature sensing, platinum is used as heaters and as thermometers. Assembly and Calibration The assembly flow of the testbed is shown in Figure 14. First, the TSV-integrated micropin-fin heat sink was capped with a glass wafer using a thin epoxy film (approximately a few micrometers thick). After fabricating the fluidic vias, two external connectors serving as the inlet and outlet for the cooling fluid were connected to the testbed. Figures 15a and 15b show the micropin-fin array (back side) and the fully assembled sample (front side), respectively. In the center of the sample (Figure 14), platinum is patterned as a resistance-temperature Figure 16 The relationship between resistance and temperature of the platinum heater/rtd. detector (RTD) in a spiral shape; this design yields a platinum resistance value of 42 at room temperature. Figure 16 illustrates the calibrated results of the platinum RTD, showing a linear relationship between resistance and temperature. Measurement Setup Figure 17 illustrates a schematic of the microfluidic cooling experimental setup in which the flow rate, pressure drop, and temperature of the testbed are measured as a function of power dissipation. The thermal testbed contains a platinum heater/rtd and is interconnected to a nearby distilled water reservoir using a Cole-Parmer gear pump with ml/rev. A polyester-based filter is connected to the pump outlet to eliminate particles larger than 20 μm, which may block the testbed during experiments. To measure the pressure drop of the testbed, a differential pressure gauge (error of 1 kpa) is connected to the inlet and the outlet of the sample, while the coolant flow rate was measured at the using a KOBOLD acrylic flow meter with an accuracy of 5 ml/min and a measurement range of 10 to 100 ml/min. Inlet and outlet temperature measurements were made at the water reservoirs using J-type thermocouples, which have a Figure 15 The testbed for thermal measurement: (a) the micropin-fin array and (b) the assembled sample. Figure 17 A schematic of the thermal testbed with a microfluidic heat sink.

8 H. OH ET AL. 7 Figure 18 Junction temperature increases as a function of power. temperature accuracy of 1 C. Note that the distilled water flows through the gear pump, the pressure gauge, and a total of 50 cm tube length before reaching the inlet port of the testbed, and thus the actual testbed inlet temperature will increase relative to the reservoir temperature. In addition, an Agilent power analyzer is directly connected to the on-chip platinum heater to apply constant power during testing. To thermally insulate the sample from the ambient, a thick epoxy layer was deposited on top of the heater. Microfluidic Cooling Testing The first step in the thermal measurements is to turn on the gear pump at a fixed flow rate, allowing the distilled water to flow. Next, a small value of power is applied to the platinum heater to generate heat. Meanwhile, since the resistance of the platinum increases linearly with temperature, the heater can serve as a temperature sensor. By detecting the resistance of the platinum heater, the junction temperature of the sample is calculated as T j = T 0 + r(t j) r(t 0 ) (1) α r(t 0 ) where T 0 is the reference temperature, r(t j ) and r(t 0 ) are the resistance of the RTD at temperatures T j and T 0, and α is the temperature coefficient of resistance extracted from the calibration of the RTD. With the measured junction temperature, the total thermal resistance of the micropin-fin heat sink, or R total, can be calculated as ( ) Tj T in R total = (2) P diss where T j is the chip junction temperature, T in is the coolant temperature at an inlet, and P diss is the total dissipated power across the chip [6]. In this experiment, three power levels (25, 50, and 75 W/cm 2 ) are applied at two flow rates, resulting in a total of six thermal measurements. At the maximum power level of 75 W/cm 2, the micropin-fin heat sink yields a junction temperature of 43 C and 40 C with a pressure drop of 28.4 and 44.6 kpa at a flow rate of 60 and 80 ml/min, respectively, as shown in Figure 18. This yields a total thermal resistance of 0.33 and 0.28 K/W using Eq. (2), respectively. The theoretical thermal resistance for each case is calculated using equations proposed in references 15 and 18, and the pressure drop for each case is extracted from ANSYS simulations, as summarized in Table 3. CONCLUSIONS This paper presented novel technology enablers for liquidcooled 3D integration, including a micropin-fin heat sink with high-aspect ratio TSVs, as well as fine-pitch electrical and fluidic microbumps. High-aspect-ratio TSVs (aspect ratio of 23:1) were fabricated within micropin-fins and electrically characterized by four-point Kelvin measurements. Electrical and fluidic microbumps were co-fabricated, assembled, and tested, without fluid leakage. Microfluidic cooling experiments were conducted using the fabricated testbed containing a staggered micropin-fin heat sink with embedded TSVs and distilled water as the coolant. Thermal resistance and pressure drop were experimentally extracted for different flow rates. NOMENCLATURE 3D IC three-dimensional integrated circuit CMP chemical mechanical polishing D diameter of micropin-fins, μm I/O input/output MFHS microfluidic heat sink P diss dissipated power, W P drop pressure drop, kpa Table 3 Results of the thermal experiments P l lateral pitch of micropin-fins, μm P t transverse pitch of micropin-fins, μm 60 ml/min 80 ml/min r resistance of platinum heater, Flow rate Theo./sim. Measured Theo./sim. Measured RTD resistance-temperature detector R total (K/W) R total total thermal resistance, K/W P drop (kpa) T in coolant temperature at an inlet, C α (K 1 ) T j chip junction temperature, C T 0 reference temperature, C

9 8 H.OH ETAL. TSV Greek Symbols through-silicon via α temperature coefficient, K 1 ACKNOWLEDGMENTS This work has been carried out in part under support from Defense Advanced Research Projects Agency (DARPA) contracts N and HR The authors acknowledge Enthone for providing the electroplating solution and Cabot Microelectronics Corporation for providing CMP slurries. We also acknowledge Futurrex for providing the NR photoresist. REFERENCES [1] Souri, S. J., Banerjee, K., Mehrotra, A., and Saraswat, K. C., Multiple Si layer ICs: Motivation, Performance Analysis, and Design Implications, Proc. 37th Annual Design Automation Conf., Los Angeles, CA, June 5 9, pp , [2] Banerjee, K., Souri, S. J., Kapur, P., and Saraswat, K. C., 3-D ICs: A Novel Chip Design for Improving Deep- Submicrometer Interconnect Performance and Systemson-Chip Integration, Proc. of the IEEE, vol. 89, no. 5, pp , [3] Tuckerman, D. B., and Pease, R. F. W., High-Performance Heat Sinking for VLSI, IEEE Electronic Device Letters, vol. 2, pp , [4] Bakir, M., King, C., Sekar, D., Thacker, H., Dang, B., Huang, G., Naeemi, A., and Meindl, J. D., 3D Heterogeneous Integrated Systems: Liquid Cooling, Power Delivery, and Implementation, Proc. Custom Integrated Circuits Conf., San Jose, CA, September 21 24, pp , [5] Steinke, M. E., and Kandlikar, S. G., Single-Phase Liquid Heat Transfer in Plain and Enhanced Microchannels, Proc. International Conference on Nanochannels, Microchannels and Minichannels, pp. 1 9, Limerick, Ireland, June 19-21, [6] Brunschwiler, T., Michel, B., Rothuizen, H., Kloter, U., Wunderle, B., Oppermann, H., and Reichl, H., Interlayer Cooling Potential in Vertically Integrated Packages, Microsystem Technologies, vol. 15, pp , [7] Ndao, S., Peles, Y., and Jensen, M., Multi-Objective Thermal Design Optimization and Comparative Analysis of Electronics Cooling Technologies, International Journal of Heat and Mass Transfer, vol. 52, issues 19 20, pp , [8] Kosar, A., Mishra, C., and Peles, Y., Laminar Flow Across a Bank of Low Aspect Ratio Micro Pin Fins, Journal of Fluids Engineering, vol. 127, pp , [9] Peles, Y., Koşar, A., Mishra, C., Kuo, C.-J., and Schneider, B., Forced Convective Heat Transfer Across a Pin Fin Micro Heat Sink, International Journal of Heat and Mass Transfer, vol. 48, no. 17, pp , [10] Wan, Z., Yueh, W., Joshi, Y., and Mukhopadhyay, S., Enhancement in CMOS Chip Performance Through Microfluidic Cooling, Proc. 20th International Workshop on Thermal Investigations of ICs and Systems, vol. 2014, no. 2, pp. 1 5, Greenwich, London, UK, September 24 26, [11] Tullius, J. F., Tullius, T. K., and Bayazitoglu, Y., Optimization of Short Micro Pin Fins in Minichannels, International Journal of Heat and Mass Transfer, vol. 55, no , pp , [12] Liu, M., Liu, D., Xu, S., and Chen, Y., Experimental Study on Liquid Flow and Heat Transfer in Micro Square Pin Fin Heat Sink, International Journal of Heat and Mass Transfer, vol. 54, no , pp , Dec [13] Prasher, R. S., Dirner, J., Chang, J.-Y., Myers, A., Chau, D., He, D., and Prstic, S., Nusselt Number and Friction Factor of Staggered Arrays of Low Aspect Ratio Micropin-Fins Under Cross Flow for Water as Fluid, Journal of Heat Transfer, vol. 129, no. 2, pp. 141, [14] Madhour, Y., Zervas, M., Schlottig, G., Brunschwiler, T., Leblebici, Y., Thome, J. R., and Michel, B., Integration of Intra Chip Stack Fluidic Cooling Using Thin-Layer Solder Bonding, Proc. Int. 3D Syst. Integr. Conf., pp. 1 8, San Francisco, CA, October 2 4, [15] Zhang, Y., Dembla, A., and Bakir, M. S., Silicon Micropin- Fin Heat Sink With Integrated TSVs for 3-D ICs: Tradeoff Analysis and Experimental Testing, IEEE Trans. Components, Packag. Manuf. Technol., vol. 3, no. 11, pp , [16] International Technology Roadmap for Semiconductors, 2012, [17] Zhang, Y., Zheng, L., and Bakir, M. S., 3-D Stacked Tier- Specific Microfluidic Cooling for Heterogeneous 3-D ICs, IEEE Trans. Components, Packag. Manuf. Technol., vol. 3, no. 11, pp , November [18] Zhukauskas, A. A., Heat Transfer From Tubes in Cross Flow, Advances in Heat Transfer, vol. 8, no. 1, pp , Hanju Oh received the B.S. degree in electrical and computer engineering from Hanyang University, Seoul, Korea, in 2010 and the M.S. degree from the Georgia Institute of Technology, Atlanta, GA, in He is currently pursuing his Ph.D. degree in electrical and computer engineering at the Georgia Institute of Technology, Atlanta, GA.

10 H. OH ET AL. 9 Yue Zhang received the B.S. degree in electrical engineering and automation from Harbin Institute of Technology, China, and from University of Science and Technology of Lille, France, in 2007, and the M.S. degree in micro- and nanotechnology from University of Science and Technology of Lille, France, in She is currently pursuing her Ph.D. degree in electrical engineering at the Georgia Institute of Technology, Atlanta, GA. Li Zheng received the B.S. degree from Zhejiang University, Hangzhou, China, in 2006, and dual M.S. degree in electrical and computer engineering from Shanghai Jiao Tong University, Shanghai, China, and Georgia Institute of Technology, Atlanta, GA, in He is currently pursuing his Ph.D. degree in electrical and computer engineering at the Georgia Institute of Technology. His research interests include embedded microfluidic cooling, power delivery modeling, and chip-to-chip signaling modeling for highperformance silicon interposers and 3D integrated systems. Gary S. May received the B.S. degree in electrical engineering from the Georgia Institute of Technology in 1985 and the M.S. and Ph.D. degrees in electrical engineering and computer science from the University of California at Berkeley in 1987 and 1991, respectively. He is currently Dean of the College of Engineering at Georgia Tech. In that capacity, he serves as the chief academic officer of the college and provides leadership to more than 400 faculty members and more than 13,000 students in the fourth-ranked engineering program in the nation. Prior to his current appointment, he was the Steve W. Chaddick School Chair of the School of Electrical and Computer Engineering at Georgia Tech from His research is in the field of computer-aided manufacturing of integrated circuits, and his interests include semiconductor process and equipment modeling, process simulation and control, automated process and equipment diagnosis, and yield modeling. Dr. May was editor-in-chief of IEEE Transactions on Semiconductor Manufacturing during and was a National Science Foundation National Young Investigator ( ). He was a National Science Foundation and an AT&T Bell Laboratories graduate fellow, and has worked as a member of the technical staff at AT&T Bell Laboratories in Murray Hill, NJ. He is an IEEE fellow, as well as a fellow of the American Association for the Advancement of Science and a member of the National Advisory Board of the National Society of Black Engineers (NSBE). Muhannad S. Bakir received the B.E.E. degree (summa cum laude) from Auburn University, Auburn, AL, in 1999 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology (Georgia Tech) in 2000 and 2003, respectively. He is currently an associate professor and the ON Semiconductor Junior Professor in the School of Electrical and Computer Engineering at Georgia Tech. Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, and 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. He is also a recipient of the Semiconductor Research Corporation (SRC) Inventor Recognition Awards (2002, 2005, 2009). He and his research group have received 14 conference and student paper awards, including five from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir is an editor of IEEE Transactions on Electron Devices, an associate editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and was a guest editor of the June 2011 special issue of IEEE Journal of Selected Topics in Quantum Electronics. He is also a member of the International Technology Roadmap for Semiconductors (ITRS) technical working group for Assembly and Packaging (AP).