Solid circuits. A. Schmitz

Transcription

1 192, PHILIPS TECHNICAL REVIEW VOLUME 27 Solid circuits A. Schmitz :548 This article deals with integrated circuits who~e elements, both active and passive, are incorporated in a single crystal of silicon by forming zones of P-type and N-type silicon in the crystal at certain places and in a certain sequence. Such circuits are therefore referred to as solid or monolithic circuits, as distinct from integrated circuits made by evaporating thin films on to a substrate (thin-film circuits, see the preceding article [IJ). The P-type and N-type zones are formed by a diffusion process: the crystal is heated in an atmosphere. containing the substance to be incorporated (donors or acceptors), which then diffuses into the crystal. The diffusion is confined to previously determined places by masking the rest of the surface with a layer of silicon dioxide. By subjecting a crystal to successive operations of this kind, various circuit elements can be generated in it. These elements are interconnected to form a more or less complete electronic circuit by means of contacts and conducting strips all in one plane on the Si02. Hence the name "planar technique" commonly used for this method. The volume of these circuits can be kept exceptionally small. The circuits discussed in this article are made from a crystal slice or wafer about 200!Lmthick, covering an area of less than 1 mm". The various elements that can be made in this way are diodes, transistors, resistors and capacitors. Inductors cannot be made by this technique; if in a solid circuit application an inductive impedance is required, some other means of providing it must be found. After some general introductory remarks on the processes employed, we shall discuss the method of manufacture and the characteristic features of the elements in a solid circuit. A few examples of solid circuits made in this way will be described.. "The masking and diffusion process The starting point is always a single crystal consisting of a wafer of N-type silicon. As mentioned, the thickness is of the order of 200!Lm. The wafer-is first coated with the maskinglayer of silicon dioxide by heating it to about 1150 C in an oxidizing atmosphere. Oxygen might be thought to be the obvious oxidizing agent, but experience has shown that the oxidation process goes much faster when steam is used. An oxide film' from: 0.4 to 0:6!Lmthick, which is sufficient to mask the crystal surface in the diffusion process, can be formed in about half an hour at 1150 C in steam; if oxygen Drs. A'. Schmitz is with Philips Research Laboratories, Eindhoven. were used it would take about eight hours. In jig. 1,' which illustrates the various stages in the process, the result of this initial operation is represented by a. Openings are introduced in the appropriate places in the oxide layer by means of a photo-etching process; the wafer is therefore coated with a photosensitive lacquer after oxidation (fig. lb). This lacquer has the property that on exposure to light it ceases to be soluble in a particular solvent. An exposure of the lacquer film is ' made with a mask which transmits light to,all places where diffusion is not wanted, and the unexposed areas of lacquer are dissolved away (fig. Ie), Next, the remaining lacquer film is hardened, and it is then used as a mask, for etching the required openings into the Si0 2 layer (fig. Id). After this, the remaining layer of lacquer, which is of no further use, is removed by chemical agents. The wafer is then cleaned. In order to set up zones of P-type silicon in the N- type crystal, the wafer is heated to about 1170 C in an atmosphere containing boron. At the places where there is no Si02 the boron then diffuses into the N-type silicon, forming zones of P-type silicon (fig. le). By again subjecting the wafer to oxidation, the zones are sealed off with a layer of Si02 (fig. If). The thickness of the oxide layers is of the same order of magnitude as the wavelength of light, and beautiful interference effects can be observed. These can be put to good use, for since the first and the later formed layers are not equally thick, the zones of P-type silicon remain clearly distinguishable (see fig. 12b and fig. 13b). By repeating the photo-etching process an N-type layer can in turn be produced in the P-type silicon now formed. Contacts can then be applied to the various layers so as to obtain the required circuit elements. These elements will be reviewèd in turn below. The manufacture Diodes of various circuit elements, A zone of P-type silicon obtained as described and the encircling N-type material form a diode. To make' a connection to the P-type material an opening is etched into the Si02 layer covering it (see, fig. 1/). It is necessary to proceed here very carefully; the places where the P-N junction reaches the surface of the crystal must not be affected by the etching process. The contact is then applied by evaporating aluminium on to the surface. The aluminium is deposited over the whole surface of the wafer, and is later removed at the

2 1966, No. 7 SOLID CIRCUITS 193 ;..' N N Q L lacquer -P-Si N-Si Fig. I. Schematic representation of various steps in making an integrated circuit by the planar technique, the processes being oxidation, masking and diffusion (the diagrams are not to scale). a) A silicon dioxide film is formed by oxidation on a crystal wafer of N-type silicon. b) A coating of photosensitive lacquer is applied. c) An opening is etched into the coating of lacquer by a photolithographic process. d) The oxide underlayer is etched away. e) The remaining lacquer film is removed by chemical agents, after which the wafer is heated in an atmosphere containing boron. This diffuses into the crystal to form a zone of P-type silicon. f) The opening in the SÎ02 layer is sealed off by a further oxidation process. places where it is not required, again by a photo-etching process. If only a diode is required, the connection to the N-type silicon is made by alloying the crystal wafer to a gold-plated underlayer. If, however, the diode is part of an integrated circuit, it usually has to be completely insulated from its surroundings, as will be discussed later. In this case a contact has to be applied to the upper side of the N-type silicon as well. Since aluminium does not form an ohmic contact [2] with N-type silicon that contains the quantity of donors necessary for diode operation, a zone first has to be formed which has a higher donor content (N+ material). With this the aluminium does form an ohmic contact. The required connection is then made at the same time as that to the P-type material, by the evaporation of aluminium. The result is represented in fig. 2. P-Si N-Si N+-Si Al Fig.2. Manufacture of a diode. A hole is etched in the Si02 layer formed on the P-type silicon (see fig. If), and aluminium is then deposited by evaporation to make a connection. In an integrated circuit the other diode connection is formed on the upper side of the original crystal, after first depositing a layer of N+ silicon. a Resistors A zone of P-type material which is reverse-biased with respect to the N-type material around it can be considered to be insulated from its surroundings. In this material Ohm's law applies, and the resistivity is such that useful values of resistance can be obtained with practical dimensions. The openings in the oxide layer for making the connections are again introduced by the photo-etching process described above. Fig. 3 shows such a resistance in cross-section and seen from above. For the P-N junction to act as an insulator the whole resistor must thus be given a negative potential with respect to the surrounding N-type material. - -P-Si N-Si AI Fig. 3. Cross-section (a) and plan view (b) of a resistor formed by a layer of P-type silicon. The whole resistor must have a negative potential with respect to the surrounding N-type material. [1] E. C. Munk and A. Rademakers, Integrated circuits with evaporated thin films, Philips tech. Rev. 27, , [2] By an "ohmic" contact we mean a contact that passes current linearly in both directions, i.e. has no rectifying action. b

3 194 PHILlPS TECHNICAL REVIEW VOLUME 27 In the design of solid circuits it is necessary to bear in mind that resistors made in this way show a fairly considerable spread in value. Although the resistors in a single circuit can be produced with an accuracy of about 5 %, the differences between different circuits may be as high as 20 %. The designer of a solid circuit therefore has to allow for the use of resistors with a very large tolerance. Other limitations arise because the resistivity of semiconductors has a high temperature coefficient (about 2 X 1O-3;oQ and because it is difficult to make resistors with values greater than 30 to 50 kq by this technique. The area taken up by such resistors is so large that the chance of an irregularity in the crystal at the location of the resistor is considerable (see also page 196). Finally, it should be noted that a P-N junction has a certain capacitance, so that it is not really a pure resistance but a combination of resistance and capacitance (fig. 4). This sets an upper limit to the frequency range in which a resistance formed by this technique can be considered as a substantially pure resistance. Capacitors Fig. 4. Equivalent circuit of a resistor produced by diffusion in a crystal. there are acceptors in the base (N+ material), is then covered with another film of Si02 (fig.6b). We now have an N-P-N transistor in which the original crystal wafer serves as the collector. The connections to emitter and base are again made by etching openings into the oxide layer and depositing aluminium. The collector connection can be made in two ways. A separate transistor, like a separate diode, is made by alloying the crystal wafer to a gold-plated underlayer. In an integrated circuit, however, a connection to the collector almost invariably has to be made on the upper face. This again makes it necessary to form a zone of N+type material (fig. 6c). This can be formed at the same time as the emitter. It is very difficult to use this method to make both N-P-N and P-N-P transistors in a single crystal wafer. It is, however, possible to obtain a P-N-P transistor by forming two layers of P-type material next to one another, although such a transistor has a very low current amplification factor. Such a transistor can nevertheless be combined with an N-P-N transistor, to produce a circuit which in many ways corresponds to a P-N-P transistor with a high current amplification factor [3]. Other elements Various other circuit elements can be made by the planar technique we have described. An example is given in fig. 7, which shows a field-effect transistor [4] Because a P-N junction has a certain capacitance, it can also be used as a capacitor when biased in the reverse direction. This approach allows capacitors with values up to 200 pf to be made with an accuracy of 3 to 5 %. A difficulty with this kind of capacitor is that the thickness of the barrier layer, and hence the capacitance as well, is not constant but depends on the applied voltage. Moreover, the equivalent impedance of a P-N junction is not a pure capacitance but a combination of capacitance with a series and a parallel re- Q sistance (fig. 5). The applications of these capacitors are therefore limited. Fig. 5. Equivalent circuit of a capacitor formed by a P-N junction. Transistors A transistor is made by introducing a layer of N-type silicon into a layer of P-type silicon formed in the manner illustrated in fig. 1. This is done by first etching away, as described, some of the oxide layer covering the P-type silicon (fig.6a), after which the crystal wafer is heated in an atmosphere containing phosphorus. The resulting N-type silicon, which, to function properly as an emitter, must contain more donors than Fig. 6. Manufacture of an N-P-N transistor. a) Openings are etched into the Si02 layer sealing off the P-type silicon (see fig. IJ) and above the N-type silicon. b) Layers of N+ silicon are formed under these openings by diffusion. The whole surface is then sealed off again by oxidation. c) After once more etching holes into the Si02layer, connections are made to the emitter (E), base (B) and collector (C).

4 1966, No. 7 SOLID CIRCUITS 195 in cross-section and seen from above. Here again, successive layers of Pand N+ semicondu ctor are formed in a wafer of N-type silicon. The last layer formed is now, however, made long enough in one direction for it to make contact with the original crystal, while two connections are applied to the P-type material, one on each side of the N+ layer. The current through the P- type layer can now be controlled by the voltage between the N-type and P-type material. N Other elements that can be made by the planar technique are N-P-N-P rectifiers (silicon controlled rectifiers, thyristors) and elements in which a layer of silicon dioxide acts as dielectric. These include MOS capacitors (MOS = metal-oxide semiconductor) and MOS transistors (MOST devices). Insulation of circuit elements from each other When several circuit elements have been introduced in a crystal wafer by the method described, they all have an N-type layer in common; i.e. they are connected to one pole. In nearly all circuits, however, the elements have to be completely insulated from each other. This can be done by means of an extra P-N junction, using a procedure illustrated infig. 8. Instead of starting from g a wafer of N-type silicon, we now start from a singlecrystal layer of N-type material which is grown epitaxially on a crystal of P-type silicon. Again, a silicon dioxide film is formed on this layer and a pattern of channels is etched following lines where an insulating separation is required (fig. 8a). P-type silicon is now b formed along these lines by diffusion. The diffusion process is continued until the newly-formed P-type material extends to the original P-type crystal. After the diffusion the channel pattern is once again sealed off by a layer of SiOz (fig. 8b). The N-type silicon now forms a number of "islands" in the P-type material, and the islands can be insulated from each other by applying f a reverse voltage between the P- and N-type silicon. (This insulation has a fairly high capacitance.) The processes described above can be used to make a circuit element in each of these islands. Fig. 8c shows a cross-section of an N-P-N transistor formed in this way. The collector connection was made by the method described above. A transistor made by this technique has several special features which have to be taken into account in application. In the first place, the collector-series resistance is fairly high. This is because the epitaxial N-type layer from which the collector is formed is [3] See H. C. Lin, T. B. Tan, G. Y. Chang, B. van der Leest and N. Formigoni, Lateral complementary transistor structure for the simultaneous fabrication of functional blocks, Proc. IEEE 52, ,1964. [4] The field-effect transistor and its operation are described in the next article in this number: H. C. de Graaff and H. Koelmans, The thin-film transistor, Philips tech. Rev. 27, , Q2J. Si02 P-Si N-Si N+-Si AI Fig. 7. Cross-section (a) and plan view (b) of a field-effect transistor. A layer of N+ silicon is formed on the strip of P-type silicon, which has two connections. The N+ silicon strip is long enough to connect with the N-type silicon of the underlayer. - - Si02 P-Si N-Si N+-Si AI - 1/ ;+<;1 Fig. 8. Insulation of elements in a solid circuit. a) An epitaxial N-type layer is formed on a substrate of P-type silicon. The N-type layer is covered with a layer of Si02 by oxidation. A pattern of lines is etched into the Si02 layer by the method previously described. b) P-type silicon, penetrating to the substrate, is produced along the lines of the pattern by diffusion. This results in "islands" of N-type silicon, which, when a voltage is applied in the reverse direction, can be insulated from the surrounding P-type silicon. c) Formation of a transistor which is insulated from the other elements in the circuit. In the island of N-type silicon, which acts as collector, a layer of P-type silicon is formed, the base. In this a layer of N+ silicon is formed, the emitter. To make a connection to the N-type materialof the collector, a layer of N+ silicon is formed in it at the same time as the emitter. The connections to emitter, base and collector, which are produced by the evaporation of aluminium, are indicated by E, Band C.

5 196 PHILlPS TECHNICAL REVIEW VOLUME 27 extremely thin: it is about 10 urn thick. The actual collector region, situated under the base (see fig. 8c), is even thinner, about 7 [Lm. Because of the high collector series resistance the knee voltage is always greater than tbat of transistors made by "normal" methods. It is therefore difficult to use the planar technique in this integrated form to produce transistors of high efficiency and relatively high power output. The collector resistance can be reduced and the knee voltage lowered if a layer of N+ material (the "buried layer", see fig. 9) is formed in the P-type silicon before the first operation, i.e. the growth of the epitaxial N- type layer on the P-type silicon. The buried layer, which has a higher conductivity than the N-type silicon, is thus situated under the N-type materialof the collector and can appreciably reduce the collector resistance. Anotber feature of transistors of this type is that, because of the presence of several regions of P- and N-type material, transistor characteristics other than those P-Si N-Si N+-Si AI Fig. 9. The collector resistance can be reduced by means of a layer of N+ silicon under the N-type silicon of the collector. the desired transistor may be found. For example, the base, the collector and the underlayer of P-type material constitute a P-N-P transistor, the base being formed by the collector of the desired transistor. Since this "b ase" is thicker than that of a normal transistor, the amplification factor of such a P-N-P transistor is fairly low (e.g. 4 to 5). Nevertheless, this may give rise to unwanted effects in some circuits, and preventive measures have to be taken. Finally, we would point out that in the process described a combination of four layers of silicon is formed (emitter, base, collector and underlayer), and that these are alternately N-type and P-type. Such a combination may show characteristics comparable to those of a thyristor. Any unwanted effects arising through this can nearly always be avoided by giving the voltages between the layers an appropriate polarity. Another method of insulating the elements from each other consists in etching grooves into a crystal wafer and providing an insulating Si02 layer by oxidation. The manufacture of such circuits, known as "Epitaxial Passivated and Isolated Integrated Circuits" (EPIC), however involves considerable difficulties. Production of large numbers of circuits In the foregoing we have considered the method of manufacture for a single solid circuit. An economically acceptable production yield is possible with this rather laborious technique as a large number of circuits can be made simultaneouslyon a single wafer of silicon. Hundreds of similar circuits can be made on a wafer of 2.5 cm diameter. For a single circuit, greatly magnified drawings (200 times) are first made of the masks to be used in all successive operations. These drawings are photographically reduced in two steps and the final mask is obtained by repeating the last photographically reduced drawing many times on a single negative. To make sure that the masks used in the successive processes exactly cover the appropriate parts ofthe crystal, the printing has to be done with extremely high precision. The maximum permissible deviation is of the order of 1 [Lm. Limitations of the planar technique Slight imperfections in the crystal may give rise to impermissible deviations in the leakage current or reverse breakdown voltage of one or more of the diffused P-N junctions. The probability that such a crystal defect will be encountered in a circuit increases with the area occupied by the circuit. In a number of simultaneously manufactured solid circuits the percentage of rejects therefore increases with the area ofthe individual circuit. It is thus also desirable for reasons other than that of microminiaturization to keep the size of the circuit as small as possible. The need for small dimensions also sets a limit to the number of elements that can be incorporated in a circuit and also to the maximum values of the resistances and capacitances. We have already mentioned a maximum resistance of 50 kd and a maximum capacitance of 200 pf. Another cause of faults which is also closely bound up with the small dimensions may be the presence of dust during masking operations on the crystal. These should therefore be carried out in a dust-free room. Since, in a number of simultaneously produced solid circuits, the percentage of rejects due to faulty operation increases with the area of the circuit, the costs involved in incorporating an element are determined more by the area occupied than by the type and the required characteristics of the element. For example, a 10 kd resistor, which takes up nearly as much space as 5 or 6 transistors, is 5 to 6 times more expensive than a transistor. A rule that nearly always applies in the economical design of other kinds of circuit, namely that resistors are much cheaper than transistors, thus ceases to apply in solid circuits. It may be advantageous to design these circuits in such a way that relatively few

6 1966, No. 7 SOLID CIRCUITS 197 large resistances are needed; there is much less objection to the use of more transistors than in a conventional circuit. For completeness we shall mention some ofthe factors that limit the realization of some of the requirements that may be asked of solid circuits: the high temperature coefficient of the resistors, the high capacitance between elements insulated from each other, the variation of capacitance with voltage, the large collector series resistance of the transistors and the fact that inductors cannot be formed in a solid circuit. Some of the resultant problems can be overcome by combining monolithic and thin-film techniques. If the resistors are not formed by diffusion in the crystal but by metal films evaporated on top ofthe oxidelayer, then the temperature coefficient of the resistors is much smaller. This brings us to a combination of diffusion technique and thin-film technique, and the "hybrid circuits" thus produced have been mentioned in reference [1] (page 191). Assembly The form in which a solid circuit is supplied depends on how it is to be mounted in the equipment in which it is to be used. A method still widely used is to mount the circuit in a holder of the same dimensions as those Fig. ID. Two mounting methods for solid circuits. Left, transistor mount TO 5, right "flat package". (a "flat package"). The total volume of this arrangement is smaller, about 0.05 cm". Both forms of assembly are shown in fig. JO. In view of the small dimensions, high precision is also required in making the connections between a solid circuit and the connecting wires. The material generally used for these connections is gold: the procedure is illustrated in fig. 11. After all connectors have been fitted, the holder is hermetically sealed in a dry nitrogen atmosphere. G K K g b Fig. 11. Making the connections between a solid circuit and the connections to the mount. a) There is a 20 [1.m gold wire G inside the capillary tube C. b) By means of a hydrogen flame, a ball is formed at the end of the gold wire (diameter roughly 75 [1.m). c) A connection is made between the gold wire and the contact by pressing it on to the contact K of the solid circuit, which is heated to 320 De. d) The capillary tube is raised, releasing the gold wire. The tube is then pressed down again and connection is made with the contacts P in the assembly mount, which is heated as well. e) After the capillary tube is raised, the gold wire is melted in two, producing a ball again at both ends. The ball formed on the contact pin P can be removed if necessary. used for transistors (type TO 5). This means, of course, that full advantage is no longer taken of the extremely small volume of a solid circuit (e.g mm"). After assembly the space thus occupied may be as much as 0.3 cm", which is more than 1000x as large, without taking into account the space needed for the connectors. In another method of assembly the solid circuit is fixed in a flat holder fitted with connectors at both ends Examples of solid circuits Figures 12 and 13 show two solid circuits as examples of the technique we have been discussing. Fig. J 2 gives the circuit diagram and an enlarged photograph of an amplifier (with two transistors, one diode and four resistors) which has strong negative feedback to produce an accurately defined gain (operational amplifier). The location of the various compo-

7 198 PHILlPS TECHNICAL REVIEW VOLUME 27 a I r ,, ~ r ,, I j I I :: : : c=:==j : : I,ox )J}~::(fnH : I I I, 0 t I,. :: ~ 0: GD TrI i! tel Tr2,. DO!, ", :: I I'-- ; I1 I. J I'-- JI c r r------o2 t-----o3 Fig. 12. Operational amp lifter with two transistors, a diode and four resistors, produced as a solid circuit. a) Photograph, b) circuit diagram, c) diagram indicating the location of the elements. The dark double lines in the photograph are the insulating partitions between the various components (P-type material, see fig. 8). The light areas are the evaporated aluminium connections between the elements. The connection terminals are denoted in the diagram and the location diagram by the same numbers. The true dimensions of the crystal wafer are I x I mm. o b Fig.13a Fig. 13. Photograph (a) and circuit diagram (b) of a shift register for a computer. The circuit contains 17 transistors and IS resistors. Here again the dark lines are the insulating partitions between the elements and the light areas are the connections between them. Connections are indicated by the same numbers on the diagram and the photograph. In the lower right-hand corner of the crystal wafer (l x I mm) is a monitoring transistor, which is used for checking the diffusion process.

8 1966, No. 7 SOLID CIRCUITS '199. Fig. 13b nents in the diagram is indicated in the diagram of fig. 12c. To illustrate the fact that more elaborate circuits can be produced in solid form, fig. 13 shows the circuit diagram and a photograph of a shift register for a computer. This circuit contains 17 transistors and 15 resistors, and, like the previous one, is contained on a crystal wafer with a surface area of I mmê. The area occupied by the circuit itself is of course even smaller. Summary. Solid circuits are integrated circuits in which both the active and the passive elements are formed in a silicon crystal. This is done by subjecting a silicon wafer to a succession of masking and diffusion processes to form alternate zones of P-type or N-type (or N+) silicon. The article describes how diodes, resistors, capacitors and transistors are made by these processes. The circuits thus formed have extremely small dimensions, i.é. less than 1 x 1 mm. Reverse-biased P-N junctions can be used to provide insulation between the various elements. An economically acceptable production yield is made possible by the fact that large numbers of circuits can be made simultaneouslyon a single crystal wafer. Various limitations are mentioned which affect the design of solid circuits. Finally, two methods of assembly are described, and examples of typical solid circuits are given