ETCHING OF SILICON NITRIDE WITH HIGH TEMPERATURE WATER AND DEUTERIUM OXIDE

Size: px
Start display at page:

Download "ETCHING OF SILICON NITRIDE WITH HIGH TEMPERATURE WATER AND DEUTERIUM OXIDE"

Transcription

1 ETCHING OF SILICON NITRIDE WITH HIGH TEMPERATURE WATER AND DEUTERIUM OXIDE Joshua Barclay, Jesse Smith, Rick Reidy Department of Materials Science and Engineering University of North Texas, Denton TX (979)

2 Outline Rationale Deuterium oxide Dissociation of water and D 2 O Experimental conditions Results Ellipsometry SEM Molybdate blue UV-Vis (dissolved silica) ATR D 2 O post etch liquid Etch rate comparison Summary Future work

3 Rationale SiN is commonly etched using 160 C (85%) H 3 PO 4 --it is widely believed that the principal etchant is water At this temperature, surface Si-N are protonated followed by water attack creating Si-OH (soluble groups)* Previous work showed high temperature water (HTW) is an effective etchant for SiN Compare HTW and HT deuterium oxide (HTD 2 O) to understand the etching mechanism Because dissociation of D 2 O is 10x less than H 2 O *Martin Knotter, Handbook for Cleaning for Semiconductor Manufacturing: Fundamentals and Applications, Chapter 3, Scrivener, 2011

4 Deuterium Oxide (D2O) H 2 O D 2 O N + + N N N N N + + N N N N g/mol Boiling Point 100 C Vapor Pressure 23.8 torr g/mol Boiling Point C Vapor Pressure 20.6 torr

5 Dissociation pk w H2O D2O D2O estimated Temperature ( C) H 2 O 140 C pk w =11.71 D 2 O 140 C pk w =12.56 H 2 O 160 C pk w =11.53 D 2 O 160 C pk w =12.35 Order of magnitude difference in reactive specie concentration between H 2 O and D 2 O AV Bandura, AN Lvov, J. Phys and Chem Ref Data 35 (1) 15 30, 2006 DW Shoesmith, W Lee, Can J. Chem, 54, , 1976

6 Experimental Conditions 30ml water and D 2 O Heated to 140, 160 C ramp time: 120 mins Hold times of 0,10,20 min at temp 3 samples for each condition P equil, H 2 O (140 C) = 3.5 atm P equil, H 2 O (160 C) = 6.1 atm Reactor is quickly cooled with water Post etch water is collected for characterization 140/160 C SiN

7 Post Etch Thickness (Å) Thickness Losses DI Ellipsometry Results D2O Samples Etch Rate (Å /min ) D 2 O 140 C 24±8 D 2 O 160 C 30±8 DI 140 C 25±12 DI 160 C 45±9 HTW and HTD 2 O remove same amount of material HTW etches slightly faster at 160 C Etching more dependent on temperature than reactive species concentration

8 SEM 140 C D 2 O 140 C 0 min 20 min Di 140 C 0 min 20 min 310nm 275nm 315nm 270nm SEM images of 140 C samples agree with ellipsometry results Given the dissociation behavior, expected HTW to etch more (faster) than D 2 O

9 log Absorbance (%) Thickness Loss vs Dissolved SiO 2 Molybdate Blue UV-Vis C 160C 0 min 10 min 20 min 0 20 min min 10 min Thickness loss (Å) Increasing dissolved silica concentration with increased etching Molybdate blue method did not work in D 2 O need a different method

10 Absorbance a.u. Absorbance a.u. Absorbance a.u. ATR Post 160 C Etch D 2 O N-H O-D 0 min 10 min 20 min D2O D-O-H Wavenumber cm -1 D-O-D D-O-H 1450 Wavenumber cm N-H N-H: Ammonia formed during reaction D-O-H: Exchange of dissociated D 2 O with surface OH Wavenumber cm

11 Etch Rate Comparison Samples Etch Rate (Å /min) Nitride D 2 O 140 C 24±8 Nitride D 2 O 160 C 30±8 Nitride DI 140 C 25±12 Nitride DI 160 C 45±9 TOX DI 140 C 18±3 TOX DI 160 C 45±6 Etch rates of silicon nitride and TOX are equivalent under the similar conditions Poor selectivity between TOX and SiN without spiking

12 Summary SiN HTW and HT D 2 O etch rates are similar SiN Etching more dependent on temperature than reactive species concentration Follows SiN etching behavior in 85%H 3 PO 4 phosphoric increases [H + ] but does not show increased etch rates over HTW HTW is a viable etchant for silicon nitride However with poor selectivity over silica without spiking HTW is potentially more environmentally friendly and cost effective SiN etchant than hot phosphoric

13 Future Work Dilute hot phosphoric under the same conditions Substitute HT DI water with ultra pure water (UPW) to determine if other ions impact etch rates. Determine concentration and identity dissolved siliceus species in post etch water Silica spiking and other methods to gain selectivity between SiN and SiO 2 Investigate etching of bare silicon Significant etching of underlying silicon

14 Acknowledgements University of North Texas UNT Materials Research Facility Qorvo: Nitride Wafers

15 Thank You Questions?

Czochralski Crystal Growth

Czochralski Crystal Growth Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling

More information

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO (glass) Major factor in making Silicon the main semiconductor Grown at high temperature in

More information

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2 Crystallographic

More information

Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage:

Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage: ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage: http://www.rit.edu/~lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604

More information

Oxide Growth. 1. Introduction

Oxide Growth. 1. Introduction Oxide Growth 1. Introduction Development of high-quality silicon dioxide (SiO2) has helped to establish the dominance of silicon in the production of commercial integrated circuits. Among all the various

More information

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller Webpage: http://www.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604

More information

Photolithography I ( Part 2 )

Photolithography I ( Part 2 ) 1 Photolithography I ( Part 2 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

Use of Spectrograph-based OES for SiN Etch Selectivity and Endpoint Optimization

Use of Spectrograph-based OES for SiN Etch Selectivity and Endpoint Optimization Use of Spectrograph-based OES for SiN Etch Selectivity and Endpoint Optimization F. G. Celii and C. Huffman Texas Instruments, Inc., Dallas, TX, USA J. Hosch* and K. Harvey Verity Instruments, Carrollton,

More information

Chapter 3 CMOS processing technology

Chapter 3 CMOS processing technology Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),

More information

Ultra High Barrier Coatings by PECVD

Ultra High Barrier Coatings by PECVD Society of Vacuum Coaters 2014 Technical Conference Presentation Ultra High Barrier Coatings by PECVD John Madocks & Phong Ngo, General Plasma Inc., 546 E. 25 th Street, Tucson, Arizona, USA Abstract Silicon

More information

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook: HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,

More information

Surface Preparation and Cleaning Conference April 19-20, 2016, Santa Clara, CA, USA. Nano-Bio Electronic Materials and Processing Lab.

Surface Preparation and Cleaning Conference April 19-20, 2016, Santa Clara, CA, USA. Nano-Bio Electronic Materials and Processing Lab. Surface Preparation and Cleaning Conference April 19-20, 2016, Santa Clara, CA, USA Issues on contaminants on EUV mask Particle removal on EUV mask surface Carbon contamination removal on EUV mask surface

More information

VLSI Technology. By: Ajay Kumar Gautam

VLSI Technology. By: Ajay Kumar Gautam By: Ajay Kumar Gautam Introduction to VLSI Technology, Crystal Growth, Oxidation, Epitaxial Process, Diffusion Process, Ion Implantation, Lithography, Etching, Metallization, VLSI Process Integration,

More information

2.4 Period 3. Na Mg Al Si P S Cl Ar

2.4 Period 3. Na Mg Al Si P S Cl Ar 2.4 Period 3 Period 3 Na Mg Al Si P S Cl Ar Periodicity: Periodicity: The repeating trends in physical and chemical properties of elements as you go across the Periodic Table Periods often show gradual

More information

Silicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology

Silicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology Applied Surface Science 212 213 (2003) 388 392 Silicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology Marcus A. Pereira, José A. Diniz, Ioshiaki Doi *, Jacobus W. Swart

More information

Lecture #18 Fabrication OUTLINE

Lecture #18 Fabrication OUTLINE Transistors on a Chip Lecture #18 Fabrication OUTLINE IC Fabrication Technology Introduction the task at hand Doping Oxidation Thin-film deposition Lithography Etch Lithography trends Plasma processing

More information

Today s Class. Materials for MEMS

Today s Class. Materials for MEMS Lecture 2: VLSI-based Fabrication for MEMS: Fundamentals Prasanna S. Gandhi Assistant Professor, Department of Mechanical Engineering, Indian Institute of Technology, Bombay, Recap: Last Class What is

More information

Research Article Silicon Nitride Film by Inline PECVD for Black Silicon Solar Cells

Research Article Silicon Nitride Film by Inline PECVD for Black Silicon Solar Cells Photoenergy Volume 2012, Article ID 971093, 5 pages doi:10.1155/2012/971093 Research Article Silicon Nitride Film by Inline PECVD for Black Silicon Solar Cells Bangwu Liu, Sihua Zhong, Jinhu Liu, Yang

More information

Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University

Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University 2014 Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University Page1 Syllabus UNIT 1 Introduction to VLSI Technology: Classification of ICs, Scale of integration,

More information

Simple Cubic Crystal

Simple Cubic Crystal Starting Material Simple Cubic Crystal Crystal Planes offset by d/4 Diamond lattice cell (C, Si, Ge, etc.) face atom in FCC corner atom in FCC (100) plane (110) plane (111) plane Crystal Planes/Direction

More information

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are:

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are: Chapter 4 1 CHAPTER 4: Oxidation Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are: 1. mask against implant or diffusion of dopant into silicon 2. surface passivation

More information

FIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON

FIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON FIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON Maxim Fadel and Edgar Voges University of Dortmund, High Frequency Institute, Friedrich-Woehler Weg 4, 44227 Dortmund, Germany ABSTRACT

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

the surface of a wafer, usually silicone. In this process, an oxidizing agent diffuses into the wafer

the surface of a wafer, usually silicone. In this process, an oxidizing agent diffuses into the wafer Analysis of Oxide Thickness Measurement Techniques of SiO2: Nanometrics Nanospec Reflectometer and Color Chart Eman Mousa Alhajji North Carolina State University Department of Materials Science and Engineering

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)

More information

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica Microelettronica Planar Technology for Silicon Integrated Circuits Fabrication 26/02/2017 A. Neviani - Microelettronica Introduction Simplified crosssection of an nmosfet and a pmosfet Simplified crosssection

More information

Chapter 4. UEEP2613 Microelectronic Fabrication. Oxidation

Chapter 4. UEEP2613 Microelectronic Fabrication. Oxidation Chapter 4 UEEP2613 Microelectronic Fabrication Oxidation Prepared by Dr. Lim Soo King 24 Jun 2012 Chapter 4...113 Oxidation...113 4.0 Introduction... 113 4.1 Chemistry of Silicon Dioxide Formation... 115

More information

Red luminescence from Si quantum dots embedded in SiO x films grown with controlled stoichiometry

Red luminescence from Si quantum dots embedded in SiO x films grown with controlled stoichiometry Red luminescence from Si quantum dots embedded in films grown with controlled stoichiometry Zhitao Kang, Brannon Arnold, Christopher Summers, Brent Wagner Georgia Institute of Technology, Atlanta, GA 30332

More information

BEOL PRE-METALLIZATION WET CLEAN: POST-ETCH RESIDUE REMOVAL AND METAL COMPATIBILITY

BEOL PRE-METALLIZATION WET CLEAN: POST-ETCH RESIDUE REMOVAL AND METAL COMPATIBILITY BEOL PRE-METALLIZATION WET CLEAN: POST-ETCH RESIDUE REMOVAL AND METAL COMPATIBILITY Q. T. LE*, E. KESTERS*, Y. AKANISHI**, A. IWASAKI**, AND F. HOLSTEYNS* * IMEC, LEUVEN, BELGIUM ** SCREEN SEMICONDUCTOR

More information

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB Fabrication Process Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation 1 Fabrication- CMOS Process Starting Material Preparation 1. Produce Metallurgical Grade Silicon

More information

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to Supporting Information: Substrate preparation and SLG growth: All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to aid in visual inspection of the graphene samples. Prior

More information

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi

More information

Microelectronic Device Instructional Laboratory. Table of Contents

Microelectronic Device Instructional Laboratory. Table of Contents Introduction Process Overview Microelectronic Device Instructional Laboratory Introduction Description Flowchart MOSFET Development Process Description Process Steps Cleaning Solvent Cleaning Photo Lithography

More information

Midterm evaluations. Nov. 9, J/3.155J 1

Midterm evaluations. Nov. 9, J/3.155J 1 Midterm evaluations What learning activities were found most helpful Example problems, case studies (5); graphs (good for extracting useful info) (4); Good interaction (2); Good lecture notes, slides (2);

More information

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between 2 materials Need strong selectivity from masking

More information

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009 Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology

More information

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each

More information

Cambridge International Examinations Cambridge International General Certificate of Secondary Education. Published

Cambridge International Examinations Cambridge International General Certificate of Secondary Education. Published Cambridge International Examinations Cambridge International General Certificate of Secondary Education CHEMISTRY 060/33 Paper 3 Core Theory October/November 06 MARK SCHEME Maximum Mark: 80 Published This

More information

PDS Products PRODUCT DATA SHEET. BN-975 Wafers. Low Defect Boron Diffusion Systems. Features/Benefits BORON NITRIDE

PDS Products PRODUCT DATA SHEET. BN-975 Wafers. Low Defect Boron Diffusion Systems. Features/Benefits BORON NITRIDE Low Defect Boron Diffusion Systems The purpose of the hydrogen injection process is to increase die yield per wafer. This is accomplished because the effects associated with the hydrogen injection process.

More information

The test can be performed on the following devices. In addition, the required cuvette and the absorption range of the photometer are indicated.

The test can be performed on the following devices. In addition, the required cuvette and the absorption range of the photometer are indicated. Silicate HR VARIO PP 1-100 mg/l SiO 2 Silicomolybdate 352 SiHr Instrument specific information The test can be performed on the following devices. In addition, the required cuvette and the absorption range

More information

University of Texas Arlington Department of Electrical Engineering. Nanotechnology Microelectromechanical Systems Ph.D. Diagnostic Examination

University of Texas Arlington Department of Electrical Engineering. Nanotechnology Microelectromechanical Systems Ph.D. Diagnostic Examination University of Texas Arlington Department of Electrical Engineering Nanotechnology Microelectromechanical Systems Ph.D. Diagnostic Examination Fall 2012 November 17, 2012 Question # 1 2 3 To be filled by

More information

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in Chapter 5 PROCESSING OF DEVICES A discussion of crystal growth, lithography, etching, doping, and device structures is presented in the following overview gures. SEMICONDUCTOR DEVICE PROCESSING: AN OVERVIEW

More information

Chapter 5 Thermal Processes

Chapter 5 Thermal Processes Chapter 5 Thermal Processes 1 Topics Introduction Hardware Oxidation Diffusion Annealing Post-Implantation Alloying Reflow High Temp CVD Epi Poly Silicon Nitride RTP RTA RTP Future Trends 2 Definition

More information

Lecture Day 2 Deposition

Lecture Day 2 Deposition Deposition Lecture Day 2 Deposition PVD - Physical Vapor Deposition E-beam Evaporation Thermal Evaporation (wire feed vs boat) Sputtering CVD - Chemical Vapor Deposition PECVD LPCVD MVD ALD MBE Plating

More information

Fabrication and Layout

Fabrication and Layout ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide

More information

Introduction to Lithography

Introduction to Lithography Introduction to Lithography G. D. Hutcheson, et al., Scientific American, 290, 76 (2004). Moore s Law Intel Co-Founder Gordon E. Moore Cramming More Components Onto Integrated Circuits Author: Gordon E.

More information

Kinetics of Silicon Oxidation in a Rapid Thermal Processor

Kinetics of Silicon Oxidation in a Rapid Thermal Processor Kinetics of Silicon Oxidation in a Rapid Thermal Processor Asad M. Haider, Ph.D. Texas Instruments Dallas, Texas USA Presentation at the National Center of Physics International Spring Week 2010 Islamabad

More information

Schematic creation of MOS field effect transistor.

Schematic creation of MOS field effect transistor. Schematic creation of MOS field effect transistor. Gate electrode Drain electrode Source electrode Gate oxide Gate length Page 1 Step 0 The positively doped silicon wafer is first coated with an insulating

More information

MEMS Surface Fabrication

MEMS Surface Fabrication ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING MEMS Surface Fabrication Dr. Lynn Fuller webpage: http://people.rit.edu/lffeee Electrical and Microelectronic Engineering Rochester Institute

More information

CSI G SYSTEMS CSI GAS DELIVERY SUPPORT. Chemical Vapor Deposition (CVD)

CSI G SYSTEMS CSI GAS DELIVERY SUPPORT. Chemical Vapor Deposition (CVD) This page discusses the CVD processes often used for integrated circuits (ICs). Particular materials are deposited best under particular conditions. Facilitation recommendations are at the bottom of the

More information

Thermal Nanoimprinting Basics

Thermal Nanoimprinting Basics Thermal Nanoimprinting Basics Nanoimprinting is a way to replicate nanoscale features on one surface into another, like stamping copies are made by traditional fabrication techniques (optical/ebeam lith)

More information

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior

More information

Plateau-Rayleigh crystal growth of nanowire. heterostructures: Strain-modified surface chemistry

Plateau-Rayleigh crystal growth of nanowire. heterostructures: Strain-modified surface chemistry Supporting Information for: Plateau-Rayleigh crystal growth of nanowire heterostructures: Strain-modified surface chemistry and morphological control in 1, 2 and 3 dimensions Robert W. Day, Max N. Mankin,

More information

Supplimentary Information. Large-Scale Synthesis and Functionalization of Hexagonal Boron Nitride. Nanosheets

Supplimentary Information. Large-Scale Synthesis and Functionalization of Hexagonal Boron Nitride. Nanosheets Electronic Supplementary Material (ESI) for Nanoscale. This journal is The Royal Society of Chemistry 2014 Supplimentary Information Large-Scale Synthesis and Functionalization of Hexagonal Boron Nitride

More information

ALD of Manganese Silicate

ALD of Manganese Silicate ALD of Manganese Silicate Roy G. Gordon, 1,2 * Lu Sun, 2 Qiang Chen, 3 Jin-Seong Park 4 and Sang Bok Kim 1 1 Department of Chemistry and Chemical Biology 2 School of Engineering and Applied Sciences, Cambridge,

More information

AZ BARLi II Solvent Compatible Bottom Antireflective Coating for i-line Process. Data Package

AZ BARLi II Solvent Compatible Bottom Antireflective Coating for i-line Process. Data Package AZ BARLi II Solvent Compatible Bottom Antireflective Coating for i-line Process Data Package AZ BARLi II Coating Material Features, Process, and Performance AZ s bottom antireflective coating material,

More information

Oxidation of Silicon

Oxidation of Silicon OpenStax-CNX module: m24908 1 Oxidation of Silicon Andrew R. Barron This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 3.0 note: This module was developed

More information

Lecture 2: CMOS Fabrication Mark McDermott Electrical and Computer Engineering The University of Texas at Austin

Lecture 2: CMOS Fabrication Mark McDermott Electrical and Computer Engineering The University of Texas at Austin Lecture 2: CMOS Fabrication Mark McDermott Electrical and Computer Engineering The University of Texas at Austin Agenda Last module: Introduction to the course How a transistor works CMOS transistors This

More information

Fundamentals of Post-CMP Cleaning of Dielectric Surface Contaminated with Ceria (Nano-to-Micro) Particles

Fundamentals of Post-CMP Cleaning of Dielectric Surface Contaminated with Ceria (Nano-to-Micro) Particles 20 TH SUFACE PEPAATION AND CLEANING CONFEENCE (SPCC) 2018 Fundamentals of Post-CMP Cleaning of Dielectric Surface Contaminated with Ceria (Nano-to-Micro) Particles Atanu Das, Daniela White, Wonlae Kim,

More information

Materials Characterization

Materials Characterization Materials Characterization C. R. Abernathy, B. Gila, K. Jones Cathodoluminescence (CL) system FEI Nova NanoSEM (FEG source) with: EDAX Apollo silicon drift detector (TE cooled) Gatan MonoCL3+ FEI SEM arrived

More information

Semiconductor device fabrication

Semiconductor device fabrication REVIEW Semiconductor device fabrication is the process used to create the integrated circuits (silicon chips) that are present in everyday electrical and electronic devices. It is a multiplestep sequence

More information

Precursors with Metal-Nitrogen Bonds for ALD of Metals, Nitrides and Oxides

Precursors with Metal-Nitrogen Bonds for ALD of Metals, Nitrides and Oxides Precursors with Metal-Nitrogen Bonds for ALD of Metals, Nitrides and Oxides Abstract Roy Gordon Gordon@chemistry.harvard.edu, Cambridge, MA To achieve ALD s unique characteristics, ALD precursors must

More information

Chemical Vapor Deposition

Chemical Vapor Deposition Preparation of Low-k Porous SiO 2 Films by SiO 2 /Organic Hybrid Chemical Vapor Deposition Akira Fujimoto and Osamu Sugiura Department of Physical Electronics, Tokyo Institute of Technology, 2-2-, O-okayama,

More information

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao Report 1 A. Overview The goal of this lab is to go through the semiconductor fabrication process from start to finish. This

More information

TANOS Charge-Trapping Flash Memory Structures

TANOS Charge-Trapping Flash Memory Structures TANOS Charge-Trapping Flash Memory Structures A Senior Design by Spencer Pringle 5/8/15 Table of Contents Motivation Why Charge-Trapping Flash (CTF)? Charge-Trapping vs. Floating Gate Electronically-Erasable

More information

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook CMOS Fabrication Dr. Bassam Jamil Adopted from slides of the textbook CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different

More information

EFFECT OF CRYSTALORIENTATIONIN OXIDATION PROCESS OF VLSI FABRICATION

EFFECT OF CRYSTALORIENTATIONIN OXIDATION PROCESS OF VLSI FABRICATION International Journal of Research in Engineering, Technology and Science, Volume VII, Special Issue, Feb 2017 www.ijrets.com, editor@ijrets.com, ISSN 2454-1915 EFFECT OF CRYSTALORIENTATIONIN OXIDATION

More information

1 MARCH 2017 FILM DEPOSITION NANOTECHNOLOGY

1 MARCH 2017 FILM DEPOSITION NANOTECHNOLOGY 1 MARCH 2017 FILM DEPOSITION NANOTECHNOLOGY PRESENTATION Pedro C. Feijoo E-mail: PedroCarlos.Feijoo@uab.cat FABRICATION TECHNOLOGIES FOR NANOELECTRONIC DEVICES. PEDRO C. FEIJOO 2 FILM GROWTH Chemical vapor

More information

Lab #2 Wafer Cleaning (RCA cleaning)

Lab #2 Wafer Cleaning (RCA cleaning) Lab #2 Wafer Cleaning (RCA cleaning) RCA Cleaning System Used: Wet Bench 1, Bay1, Nanofabrication Center Chemicals Used: H 2 O : NH 4 OH : H 2 O 2 (5 : 1 : 1) H 2 O : HF (10 : 1) H 2 O : HCl : H 2 O 2

More information

Ni-Si alloys for Hydrogen Generation by the Sulfur-Iodine Cycle

Ni-Si alloys for Hydrogen Generation by the Sulfur-Iodine Cycle Ni-Si alloys for Hydrogen Generation by the Sulfur-Iodine Cycle J. W. Newkirk, R.D. Brow, T. Lillo*, C. Larson, and R. Hsu Missouri University of Science & Technology *Idaho National Laboratory Acknowledgments

More information

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very high voltages (10-600 KeV) Use analyzer to selection charge/mass

More information

Review of CMOS Processing Technology

Review of CMOS Processing Technology - Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 3D Perspective 2 3 Fabrication

More information

Haiyan Li 1*, Akira Endou 2, Annette Schaper 1, Todd Eck 1, Toshio Shinoda 2, Anne Miller 1*

Haiyan Li 1*, Akira Endou 2, Annette Schaper 1, Todd Eck 1, Toshio Shinoda 2, Anne Miller 1* Haiyan Li 1*, Akira Endou 2, Annette Schaper 1, Todd Eck 1, Toshio Shinoda 2, Anne Miller 1* 1 Fujimi Corporation, Oregon, USA 97062 2 Fujimi Incorporated, Gifu, Japan 509-0108 *Contacts: hli@fujimico.com,

More information

AZ BARLi II Solvent Compatible Bottom Antireflective Coating for i-line Process Data Package

AZ BARLi II Solvent Compatible Bottom Antireflective Coating for i-line Process Data Package AZ BARLi II Solvent Compatible Bottom Antireflective Coating for i-line Process Data Package The information contained herein is, as far as we are aware, true and accurate. However, no representations

More information

Crystal Growth and Wafer Fabrication. K.Sivasankaran, Assistant Professor (Senior), VLSI Division, School of Electronics Engineering, VIT

Crystal Growth and Wafer Fabrication. K.Sivasankaran, Assistant Professor (Senior), VLSI Division, School of Electronics Engineering, VIT Crystal Growth and Wafer Fabrication K.Sivasankaran, Assistant Professor (Senior), VLSI Division, School of Electronics Engineering, VIT Crystal growth Obtaining sand Raw Polysilicon Czochralski Process

More information

A Nano-thick SOI Fabrication Method

A Nano-thick SOI Fabrication Method A Nano-thick SOI Fabrication Method C.-H. Huang 1, J.T. Cheng 1, Y.-K. Hsu 1, C.-L. Chang 1, H.-W. Wang 1, S.-L. Lee 1,2, and T.-H. Lee 1,2 1 Dept. of Mechanical Engineering National Central University,

More information

Carbon Nanotubes by Microwave Plasma-Enhanced Chemical Vapor Deposition

Carbon Nanotubes by Microwave Plasma-Enhanced Chemical Vapor Deposition Carbon Nanotubes by Microwave Plasma-Enhanced Chemical Vapor Deposition M. Maschmann 2, A. Goyal 3, Z. Iqbal 3, T.S. Fisher 2, R. Gat 1 1. Seki Technotron USA. Santa Clara CA, USA. rgat@sekitech.com 2.

More information

Highly Reliable Low Temperature Ultrathin Oxides Grown Using N 2 O Plasma

Highly Reliable Low Temperature Ultrathin Oxides Grown Using N 2 O Plasma Highly Reliable Low Temperature Ultrathin Oxides Grown Using N 2 O Plasma Jam-Wem Lee 1, Yiming Li 1,2, and S. M. Sze 1,3 1 Department of Nano Device Technology, National Nano Device Laboratories, Hsinchu,

More information

Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications

Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications Authors: Jeb. H Flemming, Kevin Dunn, James Gouker, Carrie Schmidt, Roger Cook ABSTRACT Historically, while glasses have many

More information

Si DRIE APPLICATION In Corial 210IL

Si DRIE APPLICATION In Corial 210IL Si DRIE APPLICATION In Corial 210IL CORIAL 210IL ICP-RIE equipment for deep Si etching applications Enlarged functionality with capability to deep etch silicon, silicon carbide, glass, sapphire, and quartz

More information

Surface Micromachining

Surface Micromachining Surface Micromachining Outline Introduction Material often used in surface micromachining Material selection criteria in surface micromachining Case study: Fabrication of electrostatic motor Major issues

More information

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi

More information

Growth of large single-crystalline two-dimensional boron. nitride hexagons on electropolished copper

Growth of large single-crystalline two-dimensional boron. nitride hexagons on electropolished copper Supporting Information Growth of large single-crystalline two-dimensional boron nitride hexagons on electropolished copper Roland Yingjie Tay,, Mark H. Griep, Govind Mallick,, Siu Hon Tsang, Ram Sevak

More information

Doping and Oxidation

Doping and Oxidation Technische Universität Graz Institute of Solid State Physics Doping and Oxidation Franssila: Chapters 13,14, 15 Peter Hadley Technische Universität Graz Institute of Solid State Physics Doping Add donors

More information

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time IC Fabrication Technology Crystal Preparation

More information

Fabrication of sub-100nm thick Nanoporous silica thin films

Fabrication of sub-100nm thick Nanoporous silica thin films Fabrication of sub-100nm thick Nanoporous silica thin films Abstract M. Ojha, W. Cho, J. L. Plawsky, W. N. Gill Department of chemical and biological engineering, Rensselaer Polytechnic Institute Low refractive

More information

Supplementary Information

Supplementary Information Supplementary Information Supplementary Figure 1 Characterization of precursor coated on salt template. (a) SEM image of Mo precursor coated on NaCl. Scale bar, 50 μm. (b) EDS of Mo precursor coated on

More information

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Metallization deposition and etching. Material mainly taken from Campbell, UCCS Metallization deposition and etching Material mainly taken from Campbell, UCCS Application Metallization is back-end processing Metals used are aluminum and copper Mainly involves deposition and etching,

More information

Induced Crystallization of Rubrene with Diazapentacene as the Template Danqing Liu, 1 Zhefeng Li, 1 Zikai He, 1 Jianbin Xu, 2 Qian Miao* 1, 3

Induced Crystallization of Rubrene with Diazapentacene as the Template Danqing Liu, 1 Zhefeng Li, 1 Zikai He, 1 Jianbin Xu, 2 Qian Miao* 1, 3 Electronic Supplementary Information for: Induced Crystallization of Rubrene with Diazapentacene as the Template Danqing Liu, 1 Zhefeng Li, 1 Zikai He, 1 Jianbin Xu, 2 Qian Miao* 1, 3 1 Department of Chemistry,

More information

Physical Vapor Deposition (PVD) Zheng Yang

Physical Vapor Deposition (PVD) Zheng Yang Physical Vapor Deposition (PVD) Zheng Yang ERF 3017, email: yangzhen@uic.edu Page 1 Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide

More information

BEFORE you can do any resist processing, you must be familiar with the chemicals you will be using, and know and respect the dangers of them.

BEFORE you can do any resist processing, you must be familiar with the chemicals you will be using, and know and respect the dangers of them. Overview Any e-beam exposure is highly dependant upon processing and the substrate. This information is provided as a starting point and will required experimentation to optimize things for your work.

More information

Investigation on the Impact of Metallic Surface Contaminations on Minority Carrier Lifetime of a-si:h Passivated Crystalline Silicon

Investigation on the Impact of Metallic Surface Contaminations on Minority Carrier Lifetime of a-si:h Passivated Crystalline Silicon Available online at www.sciencedirect.com Energy Procedia 8 (2011) 6 288 293 1 5 SiliconPV: 17-20 April 2011, Freiburg, Germany Investigation on the Impact of Metallic Surface Contaminations on Minority

More information

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: Fabrication of p-n junctions Contact Potential Things you should know when you leave Key Questions What are the necessary steps to fabricate

More information

Wet Processing Techniques for Achieving Ultra-shallow Junctions in Future CMOS Devices

Wet Processing Techniques for Achieving Ultra-shallow Junctions in Future CMOS Devices Accelerating the next technology revolution Wet Processing Techniques for Achieving Ultra-shallow Junctions in Future CMOS Devices Joel Barnett, Richard Hill, Chris Hobbs and Prashant Majhi 07-October-2010

More information

Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge

Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge R. Chanson a, E. Pargon a, M. Darnon a, C. Petit Etienne a, S. David a, M. Fouchier a, B. Glueck b, P. Brianceau

More information

Platypus Gold Coated Substrates. Bringing Science to the Surface

Platypus Gold Coated Substrates. Bringing Science to the Surface Platypus Gold Coated Substrates Bringing Science to the Surface Overview Gold Coated Substrates - Gold Coating Introduction - Glossary of Terms - Gold Coating Methods - Critical Features Platypus Gold

More information

Semiconductor Technology

Semiconductor Technology Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................

More information

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY CHAPTER - 4 CMOS PROCESSING TECHNOLOGY Samir kamal Spring 2018 4.1 CHAPTER OBJECTIVES 1. Introduce the CMOS designer to the technology that is responsible for the semiconductor devices that might be designed

More information

Electrical Properties of Ultra Shallow p Junction on n type Si Wafer Using Decaborane Ion Implantation

Electrical Properties of Ultra Shallow p Junction on n type Si Wafer Using Decaborane Ion Implantation Mat. Res. Soc. Symp. Proc. Vol. 686 2002 Materials Research Society Electrical Properties of Ultra Shallow p Junction on n type Si Wafer Using Decaborane Ion Implantation Jae-Hoon Song, Duck-Kyun Choi

More information