Arcing prevention by dry clean optimization using plasma parameter monitoring
|
|
- Ella Barker
- 6 years ago
- Views:
Transcription
1 Arcing prevention by dry clean optimization using plasma parameter monitoring Das diesem Bericht zugrundeliegende Vorhaben wurde mit Mitteln des Sächsischen Staatsministeriums für Wirtschaft und Arbeit (Förderkennzeichen 5706) gefördert. Die Verantwortung für den Inhalt dieser Veröffentlichung liegt beim Autor. Page 1 11 th 12 th of December 2000, - Germany
2 Overview! Shallow Trench Isolation (STI) etch process - Overview! The problem! Experimental Sequence (Overview)! Basic experiments with CF 4 /O 2 Cleans " etchrate vs. O 2 - concentration " electron collision rate vs. O 2 - concentration " clean influence on Conditioning - wafers " basic experiment summary! Experiments on product wafers! Summary! Outlook Page 2 11 th 12 th of December 2000, - Germany
3 STI etch process - Overview a) Starting profile b) Mask-open step c) Trench etch step Resist ARC SiN Si deep trench Resist ARC SiN d) Oxide CVD e) Planarization f) A-B: top-cd Oxide Oxid A SiN SiN Si Si Si Oxide Resist ARC SiN Si bottom-cd Page 3 11 th 12 th of December 2000, - Germany B
4 The problem (motivation)! New DRAM product # new recipe for STI etch necessary! New recipe generates more chamber wall polymers " increased arcing danger " more extensive chamber cleaning! New dry clean for wall polymer reduction used " reduces wall polymers, but " Critcal Dimension (CD) on product wafers effected! # New dry clean recipe needed with: " effective wall polymer reduction (simultaneously reduces arcing danger) " no CD degradation on product wafers Page 4 11 th 12 th of December 2000, - Germany
5 Joined application of impulse detection in the RF stray field and SEERS to fix the arcing problem No arcing during these measurements! Illustration of impulses observed in RF stray field outside the chamber over one wetclean cycle! Very high sensitivity, many impulses, but no arcing observed! Combination of two real time in-situ measurement techniques to solve arcing problem: " Impulse detection in the RF stray field outside the chamber will detect breakdowns of the electromagnetic field caused by micro arcing " Plasma parameters will help to optimize dry clean and detect heavy arcing Page 5 11 th 12 th of December 2000, - Germany
6 Experimental sequence! Determination of suitable O 2 and CF 4 concentration! best dry clean recipe tested on resist wafers! Shorter clean step - test on resist wafers! Dry clean with conditioning step - test on product wafers! Changed conditioning step recipe - test on product wafers! Variation of clean- / conditioning time - test on resist wafers Page 6 11 th 12 th of December 2000, - Germany
7 Basic experiment with CF 4 /O 2 dry cleans (DC) O2 CF4 Gesamt O2 CF4 sccm sccm sscm % % ,3 16, ,4 20, ,0 50, ,0 50, ,7 83,3 Experiment Cond DC 1 Cond DC 3 Cond DC 4 Cond DC 5 Cond DC 2 Etchrate meas. DC 1 DC 3 DC 4 DC 5 DC 2! Test of dry clean recipies by measurement of resist etch rate on test wafers! 5 dry clean (DC) - recipes with varying O 2 /CF 4 - ratios to figure out a working recipe! First part of experiment: run conditioning wafers to recondition chamber before each clean Page 7 11 th 12 th of December 2000, - Germany
8 Dependence of etch rate on O 2 - concentration (resist test wafers) Etchrate vs. O 2 Concentration Etchrate [nm/min] O 2 [Vol%]! Highest etch rates in case of O 2 - concentration being much higher than CF 4 -concentration (dry clean 1 and 2)! Lowest etch rate in case CF 4 dominates (dry clean 5)! Higher etch rate with higher total gas flow (dry clean 3 vs. dry clean 4) 2 1 Page 8 11 th 12 th of December 2000, - Germany
9 Dependence of electron collision rate on O 2 concentration: Bare Si-wafers vs. resist wafers electron collisionrate [s -1 ] 3,50E+07 3,00E+07 2,50E+07 2,00E+07 1,50E+07 1,00E+07 5,00E+06 0,00E+00 Electron collisionrate vs. O 2 concentration [median] O 2 (vol%) DC on Si-Wafer DC etchrate meas.! The higher the O 2 - concentration, the lower the electron collision rate in dry clean - test at etch rate measurment (red curve)! But: there are big differences in electron collision rate depending on type of wafer used " DC on Si- wafer doesn t have such a big influence on plasma as DC on resist wafers, because of less reaction products from wafer surface (blue curve) Page 9 11 th 12 th of December 2000, - Germany
10 Impact of dry clean on chamber conditioning as measured by monitoring electron collision rate Page 10 median collision rate [s -1 ] Dryclean 3,00E+07 2,50E+07 2,00E+07 1,50E+07 1,00E+07 5,00E+06 electron collision rate vs. time [median] 0,00E+00 2,30E+07 14:52 15:21 15:50 16:19 16:48 17:16 17:45 time [s]! First wafer effect depends on clean time: dry clean 1: wafer dry clean 2: 1 wafer! Clean process indicates long term chamber drift dry clean 1 4,80E+07 4,30E+07 3,80E+07 3,30E+07 2,80E+07 3,00E+07 2,50E+07 2,00E+07 1,50E+07 1,00E+07 5,00E th 12 th of December 2000, - Germany median collision rate [s -1 ] Cond Dryclean! Comparison of two different dry clean recipies! Variation of process time: dry clean 1 > dry clean 2 electron collision rate vs. time [median] 0,00E+00 15:21 15:50 16:19 16:48 17:16 17:45 time [s] dry clean 2 Cond 4,80E+07 4,30E+07 3,80E+07 3,30E+07 2,80E+07 2,30E+07
11 Basic experiments - summary! General problem: " Etch rate is measured on resist test wafers on the cathode " It does not reflect etch rate of polymers on the chamber walls directly! Result of basic experiments: With higher O 2 concentration: " # higher resist etch rate on test wafers " # lower electron collision rate in plasma! Dry clean with high O 2 - concentration was chosen for further experiments! First wafer effect strongly depends on process time of dry clean. But even short dry clean shows significant impact on first wafer after clean.! Conclusions: " Application of a conditioning step after clean to reduce first wafer effect " Ratio between clean step and conditioning step has to be optimized Page th 12 th of December 2000, - Germany
12 Experiments on product wafers! Experiments on product wafers were done with dry clean recipe chosen from basic experiments (high O 2 concentration)! Questions: " Does dry clean influence the process on product wafers in the same way as on resist test wafers? " What s the impact of the CF 4 /O 2 dry clean on critical dimensions (CD) at STI etch?! # Variation of " Conditioning recipe " Clean step time " Conditioning step time! Targets: " Minimize of first wafer effects and " Maximize of polymer reduction at chamber wall Page th 12 th of December 2000, - Germany
13 Impact of dry clean with conditioning step on product wafers: Critical Dimensions top-cd vs. time [mean] top-cd [nm] 17:45 18:14 18:43 19:12 19:40 20:09 20:38 21:07 time red points: first productwafer after each clean! First wafer effect is indicated by critical dimensions, measured on product wafers! # Chosen dry clean process with conditioning step has still significant impact on critical dimensions at STI etch Page th 12 th of December 2000, - Germany
14 Impact of dry clean with conditioning step on chamber conditions electron collision rate on product wafers 6,00E+07 electron collision rate vs. time [median] 3,90E+07 median collision rate [s -1 ] 5,50E+07 5,00E+07 4,50E+07 4,00E+07 3,50E+07 3,00E+07 Dryclean 17:45 18:57 20:09 21:21 DC Clean-Step MemoryProduct IT-Mask-Step MemoryProduct IT-Mask-Step (next lot) time 3,50E+07 3,10E+07 2,70E+07 2,30E+07 Memory! First wafer effect, caused by dry clean, is indicated by electron collision rate! Additionally electron collision rate indicates drift of chamber conditions (mean down trend) Page th 12 th of December 2000, - Germany
15 Correlation top - CD vs. electron collision rate electron collision rate (IT-Mask) vs. top-cd top-cd [nm] 2,50E+07 2,70E+07 2,90E+07 3,10E+07 3,30E+07 3,50E+07 3,70E+07 3,90E+07 median electron collision rate [s -1 ]! Red points represent first product wafers after dry clean! Electron collision rate vs. top- CD does not correlate, although red points are seperated from others è because of low top- CD Page th 12 th of December 2000, - Germany
16 Impact of dry clean conditioning step without CF 4 / O 2 on Critical Dimension top-cd vs. time [mean] Page 16 top-cd [nm] 14:52 15:21 15:50 16:19 16:48 17:16 17:45 18:14 18:43 19:12 time! Now dry clean doesn t seem to have a big influence on critical dimensions! But: is dry clean still as effective? Polymers are generated in the conditioning step and without CF 4 / O 2 even more # possibly the clean effect is spoiled by the following conditioning step?) 11 th 12 th of December 2000, - Germany! Dry clean with CF 4 / O 2 in clean step, but no CF 4 / O 2 in conditioning step now!
17 Electron collision rate at conditioning step without CF 4 / O 2 electron collisionrate vs. time [median] median collisionrate [s -1 ] 3,80E+07 3,60E+07 3,40E+07 3,20E+07 3,00E+07 2,80E+07 14:52 15:21 15:50 16:19 16:48 17:16 17:45 18:14 18:43 19:12 time [s] DRAM product! No significant first wafer effect after each dry clean Page th 12 th of December 2000, - Germany
18 Variation of clean time and conditioning time! Notation: " CleanL - long clean (used in last experiments) " CleanS - short clean " CondL - long Conditioning " CondS - short Conditioning (used in last experiments)! Experiment in 3 runs on resist test wafers: " CleanL/CondS " CleanL/CondL " CleanS/CondS Page th 12 th of December 2000, - Germany
19 CleanL / CondS: comparison of plasma parameters Page 19 median collision rate [s -1 ] 4,60E+07 4,20E+07 3,80E+07 3,40E+07 electron collisionrate vs. time [median] IT-Mask-Step 3,00E+07 4,00E+06 14:24 14:52 15:21 15:50 16:19 16:48 17:16 time! But now there is a trend in electron density of resist wafers after each dry clean " plasma parameter response has changed with change in dry clean recipe! median electron density [cm -3 ] 1,20E+07 1,00E+07 8,00E+06 6,00E th 12 th of December 2000, - Germany 5,00E+08 4,60E+08 4,20E+08 3,80E+08 3,40E+08 3,00E+08! There is no significant trend in collision rate of resist wafers after each dry clean... "...as it was seen previously with CF 4 / O 2 in conditioning step or even without conditioning step electrondensity vs. time [median] Si-Etch-Step 14:24 14:52 15:21 15:50 16:19 16:48 17:16 time 2,00E+09 1,96E+09 1,92E+09 1,88E+09 1,84E+09 1,80E+09
20 Comparison of electron density for CleanL / CondS and CleanL / CondL Page 20 median electron density [cm -3 ] electron density vs. time [median] 5,00E+08 4,60E+08 4,20E+08 3,80E+08 3,40E+08 3,00E+08 14:24 14:52 15:21 15:50 16:19 16:48 17:16 CleanL/CondL Si-Etch-Step time CleanL/CondS median electron density [cm -3 ] 2,00E+09 1,96E+09 1,92E+09 1,88E+09 1,84E+09 1,80E th 12 th of December 2000, - Germany 5,00E+08 4,60E+08 4,20E+08 3,80E+08 3,40E+08 3,00E+08! Longer conditioning time doesn t seem to cause changes in trend of electron density of following resist wafers electrondensity vs. time [median] Si-Etch-Step 14:24 14:52 15:21 15:50 16:19 16:48 17:16 time 2,00E+09 1,96E+09 1,92E+09 1,88E+09 1,84E+09 1,80E+09
21 Comparison of electron density for CleanL / CondS and CleanS / CondS Page 21 median electron density [cm -3 ] 5,00E+08 4,60E+08 4,20E+08 3,80E+08 3,40E+08 3,00E+08 electrondensity vs. time [median] 17:16 17:45 18:14 18:43 19:12 19:40 20:09 20:38 CleanS / CondS Si-Etch-Step time CleanL / CondS 2,00E+09 1,96E+09 1,92E+09 1,88E+09 1,84E+09 1,80E+09 median electron density [cm -3 ] 11 th 12 th of December 2000, - Germany 5,00E+08 4,60E+08 4,20E+08 3,80E+08 3,40E+08 3,00E+08! Shorter clean time reduces first wafer effect on following resist test wafers! But shorter clean means less polymer reduction at chamber walls! electrondensity vs. time [median] Si-Etch-Step 14:24 14:52 15:21 15:50 16:19 16:48 17:16 time 2,00E+09 1,96E+09 1,92E+09 1,88E+09 1,84E+09 1,80E+09
22 Summary! Electron collision rate and electron density have been used to optimize a new clean recipe at Shallow Trench Isolation etch in AMAT MxP chamber.! Both plasma parameters show in real time " Dry clean impact on chamber conditions and first wafer effect on product wafers " And superimposed long term drift effects of chamber conditions! The general problem is dry clean optimization by etch rate measurement on resist test wafers. However, wall polymers are etched as well!! Because plasma parameters do indicate chamber condition drifts, they can be used to monitor clean efficiency with respect to wall polymers.! Therefore plasma parameter measurements can significantly help to improve efficiency & reduce costs of dry clean process development. Page th 12 th of December 2000, - Germany
23 Outlook! Dry clean optimisation from economic point of view (i.e. low cleaning incidence)! Investigation of new dry clean efficiency, i.e. by determining polymer thickness before each wetclean! Observation of inline parameters for products over long time! Do plasma parameters at new dry clean behave in a different way, than they did at the old one (long time over one wet clean cycle)? Page th 12 th of December 2000, - Germany
LAM 490 Etch Recipes. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING LAM 490 Etch Recipes Dr. Lynn Fuller Professor, Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)
More informationImprove the quality of primary reformer catalyst loading by Unidense technology
Improve the quality of primary reformer catalyst loading by Unidense technology UNIDENSE TM catalyst loading technology is used for filling primary reformer tubes in ammonia, methanol, hydrogen and other
More informationStrategy and Roadmap. Dr. Michael Klick. 4th Workshop on Self Excited Plasma Spectroscopy Hilton Salon Europa, April 18th, 2007, Dresden, Germany
Strategy and Roadmap Dr. Michael Klick 4th Workshop on Self Excited Plasma Spectroscopy Hilton Salon Europa, April 18th, 2007, Dresden, Germany Plasmetrex Business Segments Plasma metrology equipment for
More informationVia etching in BCB for HBT technology
Via etching in for HBT technology H.Stieglauer, T.Wiedenmann, H.Bretz, H.Mietz, D.Traulsen, D.Behammer United Monolithic Semiconductors GmbH, Wilhelm-Runge-Strasse 11, D-89081 Ulm, Germany Phone: +49-731-505-3075,
More informationReview of CMOS Processing Technology
- Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from
More informationProcess Challenges for 1S-1R Crossbar Memory
Process Challenges for 1S-1R Crossbar Memory W. Kim, M. Frei and M. Pakala OUTLINE Background Crossbar Memory as Storage Class Memory (SCM) Chalcogenide Materials: PCM, OTS Selector Crossbar patterning
More informationUHF-ECR Plasma Etching System for Gate Electrode Processing
Hitachi Review Vol. 51 (2002), No. 4 95 UHF-ECR Plasma Etching System for Gate Electrode Processing Shinji Kawamura Naoshi Itabashi Akitaka Makino Masamichi Sakaguchi OVERVIEW: As the integration scale
More informationInductive Coupled Plasma (ICP) Textures as Alternative for Wet Chemical Etching in Solar Cell Fabrication
Inductive Coupled Plasma (ICP) Textures as Alternative for Wet Chemical Etching in Solar Cell Fabrication 1 Motivation 2 Experimental setup 3 ICP textures as alternative technique 3.1 Surface morphology
More informationSURFACE AND GAS PHASE REACTIONS FOR FLUOROCARBON PLASMA ETCHING OF SiO 2
27th IEEE International Conference on Plasma Science New Orleans, Louisiana June 4-7, 2000 SURFACE AND GAS PHASE REACTIONS FOR FLUOROCARBON PLASMA ETCHING OF SiO 2 Da Zhang* and Mark J. Kushner** *Department
More informationCorial PS200 4-sided multi-module platform
Corial PS200 4-sided multi-module platform Single wafer platform equipped with 200 mm modules Integration of ICP-CVD or PECVD process chambers Fully automated platform with cassette-to-cassette handler
More informationA Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon
A Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon April 2009 A Deep Silicon RIE Primer 1.0) Etching: Silicon does not naturally etch anisotropically in fluorine based chemistries. Si
More informationSi DRIE APPLICATION In Corial 210IL
Si DRIE APPLICATION In Corial 210IL CORIAL 210IL ICP-RIE equipment for deep Si etching applications Enlarged functionality with capability to deep etch silicon, silicon carbide, glass, sapphire, and quartz
More informationUsage of Hercules inside. Dennis Föh Advanced Process Control Micronas Freiburg. commercial FDC System Maestria
Usage of Hercules inside Dennis Föh Advanced Process Control Micronas Freiburg commercial FDC System Maestria Why are Plasma Parameters ideal for FDC in Etch? Electron Density and Collision Rate are sensitive
More informationA Production-Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts*
A Production-Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts* Raymond R. Jin, Jeffrey David, Bob Abbassi, Tom Osterheld, Fritz Redeker Applied Materials, 3111 Coronado Drive, M/S
More informationEE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects
EE 330 Lecture 8 IC Fabrication Technology Part II - Oxidation - Epitaxy - Polysilicon - Interconnects Review from Last Time MOS Transistor Bulk Source Gate Drain p-channel MOSFET Lightly-doped n-type
More information2.830J / 6.780J / ESD.63J Control of Manufacturing Processes (SMA 6303) Spring 2008
MIT OpenCourseWare http://ocw.mit.edu 2.830J / 6.780J / ESD.63J Control of Manufacturing Processes (SMA 6303) Spring 2008 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/term
More informationCMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI
CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters
More informationEE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time IC Fabrication Technology Crystal Preparation
More informationUnderstanding. Brewer Science
Understanding ARC Products General ARC Presentation: Slide #1 Overview Anti-reflective coating introduction Types of anti-reflective coating Advantages to anti-reflective coatings Advantages to bottom
More informationExamples of dry etching and plasma deposition at Glasgow University
Examples of dry etching and plasma deposition at Glasgow University Glasgow has pioneered and established many novel research activities involving the development of new dry etch processes and dry etch
More informationEE 434 Lecture 9. IC Fabrication Technology
EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and
More informationFabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB
Fabrication Process Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation 1 Fabrication- CMOS Process Starting Material Preparation 1. Produce Metallurgical Grade Silicon
More informationMake sure the exam paper has 9 pages total (including cover page)
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2010 EE143 Midterm Exam #2 Family Name First name SID Signature Solution Make sure the exam
More informationEtching Gold using Oxford Ion Mill Tool
Etching Gold using Oxford Ion Mill Tool Object: To get the etch rate and selectivity (Al2O3 as an etch mask), as well as etch profile, of Au by using Oxford Ion Mill tool. Experimental: 1) Wafer Clean:
More informationDesign, Construction, and Competition-mode of an energygaining prototype for future living in 2015 within the Solar Decathlon 2009
Summary Report Design, Construction, and Competition-mode of an energygaining prototype for future living in 2015 within the Solar Decathlon 2009 Project Ing. Jörg Manager: Wollenweber Prof. Manfred Hegger,
More informationEndpoint Detection of Low Open Area Contact Nitride Etches by Use of Optical Emission Spectroscopy in an APC Compatible Multi-Sensor Platform
Endpoint Detection of Low Open Area Contact Nitride Etches by Use of Optical Emission Spectroscopy in an APC Compatible Multi-Sensor Platform AEC/APC Asia 2005 Bernard KAPLAN, Eric BLUEM (HORIBA Jobin
More informationSemiconductor Manufacturing Technology. IC Fabrication Process Overview
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you
More informationLect. 2: Basics of Si Technology
Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters
More informationPlasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate
Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates
More informationReactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge
Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge R. Chanson a, E. Pargon a, M. Darnon a, C. Petit Etienne a, S. David a, M. Fouchier a, B. Glueck b, P. Brianceau
More informationEE 330 Lecture 9. IC Fabrication Technology Part 2
EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this
More informationHolography of Making 1D-Nano-Trench-Lines and 2D-Nano-Posts
Laser: He-Cd Gas Laser ( =325nm). Pitch Distance d: 200~300nm ( : 54~33 o ). Holography of Making 1D-Nano-Trench-Lines and 2D-Nano-Posts A)Process Details of the holographic 1D-line pattern (210nm thick
More informationCORIAL D500. Large capacity batch system for 24/7 production environment
CORIAL D500 Large capacity batch system for 24/7 production environment High-quality films for a wide range of materials, incl. SiO2, Si3N4, SiOCH, SiOF, SiC and asi-h films Film deposition from 120 C
More informationPhysical Vapor Deposition (PVD) Zheng Yang
Physical Vapor Deposition (PVD) Zheng Yang ERF 3017, email: yangzhen@uic.edu Page 1 Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide
More informationChapter 4 : ULSI Process Integration (0.18 m CMOS Process)
Chapter : ULSI Process Integration (0.8 m CMOS Process) Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e)
More informationProcess Stability in Photo Mask Manufacturing
Process Stability in Photo Mask Manufacturing Authors: Martin Bäßler 1, Haiko Rolff 1, A. Lajn 1, Michael Klick 2, Ralf Rothe 2 Affiliation: 1) Advanced Mask Technology Center GmbH & Co. KG 2) Plasmetrex
More informationCorial D500 No mechanical cleaning
Corial D500 No mechanical cleaning Large capacity batch system for 24/7 production environment High-quality films for a wide range of materials, incl. SiO2, Si3N4, SiOCH, SiOF, SiC and asi-h films Film
More informationAktualisierte Analyse des deutschen Marktes zur freiwilligen Kompensation von Treibhausgasemissionen
CLIMATE CHANGE 02/2015 Aktualisierte Analyse des deutschen Marktes zur freiwilligen Kompensation von Treibhausgasemissionen Revised Analysis of the German Offset Market for Greenhouse Gas Emissions - ENGLISH
More informationHybrid BARC approaches for FEOL and BEOL integration
Hybrid BARC approaches for FEOL and BEOL integration Willie Perez a, Stephen Turner a, Nick Brakensiek a, Lynne Mills b, Larry Wilson b, Paul Popa b a Brewer Science, Inc., 241 Brewer Dr., Rolla, MO 6541
More informationPlasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate
Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates
More informationEE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO
More information200mm Next Generation MEMS Technology update. Florent Ducrot
200mm Next Generation MEMS Technology update Florent Ducrot The Most Exciting Industries on Earth Semiconductor Display Solar 20,000,000x reduction in COST PER TRANSISTOR in 30 years 1 20x reduction in
More informationCopper Interconnect Technology
Tapan Gupta Copper Interconnect Technology i Springer Contents 1 Introduction 1 1.1 Trends and Challenges 2 1.2 Physical Limits and Search for New Materials 5 1.3 Challenges 6 1.4 Choice of Materials 7
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 3D Perspective 2 3 Fabrication
More informationEtching Mask Properties of Diamond-Like Carbon Films
N. New Nawachi Diamond et al. and Frontier Carbon Technology 13 Vol. 15, No. 1 2005 MYU Tokyo NDFCT 470 Etching Mask Properties of Diamond-Like Carbon Films Norio Nawachi *, Akira Yamamoto, Takahiro Tsutsumoto
More informationLecture Day 2 Deposition
Deposition Lecture Day 2 Deposition PVD - Physical Vapor Deposition E-beam Evaporation Thermal Evaporation (wire feed vs boat) Sputtering CVD - Chemical Vapor Deposition PECVD LPCVD MVD ALD MBE Plating
More informationDenton 635 Sputter SOP
Denton 635 SOP Page 1 of 8 Denton 635 Sputter SOP 1. Scope 1.1 This document provides operating procedures for the Denton 635 automated sputter system.. 2. Table of Contents 1. Scope... 1 2. Table of Contents...
More information(12) United States Patent (10) Patent No.: US 6,670,279 B1
USOO6670279B1 (12) United States Patent (10) Patent No.: US 6,670,279 B1 Pai et al. (45) Date of Patent: Dec. 30, 2003 (54) METHOD OF FORMING SHALLOW 6,228,727 B1 5/2001 Lim et al.... 438/296 TRENCH ISOLATION
More informationCzochralski Crystal Growth
Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling
More informationPROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS
Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative
More informationApplication of SEERS to real time Plasma Monitoring in Production at different FABs
AECAPC SYMPOSIUM 21, BANFF Application of SEERS to real time Plasma Monitoring in Production at different FABs Volker Tegeder Sensor Evaluation Calculation of expected Economical Benefit Automatic link
More informationFIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON
FIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON Maxim Fadel and Edgar Voges University of Dortmund, High Frequency Institute, Friedrich-Woehler Weg 4, 44227 Dortmund, Germany ABSTRACT
More informationEV-140 P, New Emission Spectroscopic Product for Semiconductor Endpoint, Cleaning and Plasma Chambers Control.
F e a t u r e A r t i c l e Feature Article EV-140 P, New Emission Spectroscopic Product for Semiconductor Endpoint, Cleaning and Plasma Chambers Control. Eric BLUEM, Jean-Philippe VASSILAKIS, Mickael
More informationMicrostructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley
Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2 Crystallographic
More informationChapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
More informationMetallization deposition and etching. Material mainly taken from Campbell, UCCS
Metallization deposition and etching Material mainly taken from Campbell, UCCS Application Metallization is back-end processing Metals used are aluminum and copper Mainly involves deposition and etching,
More informationECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:
ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: Fabrication of p-n junctions Contact Potential Things you should know when you leave Key Questions What are the necessary steps to fabricate
More informationInductively Coupled Plasma Etching of Pb(Zr x Ti 1 x )O 3 Thin Films in Cl 2 /C 2 F 6 /Ar and HBr/Ar Plasmas
Korean J. Chem. Eng., 19(3), 524-528 (2002) Inductively Coupled Plasma Etching of Pb(Zr x Ti 1 x )O 3 Thin Films in Cl 2 /C 2 F 6 /Ar and HBr/Ar Plasmas Chee Won Chung, Yo Han Byun and Hye In Kim Department
More informationStandard Operating Procedure: PECVD
Contents Hardware Description and Principle of Operation... 1 Procedure... 1 Emergency Stop... 3 Allowed Activities... 3 Disallowed Activities... 3 What to watch out for during operation... 4 Common Troubleshooting
More informationAtomic Layer Deposition (ALD)
Atomic Layer Deposition (ALD) ALD provides Uniform, controlled, conformal deposition of oxide, nitride, and metal thin films on a nanometer scale. ALD is a self limiting thin film deposition technique
More informationTest Patterns for Chemical Mechanical Polish Characterization
Dobek S: CMP Characterization 15th Annual Microelectronic Engineering Conference, 1997 Test Patterns for Chemical Mechanical Polish Characterization Stanley 3. Dobek Senior Microelectronic Engineering
More informationECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 7: CMOS Manufacturing Process Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last
More informationFigure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.
Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed
More informationBulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester,
More informationOverview of Dual Damascene Cu/Low-k Interconnect
ERC Retreat Stanford: New Chemistries & Tools for scco 2 Processing of Thin Films Overview of Dual Damascene Cu/Low-k Interconnect P. Josh Wolf 1,4 - Program Manager, Interconnect Div. josh.wolf@sematech.org
More informationA STUDY OF THE EFFECTIVENESS OF THE REMOVAL OF HYDROCARBON CONTAMINATION BY OXIDATIVE CLEANING INSIDE THE SEM.
A STUDY OF THE EFFECTIVENESS OF THE REMOVAL OF HYDROCARBON CONTAMINATION BY OXIDATIVE CLEANING INSIDE THE SEM. Neal Sullivan, Tung Mai, Scott Bowdoin* and Ronald Vane** A poster paper presented at Microscopy
More informationEvaluation and Evolution of Low κ Inter-Layer Dielectric (ILD) Material and Integration Schemes
Evaluation and Evolution of Low κ Inter-Layer Dielectric (ILD) Material and Integration Schemes Dr Eb Andideh Intel Corporation Logic Technology Development Contact: ebrahimandideh@intelcom 1 Disclaimer
More informationMEMS Surface Fabrication
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING MEMS Surface Fabrication Dr. Lynn Fuller webpage: http://people.rit.edu/lffeee Electrical and Microelectronic Engineering Rochester Institute
More informationToday s Class. Materials for MEMS
Lecture 2: VLSI-based Fabrication for MEMS: Fundamentals Prasanna S. Gandhi Assistant Professor, Department of Mechanical Engineering, Indian Institute of Technology, Bombay, Recap: Last Class What is
More informationFABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS
AND FABRICATION ENGINEERING ATTHE MICRO- NANOSCALE Fourth Edition STEPHEN A. CAMPBELL University of Minnesota New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Preface xiii prrt i OVERVIEW AND MATERIALS
More informationMEMS Fabrication. Beyond Integrated Circuits. MEMS Basic Concepts
MEMS Fabrication Beyond Integrated Circuits MEMS Basic Concepts Uses integrated circuit fabrication techniques to make mechanical as well as electrical components on a single chip. Small size 1µm 1mm Typically
More informationOerlikon PVD production solution for in-situ large scale deposition of PZT
Oerlikon PVD production solution for in-situ large scale deposition of PZT 2nd International Workshop on Piezoelectric MEMS Materials - Processes - Tools - Devices Lausanne, 06./07.09.2011 M. Kratzer,
More informationIsolation of elements
1 In an IC, devices on the same substrate must be isolated from one another so that there is no current conduction between them. Isolation uses either the junction or dielectric technique or a combination
More informationHBr Etching of Silicon
NNCI ETCH WORKSHOP Cornell University May 25, 2016 HBr Etching of Silicon Vince Genova CNF Research Staff CNF TCN, page 1 Characteristics of HBr based etching of Silicon HBr plasmas tend to be somewhat
More informationPower Vision Ltd. PV Research. Power Vision Ltd. Unit R2, Herald Park, Crewe, Cheshire, CW1 6EA, UK Tel:
Power Vision Ltd PV Research Power Vision Ltd Unit R2, Herald Park, Crewe, Cheshire, CW1 6EA, UK www.pvoptical.com Tel: +44 1270 253000 Flexible Whether it be fast AR coating onto temperature sensitive
More informationThin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high vacuum ~10-7 torr Removes residual gases eg oxygen from
More informationMANUAL FOR SPTS APS (DIELECTRICS ETCHER)
MANUAL FOR SPTS APS (DIELECTRICS ETCHER) To be read first: SPTS APS is an etcher dedicated to dielectrics (SiO2, Si3N4, glass types...). Dielectrics etching in AMS200 is no more CMi standard. AMS200 is
More informationElectroless Silver Plating as a Tool for Enhancement of Efficiency of Standard Industrial Solar Cells
Electroless Silver Plating as a Tool for Enhancement of Efficiency of Standard Industrial Solar Cells Outline Short introduction to ISC Konstanz Plating on standard industrial solar cells Electroless Ag-plating
More informationComparison of Different Sputter Processes for ITO: Planar DC versus Planar AC
Comparison of Different Sputter Processes for ITO: Planar DC versus Planar AC P. Sauer,H.-G.Lotz, A. Hellmich R. Kukla, J. Schröder Applied Films GmbH &,Co. KG, Alzenau, Germany Outline n n n n n n Current
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
More informationIsolation Technology. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
More informationAlternative Methods of Yttria Deposition For Semiconductor Applications. Rajan Bamola Paul Robinson
Alternative Methods of Yttria Deposition For Semiconductor Applications Rajan Bamola Paul Robinson Origin of Productivity Losses in Etch Process Aggressive corrosive/erosive plasma used for etch Corrosion/erosion
More informationCost Effective 3D Glass Microfabrication for Advanced Packaging Applications
Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications Authors: Jeb. H Flemming, Kevin Dunn, James Gouker, Carrie Schmidt, Roger Cook ABSTRACT Historically, while glasses have many
More informationPlasma-Enhanced Chemical Vapor Deposition
Plasma-Enhanced Chemical Vapor Deposition Steven Glenn July 8, 2009 Thin Films Lab 4 ABSTRACT The objective of this lab was to explore lab and the Applied Materials P5000 from a different point of view.
More informationSilicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology
Applied Surface Science 212 213 (2003) 388 392 Silicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology Marcus A. Pereira, José A. Diniz, Ioshiaki Doi *, Jacobus W. Swart
More informationChapter 4. UEEP2613 Microelectronic Fabrication. Oxidation
Chapter 4 UEEP2613 Microelectronic Fabrication Oxidation Prepared by Dr. Lim Soo King 24 Jun 2012 Chapter 4...113 Oxidation...113 4.0 Introduction... 113 4.1 Chemistry of Silicon Dioxide Formation... 115
More informationMARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices
Hitachi Review Vol. 57 (2008), No. 3 127 MARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices Tadashi Terasaki Masayuki Tomita Katsuhiko Yamamoto Unryu Ogawa, Dr. Eng. Yoshiki Yonamoto,
More informationProcess Improvement Projects May 2006 Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Process Improvement Projects May 2006 Dr. Lynn Fuller 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
More informationProcessing guidelines. Negative Tone Photoresist Series ma-n 2400
Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 2400 ma-n 2400 is a negative tone photoresist series designed for the use in micro- and nanoelectronics. The resists are available
More informationLecture #18 Fabrication OUTLINE
Transistors on a Chip Lecture #18 Fabrication OUTLINE IC Fabrication Technology Introduction the task at hand Doping Oxidation Thin-film deposition Lithography Etch Lithography trends Plasma processing
More informationSTUDY OF INFLUENCE OF IN SITU CLEANING PROCESS ON THE QUALITY OF PECVD SiO 2 / LPCVD POLYSILICON INTERFACE
STUDY OF INFLUENCE OF IN SITU CLEANING PROCESS ON THE QUALITY OF PECVD SiO 2 / LPCVD POLYSILICON INTERFACE Abstract ANA NEILDE R. DA SILVA, NILTON MORIMOTO, OLIVIER BONNAUD* neilde@lsi.usp.br - morimoto@lsi.usp.br
More informationChapter 5 Epitaxial Growth of Si 1-y C y Alloys
Chapter 5 Epitaxial Growth of Si 1-y C y Alloys 5.1 Introduction Traditionally, the incorporation of substitutional carbon into silicon and silicongermanium alloys during growth is of great interest for
More informationPlasma..TI'1eITI1 I.P.
Plasma..TI'1eITI1 I.P. RPPI..ICRTION NOTES PLASMA ETCHING OF SIUCON NITRIDE AND SIUCON DIOXIDE Silicon nitride and silicon dioxide thin films find e variety of uses in both semiconductor and nonsemiconductor
More informationAustralian Journal of Basic and Applied Sciences. Utilization of Oxygen Plasma For Plasma Ashing and Etching Process
AENSI Journals Australian Journal of Basic and Applied Sciences ISSN:1991-8178 Journal home page: www.ajbasweb.com Utilization of Oxygen Plasma For Plasma Ashing and Etching Process 1 Nereus Tugur Redationo,
More informationSupporting Information
Supporting Information The adhesion circle: A new approach to better characterize directional gecko-inspired dry adhesives Yue Wang, Samuel Lehmann, Jinyou Shao and Dan Sameoto* Department of Mechanical
More informationMicro/Nano Technology Center University of Louisville. Dry Etch Capabilities. NNCI Etch Workshop May 24-25, 2016
Micro/Nano Technology Center University of Louisville Dry Etch Capabilities NNCI Etch Workshop May 24-25, 2016 TRION METAL ETCHER MODEL: MINILOCK-PHANTOM III ICP/RIE Trion etcher uses 7 gasses for chemistry:
More informationEE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
More information行政院國家科學委員會補助專題研究計畫成果報告
NSC89-2215-E-009-104 89 08 01 90 07 31 Fabrication and Characterization of Low-Temperature Polysilicon Thin Film Transistors with Novel Self-Aligned Sub-Gate Structures NSC89-2215-E009-104 (FID) self-aligned
More informationHigh Rate low pressure PECVD for barrier and optical coatings
High Rate low pressure PECVD for barrier and optical coatings, Matthias Fahland, John Fahlteich, Björn Meyer, Steffen Straach, Nicolas Schiller Outline Introduction PECVD New developments magpecvd arcpecv
More informationA High Speed Surface Illuminated Si Photodiode. Using Microstructured Holes for Absorption. Enhancements at nm wavelength
A High Speed Surface Illuminated Si Photodiode Using Microstructured Holes for Absorption Enhancements at 900 1000 nm wavelength Supporting Information Yang Gao, Hilal Cansizoglu, Soroush Ghandiparsi,
More information