STUDY OF INFLUENCE OF IN SITU CLEANING PROCESS ON THE QUALITY OF PECVD SiO 2 / LPCVD POLYSILICON INTERFACE

Transcription

1 STUDY OF INFLUENCE OF IN SITU CLEANING PROCESS ON THE QUALITY OF PECVD SiO 2 / LPCVD POLYSILICON INTERFACE Abstract ANA NEILDE R. DA SILVA, NILTON MORIMOTO, OLIVIER BONNAUD* neilde@lsi.usp.br - morimoto@lsi.usp.br - bonnaud@univ-rennes1.fr L.S.I. - E.P.U.S.P. - São Paulo - S.P. - Brasil Fax: *G.M.V. - University of Rennes - France The influence of in situ wafer cleaning process has been studied in the quality of TEOS-PECVD silicon oxide deposited in a home made cluster tool system. We used MOS capacitor structure with and without polysilicon layer to perform the C-V measurements. The results showed that in situ cleaning process cause damages in the silicon surfaces. Introduction Deposition of silicon dioxide films at low temperature by the Plasma Enhanced Chemical Vapor Deposition (PECVD) has large applications on silicon integrated circuits technology. [1-4] Silicon oxide deposition from tetraethylorthosilicate (TEOS) provides excellent conformality, which is not achievable when silane is used as silicon source. [5] Nevertheless, poor electrical characteristics is reported for silicon oxide films deposited by TEOS-PECVD; due to the problems related with process parameters control as pressure, temperature, TEOS/O 2 ratio, etc. [6-8]. Also, the Si/SiO 2 interface plays a role in the electrical behavior of SiO 2 films [3,7]. To improve the interface Si/SiO 2 quality, we used two in situ cleaning process before the TEOS silicon oxide deposition. This paper shows the influence of these cleaning process in the electrical behavior of MOS capacitors. Experimental Silicon substrates used for TEOS PECVD oxide deposition were 51 mm, n-type <100>; 1-20 Ω.cm. Figure 1 shows the MOS capacitors structures used in this experiment. Al Undoped poly-si SiO 2-TEOS Si-n Al SiO 2-TEOS Si-n Figure 1: Capacitors structures used in this experiment.

2 It was used the follows wafer cleaning processes: Normal - conventional RCA cleaning. CF 4 +O 2 - in situ cleaning process using CF 4 -O 2 plasma in the following conditions: 100 sccm CF 4, 20 sccm O 2, work pressure 0.5 Torr, RF Power 100 W during 1 min. O 2 - in situ treatment of the silicon substrate using O 2 plasma in the following conditions: 20 sccm O 2, work pressure 0.5 Torr, RF Power 100 W during 1 min. Table I shows the deposition process parameters used in TEOS-PECVD silicon oxide deposition carried out in a home made cluster tool system [4]. Table I: Deposition process parameters used for TEOS PECVD silicon oxide deposition. RF power (W) 500 Temperature ( C) 360 Distance between electrodes (mm) 15 Oxygen flux (sccm) 200 TEOS flux (sccm) 10 Process pressure (Torr) 8 Thickness (nm) 50 The TEOS PECVD silicon oxide thickness and refractive index measurements were made in a Rudolph Research ellipsometer model Auto-El-NIR3. Before TEOS PECVD deposition process, it was made a chamber wall cleaning process using a plasma of a mixture of 100 sccm CF 4 and 20 sccm O 2. This procedure ensures the same initial conditions for all deposition process. The process for polysilicon was carried out in a home made LPCVD (Low Pressure CVD) system initially in the following conditions: work pressure1,5 Torr, 50 sccm SiH 4, 550 C, deposition rate of 5 nm/s to have an amorphous film. After the deposition process, the amorphous thin film was annealed in the same furnace, during 12 hs at 600 C in vacuum, to obtain a polycrystalline layer. To remove the polysilicon layer from the backside of the wafer a SF 6 plasma etching process has been performed in the following conditions 20 sccm SF 6, 30 mtorr, 50 W, 1 min. The evaporated Aluminum thin film had ~300 nm thick. The MOS capacitors (area=2,25 µm 2 ) was patterned by conventional lithography process. Capacitance Voltage- High Frequency (CV-HF) measurements were performed in a HP CV-4140 analysis station.

3 Results and Discussion Figure 2 shows the CV-HF curves obtained from the capacitors structures. Figure 2: CV-HF curves from SiO 2 -TEOS/Al and SiO 2 -TEOS/Si-poli/AL structures

4 Table II shows the electrical parameters (C fb -Flat Band Capacitance, V fb -Flat Band Voltage and N ss -interface charge density), calculated from the CV-HF curves. Table II: Electrical parameters calculated from the CV-HF curves Surface Sample SiO 2 thickness Refractive C fb (pf) N ss V fb (V) preparation measured (nm) Index (charge/cm 2 ) Normal F1(poly) E F3(Al) E CF 4 +O 2 F4(poly) E11-1 F6(Al) E O 2 F7(poly) E F9(Al) E Figure 3 shows a histogram comparing the N ss values for each wafer cleaning procedure The highest N ss value was obtained for sample F9, that was treated with in situ O 2 plasma. The Al/SiO 2 structure showed higher N ss values compared with SiO 2 /Poly/ Al. 5,0E+11 Nss (charge/cm -2 ) 4,0E+11 3,0E+11 2,0E+11 1,0E+11 poly-si Al 0,0E+00 Normal CF4+O2 O2 Figure 3: Histogram comparing the Nss values obtained for each wafer cleaning procedure. The results observed in figure 3 related to the differences between capacitors structures can be attributed to the two thermal steps which the SiO 2 films were submitted during polysilicon deposition. SiO 2 films deposited by CVD and submitted to thermal treatment for several hours can bear modifications on the film structure and composition and consequently the electrical behavior of these films are changed [4,7,9] also when TEOS is used as a Si precursor, some radicals like Si-OH and C-O can be incorporated into the film bulk. [10]

5 Thermal processes can either eliminate the Si-OH and C-O radicals that are trapped in the film during TEOS-PECVD SiO 2 deposition process and/or modify the SiO 2 structure. However, this process depends on temperature, time of thermal treatment and on radical nature. These mechanisms still not well understood [9-11]. We can conclude that the lower N ss value obtained for the polysilicon capacitors should be due to the thermal steps during LPCVD polysilicon deposition process. The quality and/or the condition of the silicon wafer surface can influence the deposition process and the oxide quality. [3,7] Silicon wafer cleaned with conventional RCA process with final dip in HF solution, presents mainly Si-H on the surface. This surface can improve the nucleation sites of the deposition process and can lower the interface charges [12]. O 2 plasma is used before the PECVD-TEOS SiO 2 deposition, to grow a thin oxide layer over the wafer surface. In this case, we can improve the quality of the interface Si/SiO 2. However, we also increase the density of the impurities damage in the Si/SiO 2 interface. In our case these impurities increased the Nss values as observed in the figure 3. [3,8] A CF 4 -O 2 plasma treatment could reduce the influence of the native oxide producing a cleaner surface. However, CF 4 plasma also produce organic polymers which can be deposited over the silicon wafer. These residues act as electrical charges in the Si/SiO 2 interface. Plasma treatments performed over silicon wafer surfaces can also increase the roughness by ions bombardments, which agrees with the results. [13] Conclusions We showed that the SiO 2 film structure and electrical behavior are modified by thermal treatments. The thermal steps used during the polysilicon deposition, improve the electrical behavior of the SiO 2 -TEOS films The silicon wafer surface quality is influenced by the cleaning treatment that are performed before SiO 2 films deposition. We report that the regular chemical cleaning process (RCA) is better than the in situ plasma treatments Acknowledgments We are grateful to David Briand for the LPCVD polysilicon deposition, to Victor Sonnenberg for the discussions on electrical measurements, to Carlos Carvalho and Gilberto Nishioka for the SiO 2 deposition processes.

6 This work was supported by Finep, FAPESP, and CNPQ. References 1. K.Maeda and S.M. Fisher; CVD TEOS/O 3 Development history and applications ; Solid State Technology, June, 1993, p C.Y.Lu, et al; The Chalenge of the ULSI Semiconductor Memory Interconnection Technology ; Proceedings of the Materials Research Society Symposium, vol.427, april S.K.Ray, et al; Electrical Properties of Silicon Dioxide Deposited at Low Temperature by Metal-Organic Microwave Plasma CVD Technique Electronics Letters, July, 1990, vol.26 n 14, p N.I.Morimoto and J.W.Swart, in Proc. V Symp. Rapid Thermal and Integrated Processing, MRS, Vol 429, p.263, San Francisco, T. Sorita, et al; The Formation Mechanism and Step Coverage Quality of Tetraethylorthosilicate-SiO 2 Films Studied by the Micro/Macrocavity Method, J. Electrochem. Soc. Vol. 140, n 10, october 1993, p C.Pavalescu et al.; High Frequency C-V Investigation of Metal-Oxide-Semiconductor Capacitors Prepared by Low Temperature subatmospheric Pressure Chemical Vapor Deposition of SiO 2 Films on Silicon Substrates ; Thin Solid Films, 217(1992), W.J.Patrick, et al.; Plasma-Enhanced Chemical Vapor Deposition of Silicon Dioxide Films Using Tetraethoxysilane and oxygen: Characterization and Properties of Films. J. Electrochemical Soc., vol.139, n 9,sep.1992, p A.C. Calrson, et al.; Deposition Method to Control Plasma-Enhanced Chemical Vapor Deposition tetraethylorthosilicate Oxide Charge ; J. Electrochem. Soc., vol.140, n 3, march 1993, p P. Lange, et al; Electrical and Structural Properties of Ultrathin SiO 2 Gate Dielectrics Prepared Under Various Conditions ; J. Electrochem. Soc., vol.139, n 5, may 1992, p S.C. Deshmukh, et al; Investigation of Low Temperature SiO2 Plasma Enhanced Chemical Vapor Deposition ; J.Vac.Sci.Technol.B 14(2), mar/apr, 1996; p H.J. Schliwinski, et al; Thermal Annealing Effect on the Mechanical Properties of Plasma-Enhanced Chemical Vapor deposition Silicon Oxide Films ; J. Electrochem. Soc., vol.139, n 6, june 1992, p S.G. dos Santos Filho, et al; The Deposition and Removal of Surfaces Contaminants from Silicon Wafer by Means of a Diluted HF Dip Followed or not by an Isopropyl Alcohol Boil ; annais of the IX Simposium of the Brasilian Microelectronics Society, Rio de Janeiro, 1993, p A.K.Stamper, et al.; Plasma-induced gate oxide charging issues for sub-0,5µm complemetary metal-oxide-semiconductor technologies ; J.Vac.Sci.Technol.B 13(3), jul/aug. 1995, p