Using Mass Metrology for Process Monitoring and Control During 3D Stacking of IC s
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1 Metryx Copyright 1
2 Using Mass Metrology for Process Monitoring and Control During 3D Stacking of IC s SEMATECH 3D Interconnect Workshop 11 th July 2012 Metryx Copyright 2
3 Mass Metrology Less Mass More Mass All process steps create a wafer mass change This mass change reflects all aspects of process performance within a wafer Metryx Mass Metrology provides passive data collection on product wafers to assess process performance Metryx Copyright 3
4 Mass Metrology Etch Less Mass More Mass All process steps create a wafer mass change This mass change reflects all aspects of process performance within a wafer Metryx Mass Metrology provides passive data collection on product wafers to assess process performance Metryx Copyright 4
5 Mass Metrology Deposition Less Mass More Mass All process steps create a wafer mass change This mass change reflects all aspects of process performance within a wafer Metryx Mass Metrology provides passive data collection on product wafers to assess process performance Metryx Copyright 5
6 Measurement Capability H Ti 2.5Ǻ TiN 2.5Ǻ Cr 1.6Ǻ Co 1.3Ǻ CoSi 2.6Ǻ CoWP 1.2Ǻ Ni 1.3Ǻ NiSi 5.0Ǻ Cu 1.3Ǻ Al 4.2Ǻ AlCu 3.8Ǻ AlN 3.5Ǻ Si 4.9Ǻ SiO2 4.9Ǻ SiN 4.5Ǻ SiON 4.7Ǻ SiOC 7.5Ǻ Li Be B C N O F Ne Na Mg Al Si P S Cl Ar K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn He Zr 1.7Ǻ Mo 0.6Ǻ Ag 1.1Ǻ Hf 0.9Ǻ HfO2 1.2Ǻ Ta 0.7Ǻ TaN 1.3Ǻ W 0.6Ǻ Pt 0.5Ǻ Au 0.6Ǻ 1σ thickness repeatability for blanket films on 200mm & 300mm wafers Thickness sensitivity improves with patterned wafers and increased surface area Atomic level accuracy maintained (or improved) with smaller feature sizes and more complex structures Metryx Copyright 6
7 Mass Weight Weight Measurement Unstable, irreproducible, not designed for semiconductor measurement use Mass Measurement Load-cell utilising complex force measurement Real-time corrections for internal and external forces influencing measurement Fully automatic wafer handling and host communication compliant Metryx Copyright 7
8 3D IC Metrology Challenges TSV Formation M & I Challenges Via CD, depth & profile (optical/mass/interferometry/) Etch defects/residues (BF- DF pattern inspection) Via Fill M & I Challenges Barrier and Seed continuity (Electrical) Void detection in filled TSV s (Mass/Electrical) Temporary Carrier Processing M & I Challenges Glue layer void/defect & thickness variations (optical (IR/SAM)) Thinning process M & I Challenges Wafer thickness and shape (Optical(IR)/capacitance) Post thinning/recess etch backside defects ( Optical BF/DF) Cu TSV co-planarity (Interferometry/confocal) Edge defects (optical ) Debonding I challenges Thin wafer inspection on FFC(BF/DF inspection) Thin die inspection on FFC (BF/DF inspection) Dicing and Stacking M& I challenges TSV module Wafer thinning module Debonding and stacking module Die alignment (Optical (IR) X-ray ) Underfill integrity (X-ray) Edge boundary violation (BF- pattern recognition software) Metryx Copyright 8
9 3D IC Metrology Challenges TSV Module Wafer Thinning Module Via CD, depth & profile Etch defects/residues Barrier and Seed Via filling Void detection in filled TSV s Glue layer void & thickness Wafer thickness & shape Post thinning/recess etch Cu TSV co-planarity Edge defects Debonding & Stacking Module Thin wafer inspection Thin die inspection Die alignment Underfill integrity Edge boundary violation Metryx Copyright 9
10 TSV Etch Mass vs Depth 30 Via Depth (ums) Via Depth 5 um Diameter Vias PoR 25 µm Depth 5 0 y = x x R 2 = Mass Loss (mg) Metryx Copyright 10
11 TSV Etch Mass is used as a monitor of etch process stability Out of spec lots usually have deeper TSV s etch Depth variations in TSV has implications in the TSV grinding and reveal process Metryx Copyright 11
12 Liner/Barrier/Seed Highly topographical layer Difficult to measure optically as most of film is on sidewalls, or bottom of features Surface area increase improves sensitivity of mass change. Etch variations produce surface area variations so mass after TSV etch and mass of L/B/S are related. Mass (ug) Sidewall Top Surface 1:1 1 5:1 2 10:1 3 20:1 4 50:1 5 Aspect Ratio (AR) Metryx Copyright 12
13 Via Filling and Voids Theoretical calculations reveal possibility to detect voids in Cu vias Assuming void width = via diameter More than 6600 TSVs with 100nm height voids need to be present to be detected (50µ x 5µ TSV) Metryx Copyright 13
14 Via Filling and Voids Wafer TSV etch Liner B/S Cu fill Anneal CMP Metryx Metryx Metryx Metryx Metryx Metryx Metryx Mass of wafers with voids is less than mass of wafers without voids Difficult to separate mass of voids from mass of over etch, or over burden Metryx Copyright 14
15 CMP Stability The correlation between the mass added (Barrier + Fill) is very well correlated to the mass removed during CMP. Therefore the CMP is well controlled. Over or underpolish in the CMP results in data scatter. The over and under polish splits are clearly distinguished. Mass Removed Deviation (mg) CMP (PoR) Outliers Linear (CMP (PoR)) (M n+3 - M n+1 ) (M n+4 - M n+3 ) Over Polish Under Polish y = x R 2 = Mass Deposited Deviation (mg) Metryx Copyright 15
16 Via Filling and Voids Wafer TSV etch Liner B/S Cu fill Anneal CMP Metryx Metryx Metryx Metryx Metryx Metryx Metryx Mass change of wafers with voids is less than mass change of wafers without voids The difference is related to the loss of plating liquid from the void during the anneal process Mass can therefore indicate the presence of voids in the TSV Metryx Copyright 16
17 Wafer Thickness Measurement Wafer thickness by micrometer Correlates well with mass data Carrier Mass vs Thickness y = x R 2 = Wafer thickness by acoustic reflection data Correlates well with mass calculated thickness Mass (g) Thickness (um) Mass metrology provides average wafer thickness quickly (<60s/wafer) compared to micrometer (manual) and acoustic reflection probing (time consuming) methods Metryx Copyright 17
18 Summary Mass Metrology is an effective technique for monitoring process excursions during TSV etch Barrier/Seed Deposition Cu plating Wafer grinding Acknowledgements Co Authors Sandip Halder, Peter leunissen, Andy Miller, Mirielle Maenhoudt, Eric Beyne IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Adrian Kiermasz, Gary Ditmer Metryx, 1240 Park Avenue, Aztec West, Bristol, UK Additional thanks to Augusto Redolfi, Eddy Kunnen, Sarasvathi Thangaraju, Harold Philipson Metryx Copyright 18
19 Metryx Metryx Copyright 19
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