AS MOORE predicted in 1965, silicon chips are getting

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1 IEEE TRANSACTIONS ON ADVANCED PACKAGING 1 Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps Cheryl S. Selvanayagam, John H. Lau, Fellow, IEEE, Xiaowu Zhang, S. K. W. Seah, Kripesh Vaidyanathan, and T. C. Chai Abstract Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper ( C) is a few times higher than that of silicon ( C). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO 2 ), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore s (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as C. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps. Index Terms Copper, modeling, strain, stress. Manuscript received April 02, 2008; revised March 18, This paper was recommended for publication by Associate Editor A. Chandra upon evaluation of the reviewers comments. The authors are with the Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR), Singapore ( cheryls@ime.a-star.edu.sg). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TADVP Fig. 1. Package incorporating TSV interposer. Inset shows details of TSV. I. INTRODUCTION AS MOORE predicted in 1965, silicon chips are getting larger while incorporating a higher pin count and smaller bump pitch. Unfortunately, conventional substrates, e.g., BT (bismaleimide triazine) cannot support these fine-pitched silicon chips. Hence, there is a need for an intermediate substrate to redistribute the large array of fine-pitched pads on the chip to fewer, relatively large-pitched pads on the BT substrate. One of the major applications of the through silicon vias on silicon substrate is to serve as this intermediate substrate. One such package structure with a detailed schematic of the through silicon via (TSV) is shown in Fig. 1. The fabrication steps which subject it to various temperature cycles coupled with the large difference in coefficients of thermal expansion of copper and silicon results in a TSV which is susceptible to ring cracking and delamination. The other application for the TSV is for use in chip stacking as the interconnect length is reduced compared to perimeter wire bonding. Several authors have turned to finite element modeling for insight on the stress state in a filled TSV. While some authors were concerned with the stresses induced by the different processes involved in making a TSV, (i.e., etching, coating, plating, etc.) [1], [2], others focused on the materials [1], [3] or design aspects [4] of the TSV. By far, the most comprehensive study on the stress state in a TSV was carried out by Takana et al. [5] who investigated not only the effect of via size on thermal mismatch, but also possible cracking due to loading force during the stacking process and bump reliability under thermal fatigue. Unfortunately, these papers focus on the mechanical reliability of specific designs and do not provide any design guidelines for the design of reliable TSVs. This paper will provide these design guidelines by first assessing and analyzing the stress state /$ IEEE

2 2 IEEE TRANSACTIONS ON ADVANCED PACKAGING of a single TSV to determine the main contributor of failure at a region localized around the via. Subsequently, the accumulated effect of the localized thermal strains around each TSV (i.e., the global effect), which results in mismatch, on a larger scale, between the interposer and chip, will be analyzed. The software ABAQUS version was used for all the simulations carried out in this paper. II. LOCAL THERMAL EXPANSION MISMATCH Mechanical modeling of any structure for the electronics industry requires knowledge of the final service conditions and accurate material properties. Certain aspects of the structure such as complex geometry and thin compliant layers can be simplified or assumed negligible to reduce computational time without significantly affecting the results. In the TSV, the presence of materials with different coefficients of thermal expansion (CTE) will induce thermal mismatch stresses and strains during temperature cycling. In order to assess the possibility of failure, the following models were analyzed. First, a simple axi-symmetric model of silicon with a core filled with copper was considered. This was followed by a model of silicon with a core plated with a thin layer of copper instead of completely filled. The effect of the redistribution layer (RDL) was then taken into account for both the above-mentioned cases to assess its reliability. Finally, a diagonal slice model of a chip mounted onto a silicon interposer with TSV was used to determine the effect of the presence of TSV to the reliability of the corner microbump during temperature cycling. A. Modeling of Copper-Filled TSV For determining thermal stress in a TSV, the following assumptions were made. 1) Since the layer of tantalum (1 k ) is much thinner than the dielectric layer (1 m), its effect is negligible. 2) The redistribution layer is very thin and therefore negligible. 3) Silicon and silicon oxide are not strained beyond their elastic zone. 4) Copper undergoes elastic deformation, followed by plastic deformation. 5) The silicon interposer with TSV is stress-free at 125 C. The simplified diagram of the TSV based on the above assumptions is shown in Fig. 2(a). One quarter of this was modeled in an axi-symmetric simulation. The boundary conditions used and the mesh at the critical interfaces are shown in Fig. 2(b) and (c), respectively. Note that directions 1 and 2 the radial and axial directions, respectively. A static temperature ramp down analysis from 125 Cto C was carried out to simulate the maximum strained state. The modeling matrix and material properties used are shown in Tables I and II. During the temperature cycling of the TSV, each temperature ramp up results in copper expanding more than 5 times as much as silicon and more than 10 times as much as silicon oxide. The deformation resulting from heating from C to 125 C and cooling from 125 Cto C exaggerated 100 times is shown in Fig. 3(a) and (b) for better visualization of what happens. From Fig. 3(a), it is clear that the silicon oxide layer is Fig. 2. (a) Diagram of simplified TSV. (b) Quarter model of TSV with applied boundary conditions. (c) Mesh of critical region. TABLE I MODELING MATRIX TABLE II MATERIAL PROPERTIES highly strained as it is dragged along by the axial expansion of the copper and compressed by the radial expansion of copper. This strain however is largely not transferred to the bulk of the silicon, as silicon is much stiffer than copper and silicon oxide. Conversely, during temperature ramping down also a high strain is induced on the material near the interface indicated by points A and B. There are two critical points where failure may occur. Firstly, failure could occur due to the tearing action during contraction, at the interface between copper and silicon oxide [points A and B in Fig. 2(c)]. Secondly, cracking of copper or silicon oxide could occur at the midplane of the TSV [points C and D in Fig. 2(c)]. For the simulations carried out, the radial stress at

3 SELVANAYAGAM et al.: NONLINEAR THERMAL STRESS/STRAIN ANALYSES OF COPPER FILLED TSV 3 Fig. 4. Radial stress ( ) at critical corner for (a) copper (point A) and (b) silicon oxide (point B) in filled vias. Fig. 3. Deformation in TSV exaggerated points A and B, and the axial strains at C and D were monitored to give an indication of the stress and strains causing delamination and cracking in those regions. The radial stresses in the copper and silicon oxide at the critical corner plotted against the diameter of the via for different aspect ratios are shown in Fig. 4. It is observed that the radial stress increases linearly with the diameter of the via, with a steeper increase in vias with larger aspect ratios. This is indicated by the slopes of the graphs marked on Fig. 4. Though a larger diameter of copper via induces a similar thermal strain, the deformation in copper is increased, resulting in a larger strain and therefore larger stresses. The stress in silicon oxide is greater than that in copper for all cases due to its higher elastic modulus. In addition, the change in stress due to varying of aspect ratio effect is most evident in vias with smaller diameters approximately 15% increase in radial stress is observed in a via of m compared to 2% increase for m. The axial strains at points C and D in copper and silicon oxide are plotted on the graphs in Fig. 5. As expected due to their close proximity, the strains in copper and silicon oxide are identical for all aspect ratios and diameters. At an aspect ratio of 1, the axial strains are largest. As the aspect ratio increases, the strain decays. Beyond an aspect ratio of 5, axial strain is no longer dependant on aspect ratio. As the axial strain values are below the elongation values of copper and silicon oxide obtained from literature to be 2% [6] and 30% [7], respectively, cracking on the mid-plane is not expected. The widened range of radial stress in the case of aspect ratio of 1 (Fig. 4) and the convergence of axial strain beyond an as- Fig. 5. Axial strain (" filled vias. ) at mid-plane for (a) copper and (b) silicon oxide in pect ratio of 5 (Fig. 5) are caused by the proximity of the free edge on top of the via to the fixed edges (the axis and the midplane) which constraints the deformation. Fig. 6 shows the axial strain contours of vias of various aspect ratios. Vias with an aspect ratio larger than 7 experience large strains at the top of the via, instead of more distributed strains seen in vias with smaller aspect ratios. B. Modeling of Unfilled TSV In addition, the case of an unfilled TSV was also modeled in order to assess its mechanical behavior in comparison with

4 4 IEEE TRANSACTIONS ON ADVANCED PACKAGING Fig. 7. (a) Diagram of TSV not filled with copper. (b) Quarter model of TSV with applied boundary conditions. (c) Mesh of critical region. Fig. 6. Axial strain (" ratios. ) contours of filled TSV of D=25at various aspect a filled via. The diagram, finite element model and mesh for this unfilled via is shown in Fig. 7(a), (b), and (c), respectively. The modeling matrix and material properties used are shown in Tables I and II. Note that the thickness of the copper layer modeled is 3 m for all cases. In the case of the unfilled via, the relationship between the diameter and the radial stress is no longer linear as shown in Fig. 8. It is observed that radial stress is highly dependant on via diameter. The little difference in radial stress between the extreme aspect ratios at the smaller diameter (5%) is reduced to almost 0% in the case of the larger diameters in both copper and silicon oxide. Radial stress increases linearly with increasing diameter in filled vias (Fig. 4). In unfilled vias, however, an opposite trend is observed. This is because in the filled via, as copper contracts it pulls the silicon oxide and silicon, which contract less, inwards. A larger via diameter with its larger volume of copper results a larger thermal mismatch and hence a higher state of stress. In the unfilled via, the copper is unconstrained on the inner surface of the via. As a result, the copper is free to move inward to release the normal stress. In the unfilled via, there are two mechanisms at work to decrease the stress state decreased volume of copper and unconstrained surface area. It was found that the ratio of these parameters has a linear Fig. 8. Radial stress ( ) at critical corner for (a) copper (point A) and (b) silicon oxide (point B) in unfilled vias. (c) Linear relationship with (R 0 r )=2r. relationship with the radial stress in the unfilled via as shown in Fig. 8(c). A large reduction in stress results when replacing a filled via with an unfilled one. For the same aspect ratio and diameter,

5 SELVANAYAGAM et al.: NONLINEAR THERMAL STRESS/STRAIN ANALYSES OF COPPER FILLED TSV 5 Fig. 9. Axial strain (" ) at mid-plane for (a) copper (point C) and (b) silicon oxide (point D) in unfilled vias. substituting the filled via with the unfilled one can reduce the radial stress by 1.8 to 4.4 times in copper and by 1.8 to 2.4 times in silicon oxide. The largest reductions in stress were found to occur in larger vias of smaller aspect ratios. The reduction in axial strain in the unfilled vias compared to the filled ones is most pronounced at smaller aspect ratios (shown in Fig. 9). At these aspect ratios, smaller diameters have larger strains. The axial strain contours shown in Fig. 10 indicate that the larger diameters have larger length of silicon to constrain the copper contraction. C. Modeling Details of TSV With Redistribution Layer In TSV fabrication, once the via is made by deep reactive ion etching (DRIE), a thin passivation layer of silicon oxide is deposited on the silicon at high temperature. This is followed by via filling through electroplating. Next the wafer undergoes chemical mechanical polishing (CMP) and another thin passivation layer of silicon oxide is then deposited at high temperature. The copper in the RDL is then sputtered at room temperature. Finally, the entire structure undergoes annealing to remove any residual stress induced by the deposition processes. As a result, residual stress is assumed negligible in this modeling work. The redistribution layer in the model would simulate the real situation to a larger extent as it would include the possibility of cracking of the RDL. Hence, its effect in both the filled and unfilled via was studied. A schematic drawing of the cross-section of the filled via, the one-quarter finite element model and the mesh at the critical location in shown in Fig. 11. The unfilled via with RDL model is simply the model in Fig. 7 with an RDL layer. For the model including the RDL layer, failure is expected to occur in the RDL layer at a 45 from the surface of the copper via. Hence, the strain along directions 1 and 2 have been resolved to determine the diagonal strain denoted by along the Fig. 10. Axial strain (" ) contours showing undeformed and deformed states in copper of unfilled TSV for H=D =1. Fig. 11. (a) Diagram of simplified TSV with RDL. (b) Quarter model of TSV with applied boundary conditions. (c) Mesh of critical region.

6 6 IEEE TRANSACTIONS ON ADVANCED PACKAGING Fig. 12. Diagonal strain (" = " ) at critical location for (a) copper (point A) and (b) silicon oxide (point B) in filled vias with RDL. Fig. 13. Diagonal strain (" = " ) at critical location for (a) copper (point A) and (b) silicon oxide (point B) in unfilled vias with RDL. -direction (indicated in Fig. 11) was calculated using (1). At, there is no cosine term The diagonal strain at point A and B are plotted in Fig. 12 for the filled via and Fig. 13 for the unfilled via. As shown in the figure, there is a linear relationship between the diagonal strain and the diameter of the via. As expected, the strain in the copper is lower than that in the silicon oxide. In the unfilled via with the RDL, diagonal strains decrease with diameter. This is because the ratio of t/d is smaller resulting in relatively less expansion in copper. The axial strain at point C for the filled and unfilled vias is shown in Fig. 14 for the model with RDL. The axial strain curves at point D are not shown as they had identical axial strains as the copper. Note that these curves are very similar to those in Fig. 5(a) and Fig. 9(a), which show the axial strains in copper in the model without the RDL. Hence, for the purpose of determining axial strain, the RDL may be ignored. III. GLOBAL THERMAL EXPANSION MISMATCH (1) A. Modeling Solder Ball Fatigue due to Global Thermal Mismatch The effective CTE of the silicon interposer is higher when it contains copper in the form of filled TSVs. As a result, on temperature cycling, the interposer will expand and contract more than the chip, resulting in a fatigue loading on the solder joint. The effect of this global mismatch on the reliability of the solder bump was investigated in the following simulations. Fig. 14. Axial strain (" ) at mid-plane for copper (point C) in (a) filled and (b) unfilled models with RDL. The global model consisting of a chip assembled onto a silicon interposer containing TSVs was made to undergo three cycles of temperature cycling between C to 125 C. A diagonal

7 SELVANAYAGAM et al.: NONLINEAR THERMAL STRESS/STRAIN ANALYSES OF COPPER FILLED TSV 7 Fig. 16. (H). Creep strain energy density per cycle variation with interposer height Fig. 15. (a) Diagram of global model. (b) Diagonal slice model with applied boundary conditions. (c) Mesh of critical region. Fig. 17. Creep strain energy densities for three interposer heights. TABLE III MODELING MATRIX The creep properties of 95.5Sn3.8Ag0.7Cu solder were assigned using the Garofalo-Arrhenius creep law shown below where the material constant A was s, B was 0.037E-6 Pa, n was 5.1 and Q was 54.3 kj/mol [8] (2) TABLE IV MATERIAL PROPERTIES slice of this model was considered for computational efficiency. A schematic diagram of the model, the applied boundary conditions and the mesh of the critical region are shown in Fig. 15. The modeling matrix, material properties of copper and solder are shown in Tables III and IV, respectively. Results of the analysis indicate that as the height of the interposer increases, the creep strain energy density in the solder increase as shown in Fig. 16. For interposer heights of , the maximum strain energy density occurs at the top of the solder joint. On the other hand, for interposer heights of , the maximum strain energy occurs at the bottom surface of the solder joint. Maximum strain energy position is transferred to the bottom when the expansion of the interposer begins to exert a shearing load on the solder. This effect can be seen in Fig. 17 where the solder joint on the shortest interposer has much reduced strain energy density at its bottom surface. The use of underfill reduces the inelastic strain energy density by 4 times. Increasing the pitch results in a decreasing of the creep strain energy density as shown in Fig. 18. This is a result of the decreased copper content and hence decreased mismatch between the silicon chip and the silicon interposer with TSVs. Fig. 19 shows the creep strain energy for two different pitches decreases to almost the similar values when used with underfill.

8 8 IEEE TRANSACTIONS ON ADVANCED PACKAGING 4) Silicon oxide dielectric layer is in a higher state of stress compared to copper as a results of its lower CTE compared to copper. Hence extra care should be taken during the dielectric-layer fabrication to ensure a high quality TSV. Fig. 18. Creep strain energy density per cycle variation with via pitch (P). Fig. 19. Creep strain energy density per cycle variation with aspect ratio (H/D). IV. CONCLUSION AND RECOMMENDATIONS Nonlinear stress/strain analyses of the local and global thermal mismatches have been presented. The local stress/strain analyses considered the effect of not only the aspect ratio but also the unfilled via as opposed to the one completely filled with copper. The global model was used to quantify the life (via the creep strain energy density per cycle) of the micro-solder joints which interconnect the TSV interposer and the chip. Some important results and recommendations are summarized in the following. A. Local Thermal Expansion Mismatch 1) For all the TSVs considered, in general, above an aspect ratio (thickness/diameter) of 5, there is little dependence of stress and strain on the aspect ratio of the via. 2) For the perfect TSV structures modeled, failures at the interfaces of the TSV (due to the local thermal expansion mismatch among the Si, SiO, and Cu) are unlikely as the strains in these elements are not large enough to cause failures. 3) The imperfections that could arise during fabrication (such as the poor bonding between interfaces and the presence of asperities which act as points of stress concentration) compounded with the stresses due to the local thermal expansion mismatch could result in failure. Thus, it is recommended that the TSV structures be fabricated as perfectly as possible. B. Global Thermal Expansion Mismatch 1) The increased content of copper in the TSV interposer increased its effective CTE. Hence, the global thermal mismatch between the Si-chip and the Cu-filled TSV-interposer could be very large and the micro-solder joints connecting them are subjected to very large stresses and strains, especially the corner ones. 2) For a given TSV pitch and diameter, the thickness of the Cu-filled Si-interposer plays a very important role. The larger the thickness, the larger the creep strain energy density per cycle, and thus the shorter the thermal-fatigue life of the micro-solder joints. 3) For a given TSV thickness and diameter, the pitch of the Cu-filled Si-interposer also plays an important role. The larger the pitch, the smaller the creep strain energy density per cycle, and thus the longer the thermal-fatigue life of the micro-solder joints. 4) Underfill prolongs the life of the micro-solder joints by cementing the Si-chip to TSV-interposer. This reduces the global thermal expansion mismatch and decreases the stresses and strains in the micro-solder joints. It has been found that with the presence of underfill, the maximum creep strain energy density per cycle acting at the corner micro-solder joint can be reduced as much as 4 times. 5) Based on the cases considered, underfill is recommended, especially for thick and fine-pitch Cu-filled Si-interposer. REFERENCES [1] B. Wunderle, R. Mrossko, O. Wittler, E. Kaulfersch, P. Ramm, B. Michel, and H. Reichl, Thermo-mechanical reliability of 3D-integrated microstructures in stacked silicon, in Mater. Res. Soc. Symp. Proc., 2007, p [2] J. U. Knickerbocker et al., Development of next generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection, IBM J. Res. Develop., vol. 49, no. 4/5, pp , [3] P. A. Miranda and A. J. Moll, Thermo-mechanical characterization of copper through-wafer interconnects, presented at the Electron. Compon. Technol. Conf., San Diego, CA, [4] S. Burkett, L. Schaper, T. Rowbotham, J. Patel, T. Lam, U. Abhulimen, D. D. Boyt, M. Gordon, and T. Cai, Material aspects to consider in the fabrication of through-silicon vias, in Mater. Res. Soc. Symp. Proc., 2007, pp [5] N. Takana, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, and K. Takahashi, Mechanical effects of copper through-vias in a 3D die-stacked module, in Electron. Compon. Technol. Conf., San Diego, CA, 2002, pp [6] D. T. Read, Y. W. Cheng, and R. Geiss, Morphology, microstructure, and mechanical properties of a copper electrodeposit, Microelectron. Eng., vol. 75, pp , [7] Z. Cao and X. Zhang, Measurement of stress-strain curves of PECVD silicon oxide thin films by means of nanoindentation, in Mater. Res. Soc. Symp. Proc., 2007, vol [8] H. L. J. Pang, B. S. Xiong, C. C. Neo, X. R. Mang, and T. H. Low, Bulk solder and solder joint properties for lead free 95.5Sn-3.8Ag-0.7Cu solder alloy, in Electron. Compon. Technol. Conf., New Orleans, LA, 2003, pp [9] H. L. J. Pang, B. S. Xiong, and T. H. Low, Creep and fatigue charaterisation of lead fress 95.5Sn3.8Ag-0.7Cu solder, in Electron. Compon. Technol. Conf., Las Vegas, NV, 2004, pp

9 SELVANAYAGAM et al.: NONLINEAR THERMAL STRESS/STRAIN ANALYSES OF COPPER FILLED TSV 9 Cheryl S. Selvanayagam received the degree in mechanical engineering from the National University of Singapore. She has been with the Institute of Microelectronics since Her research interests include material characterization and mechanical modeling. John H. Lau (F 94) received three M.S. degrees in structural engineering, engineering physics, and management science. He received the Ph.D. degree in theoretical and applied mechanics from the University of Illinois, Urbana-Champaign. After more than 20 years as a Senior Scientist and MTS at Hewlett-Packard (HP) and Agilent in California, he became Director of the Microsystems, Modules, and Components Laboratory, Institute of Microelectronics, Singapore, for two years, and has been a Visiting Professor with Hong Kong University Science and Technology since With more than 30 years of R&D and manufacturing experience, he has authored or coauthored more than 300 peer-reviewed technical publications and more than 100 book chapters, and given more than 250 presentations. He has authored and coauthored 16 textbooks on advanced packaging, solder joint reliability, and lead-free soldering and manufacturing. Dr. Lau is an elected ASME Fellow. Kripesh Vaidyanathan received the M.S. degree in physics from University of Madras, India, in 1987, and the Ph.D. degree in the area of thick and thin film passives for microelectronics modules from the Max-Planck Institute for Metalforschung, Stuttgart, Germany, in He has 20 years research experience in the area of advanced packaging. He was a Visiting Scientist at Infineon Technologies, Corporate Research, Munich, Germany, in the area of 3-D-integrated circuits. Since March 2000, he has been with the Institute of Microelectronics, Singapore, heading a group of researchers in area of 3-D TSV integration and wafer level packaging process. He has authored more than 60 journal and conference publications and holds 18 patents to his credit. His research interests are 3-D-silicon stacked modules, Cu/Low-k packaging, and wafer level packaging. T. C. Chai is a Member of Technical Staff in the Microsystems, Modules, and Components Lab, Institute of Microelectronics, Singapore. He has worked on area of packaging development, reliability, and failure analysis for 18 years. Recently his focus has been flip chip packaging for Cu low K chip and TSV technology. Xiaowu Zhang received the Ph.D. degree in mechanical engineering from Hong Kong University of Science and Technology (HKUST). Currently, he is a Principal Investigator (PI) with Institute of Microelectronics (IME), A*STAR, Singapore. His research activities cover advanced packaging development and 3-D IC integration. He has authored or co-authored more than 80 technical papers in refereed journals and conference proceedings. Dr. Zhang is the recipient of the 2001 JEP Best Paper Award conferred by ASME Transactions: Journal of Electronic Packaging, and the 2004 Best Industry Support Team Award conferred by IME. He is listed in Who s Who in the World (2006).