Manufacturing Process

Transcription

1 Manufacturing Process 1

2 CMOS Process 2

3 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process 3

4 Single-crystal ingot and siliced wafers Czochralski Crystal Growing System 4

5 Crystal Defects Punctual defects 5

6 Crystal Defects Line defects 6

7 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development 7

8 Oxidation 8

9 Photo-Lithographic Process 9

10 Etching 10

11 Patterning of SiO2 Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate (e) After etching Chemical or plasma etch Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist 11

12 Ion Implantation 12

13 Metal Deposition 13

14 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 14

15 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 15

16 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 16

17 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. 17

18 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. 18

19 Advanced Metallization 19

20 Advanced Metallization 20

21 3D Perspective Polysilicon Aluminum 21

22 Silicon-on on-insulator Process 22

23 BJT Process 23

24 BJT Process 24

25 BJT Process 25

26 Resistors 26

27 Capacitances 27

28 Design Rules 28

29 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) 29

30 Layers in 0.25μm CMOS process 30

31 Intra-layer layout design rules 31

32 Transistor layout PMOS 32

33 Contacts and vias design rules 33

34 Well contacts and select layer design rules 34

35 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. 35

36 Latch-up CMOS structure with parasitic npn and pnp transistors identified 36

37 Latch-up V DD R nwell p-source n-source R psub CMOS latch-up: equivalent circuit 37

38 Circuit Under Design V DD V DD M2 M4 V in V out V out2 M1 M3 38

39 Layout of two chained CMOS inveters 39

40 CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 40

41 CMOS Inverter Layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p + 41

42 Four-input CMOS NAND layout 42

43 Computing the Capacitances 43

44 Parasitic Capacitances V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L 44

45 Layout of the Cascaded Inverter Pair PMOS (9λ/ 2λ) V DD 0.25 μm = 2λ In Out Metal1 Polysilicon NMOS (3λ/ 2λ) GND 45

46 Inverter Transistor Data 46

47 Components of C L 47

48 Capacitances Parameters in 0.25 μm CMOS process 48

49 The Overlape Capacitance Polysilicon gate Source n + x d x d W Drain n + L d Top view Gate-bulk overlap t ox Gate oxide n + L n + Cross section 49

50 The Miller Effect 50

51 Source Junction Channel-stop implant N A + Side wall W Source N D Bottom x j L S Side wall Substrate N A Channel 51

52 Junction Capacitance (1) 52

53 Junction Capacitance (2) 53

54 K for eq a 2.5 V CMOS Inverter 54

55 Gate-to to-channel Capacitance G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturation 55

56 Wire Capacitance Tipycal interconnect capacitances for 0.25 μm CMOS process (wires routed over the field oxide): - Al1 area capacitance = 30 af/μm 2 - Poly area capacitance = 88 af/μm 2 From the layout: - poly area = 72 λ 2 - Al1 area = 42 λ 2 C W = 42 λ 2 30 af/μm λ 2 88 af/μm 2 = 0.12 ff 56