Board Assembly MANUFACTURING TECHNOLOGIES. Wave and Selective Soldering... 48

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1 Board Assembly Dr. Dongkai Shangguan, Flextronics, Chair Dr. Ravi Bhatkal, Cookson Electronics, Co-Chair David Geiger, Flextronics, Co-Chair CONTENTS: Board Assembly... 1 Executive Summary... 1 Introduction... 3 Situational (Infrastructure) Analysis... 4 Business Trends... 4 Component Trends PCB Trends Assembly Materials SMT Process Part Placement Wave and Selective Soldering Rework and Repair Roadmap of Quantified Key Attribute Needs Business Issues: Research and Development Trends Business Issues: Technology Transfer Trends Cross Cutting: Assembly Materials Forecast Process Technology: SMT Process Technology Process Technology: Dispensing / Underfill Technology Forecast Process Technology: Part Placement Technology Forecast Process Technology: Wave and Selective Soldering Technology Forecast Process Technology: Rework and Repair Technology Forecast Critical Infrastructure and Technology Issues Business Issues Assembly Materials Surface Mount Technology Process Dispensing/Underfill Part Placement Wave and Selective Soldering Press Fit Rework and Repair Direct Chip Attach Business Issues, Gaps and Showstoppers Cross Cutting Issues, Gaps and Showstoppers Process Technology Gaps and Showstoppers Prioritized Research & Development Contributors inemi Technology Roadmaps i January

2 Figures Figure 1: Board assembly conversion costs forecasts by product sector... 5 Figure 2: Board assembly escape rates forecasts by product sector... 6 Figure 3: Time to add an by product sector... 7 Figure 4: NPI Cycle Time by product sector... 8 Figure 5: Maximum Component I/O Density by product sector Figure 6: Minimum Area-array Package Pitch Figure 7: Maximum Component Density by product sector Figure 8: Land Pattern reduction by product sector Figure 9: Press Fit Illustration TABLES Table 1: Impacts of embedded passive implementation at various assembly levels... 9 Table 2: Forecasted conversion to Lead-free by product Table 3: Forecasted cooling method by product sector Table 4: Research and Development Trends Table 5: Technology Transfer Trends Table 6: Assembly Materials Technology Forecast Table 7: Interconnect materials deposition technology forecast Table 8: Reflow Technology Forecast Table 9: Dispense and Underfill Technology Forecast Table 10: Pick and Place Technology Forecast Table 11: Wave and Selective Soldering Technology Forecast Table 12: Rework and Repair Technology Forecast Table 13: Research and Development Infrastructure Trends Table 14: Technology Transfer Infrastructure Trends Table 15: Assembly Materials Technology Needs Table 16: Printing Process Application Technology Needs Table 17: Reflow Technology Needs Table 18: Reflow Technology Needs Table 19: Dispense and Underfill Technology Needs Table 20: Part Placement Technology Needs Table 21: Wave and Selective Soldering Technology Needs Table 22: Rework and Repair Technology Needs Table 23: Direct Chip Attach Technology Parameters Gaps and Showstoppers inemi Technology Roadmaps ii January

3 Dr. Dongkai Shangguan, Flextronics, Chair Dr. Ravi Bhatkal Cookson Electronics, Co-Chair David Geiger, Flextronics, Co-Chair EXECUTIVE SUMMARY Board assembly is a critical part of the overall electronic products supply chain. It accounts for most of the direct-material cost, and is closely associated with component packaging, interconnect, inspection, thermal management, final assembly, and environmental technologies. Based upon the Product Sector emulators provided for this roadmap, there are four main common drivers for development in board assembly processes: Conversion Cost Reduction Reduction in New Product Introduction Time Increased Component I/O Density Transition to Environmental and Regulatory Requirements These drivers are affecting business environments, manufacturing technology, and research needs. One of the profound business environment impacts of the product sector drivers is the higher level of service demands, or opportunities, placed on the contract manufacturers by the Original Equipment Manufacturers (). Today s Electronic Manufacturing Service () companies are expanding offerings to include services in a wider range of a product s life cycle. Some new offerings, being developed by the companies today (and in the future), include product support, installation support, and field service support. There are also an increasing number of situations where the barrier to implementing a new process or technology is a business issue (as opposed to a technical uncertainty). Some of these business issues include: Supply chain readiness to deal with the transition to lead-free is a key gap for the electronics industry going forward. The ability for the supply chain to support both lead containing and lead-free bills-of-materials (BOMs) will provide significant challenges and investments for some time to come. With research and development (R&D) responsibility transitioning to the companies in low cost geographies, government, academia and industry consortia will need to formulate ways to adopt and develop emerging technologies (such as nanotechnology) into the board assembly process, in the global outsourcing environment. For the board assembly process, several cross cutting gaps and showstoppers require a renewed focus: To support the future product functionality forecast by the product emulator groups (PEGs), a showstopper exists for the printed circuit board (PCB) (or substrate) to provide a low cost fine line technology. Government, consortia and academia need to concentrate research funding to solve this problem. inemi Technology Roadmaps 1 January

4 Manufacturers of System-in-Package (SiP) will require process development to occur on passive component packages. Work is required today on the next generation of solder materials to replace the high cost silver containing alloys for cost-sensitive applications; this work needs to be coupled with the need for ultra low temperature attachment requirements for new polymer based products. Additional work is required to improve the Sn-Ag-Cu (SAC) alloys to overcome several critical concerns such as; copper dissolution during wave and selective soldering, reliability under mechanical shock, etc. Design for manufacturing (DFM) in the global outsourcing environment requires closer interactions and collaboration across the supply chain, including,, and the supply base. Industry standards to facilitate and streamline the information flow need to be developed. For the board assembly process, these technology gaps have been identified: The widening range of required paste volume deposited on mixed technology assemblies is pushing traditional stencil design rules to their limit. There is a need for stencil, printing, and materials technologies to increase the consistency of the deposit. To meet the needs of future products, non-traditional technologies for solder paste deposition may need to be developed. There is a gap in being able to support the cost reduction targets with the transition to lead-free - due to increased energy consumption, raw material cost increase, and shortterm yield issues. and companies will need to work on creative engineered solutions that support these gaps near term, and full turnkey solutions are required for the long term. inemi s PEGs are forecasting an increase in the frequency and a decrease in the footprint of their products, resulting in the increased use of new liquid crystal polymer (LCP) substrate materials and flexible circuits, requiring the existing equipment supply base to support material handling of flexible / low loss substrates. Inspection / Test technologies need to keep up with the increasing density of board designs and the complexity of component packages. Substrate technologies also need to be able to keep up with the increasing density of board designs. The increased need for three dimensional board assembly requires innovation in every step of the board assembly process including; paste deposition, component placement and attachment, inspection and test, etc. inemi Technology Roadmaps 2 January

5 INTRODUCTION The board assembly process begins with leaded component insertion (for wave soldering) or solder paste application (for SMT) on the bare printed circuit board (PCB) and ends at Printed Circuit Board Assembly (PCBA) test. It also includes special processes such as underfill application, odd form component placement, etc. Although test and inspection actions occur throughout the board assembly process, they are being addressed in the Test, Inspection, and Measurement Chapter of the inemi Roadmap. The inemi Board Assembly technical working group (TWG) formed sub-teams to focus on the different areas within the board assembly process, including: Assembly Materials, Surface Mount Technology, Placement, Dispense Technology, Wave and Selective Soldering, Press Fit, Rework, and Direct Chip Attach (DCA). This arrangement allowed the volunteers most interested in specific topics to participate in those meetings that are most relevant, and allowed participation from a wider industry audience and geography, resulting in better identification and prioritization of gaps. The Assembly Materials focus team examined the materials used in the second level board assembly process. Included in this scope were surface mount technology (SMT) solder pastes (no-clean and water soluble), ball grid array (BGA) rework pastes, SMT glues, wave bar solder, wave solder fluxes, underfills, repair / manual soldering materials, repair glues, heat sink attach glues and mechanical attach materials, die attach materials including preforms, encapsulants, conformal coatings and nano-materials (specifically as fillers). The SMT process focus team addressed the material application processes (stencil print, dip and dispense flux, etc.), reflow processes, excluding part placement processes. Additionally, this focus team addressed cleaning processes for stencils, wave, and SMT. The Placement focus team addressed the placement process and the equipment for this process. Included in this are components per hour, component dimensions, operational items such as changeover times and MTBF (Mean Time Between Failures) / MTBA (Mean Time Between Assists). The Dispense focus team addresses the issues related to the dispensing of various materials, such as underfills, solder, epoxies, etc. The Press Fit Connector focus team identified issues such as test and inspection of the press fit type of components as well as the future needs for this technology. The Direct Chip Attach focus team looked at the trends of chip-on-board technology and includes both flip-chip (defined as an area array package with <0.4mm pitch) and chip and wire technology on organic substrates. The assumption here is that this process includes other types of SMT components on a product level board (instead of a packaged part). The Repair / Rework and Wave / Selective Soldering focus teams addressed issues related to lead free conversion, such as the percentage of lead-free conversion in wave solder alloy and rework paste, as well as key process parameters for each process technology. For the Repair and inemi Technology Roadmaps 3 January

6 Rework focus team, the scope included both automated and manual component replacement, and solder joint touch-up. The Wave and Selective Soldering process focus team addressed all the technology and business issues for pin-in-hole assemblies. SITUATIONAL (INFRASTRUCTURE) ANALYSIS BUSINESS TRENDS For Original Equipment Manufacturers (s), Board Assembly represents a partner to leverage in the development of increasingly sophisticated products. The inemi emulators for the different product sectors, though diverse in form and function, have common priorities for Board Assembly. These priorities are: Aggressive reduction of conversion cost Exponential reduction of time to add an and to reduce New Product Introduction (NPI) cycle time Transition to environmental and regulatory requirements Thermal Management migration from passive cooling to active cooling Lower required escape and defect rates Move to low cost geographies for support of all aspects of the product life cycle Conversion cost is the cost to take a group of parts and convert them to a functioning electronic assembly. Conversion cost is the price of a completed PCBA (including test, material procurement cost, etc.) minus the material cost. In this way, all cost associated with manufacturing and testing the assembly is considered. All product sectors are predicting a significant requirement for a decrease in the conversion costs by The portable electronics sector appears to be requiring the most aggressive reductions in conversion cost, becoming the industry driver after 2011 (over the current industry leader, office systems products) (See Figure 1). The defense product emulator is lagging other sectors because of the focus on reliability over cost. Note that these conversion cost reduction numbers are actually cost reductions forecasted or expected by the s. It is unclear now whether companies will actually be able to deliver such conversion cost reductions, given the investment levels required and the increased variable costs accompanying technology transitions such as the lead-free conversion. inemi Technology Roadmaps 4 January

7 Board Assembly Conversion Cost Conversion Cost, Cents per I/O PORT MED DEF AUTO OFF COMM Year Figure 1: Board assembly conversion costs forecast by product sector Tied closely to the conversion cost is the escape rate metric for board assembly. All product sectors are projecting an exponential decrease in DPMO levels. This trend is being led (as expected) by the higher volume product sectors such as automotive; however Figure 2 clearly shows the emphasis being placed on the portable, medical and office equipment industries to make improvements in escape rates. For the defense industry, the reduction in escape rates is not driven primarily by cost, rather, it is driven by a need for increased quality levels, translating into increased reliability - by doing it right the first time. In light of tightening process windows due to the RoHS transition, it is yet unclear as to whether such steep escape rate reductions (especially for portable and office / communication segments) will be obtainable. inemi Technology Roadmaps 5 January

8 Board Assembly Escape Rates Escape Rate, DPMO PORT MED DEF AUTO OFF COMM Year Figure 2: Board assembly escape rates forecast by product sector Another significant contributor to the conversion cost is the migration of electronics manufacturing to lower cost geographies. The migration to China appears to be leveling, especially in the high volume production sector such as mobile phones and consumer electronics. China already produces 50% of the world s cell phone volume and almost two-thirds of the world s DVD players. companies are now beginning to seek other near neighbor locations such as India to serve as both a hedge to China as well as to serve local markets. The time to add an is defined as the elapsed time from an company s decision to add an to that company s outsourcing options, to the time that said is qualified by the to accept a product release for NPI through production. That would include having the required information systems in place to control the product s key documentation and any pilot production runs. Figure 3 compares the times to add an for the various product sectors. Portable, Medical (non-implanted only) and Office Equipment sectors show identical characteristics with shorter cycle times, while Communication, Automotive, and Defense have longer cycle times. For medical implantables, the cycle time is much greater. The most significant implication of the exponential decrease of this metric will be the commoditization of Board Assembly, discussed in detail later. inemi Technology Roadmaps 6 January

9 The New Product Introduction time is the time between a design released for alpha prototyping and its release for production (assuming that the prototype parts are available at release). With New Product Development cycle times projected to reduce by over 60% by 2017, new constraints will be placed on the manufacturing processes. Automotive shows the longest NPI times, followed by Communications and Defense. Portables, Office Equipment, and Medical (Externals only) show similar behavior with shorter cycle times. In Medical implantables, where regulatory approvals are required, cycle times are much longer. In general, for both the Time to Add an and the NPI cycle time, the projected rapid reduction of these times will need to be met with business system changes within both and organizations. Time to Add Time to Add, Weeks PORT MED DEF AUTO OFF COMM Year Figure 3: Time to add an by product sector inemi Technology Roadmaps 7 January

10 NPI Cycle Time NPI Cycle Time, Weeks PORT MED DEF AUTO OFF COMM Year Figure 4: NPI Cycle Time by product sector Looking across all product sectors at changes in component technology, while 0402 components are standard, 0201 components have been increasing in penetration. The Portable product category is predicting a move to embedded passives in. A significant number of cell phones have shipped with embedded passives. While equipment and process capability either exists or will soon be available for placing components, there is some question whether current generation passives meet the requirements for values (of capacitance and resistance) for contemplated applications. The ITRS roadmap outlines significant justification for embedded terminating resistors on the packages due to cost and low implementation barriers. As Table 1 outlines, this will affect both SiP assembly and second level board assembly in many areas. However, embedded passive technology has not been implemented at the rate originally forecast by previous roadmaps. The timing of such impact obviously would depend on the rate of embedded passives adoption and penetration. inemi Technology Roadmaps 8 January

11 Embedded Passive Type Board Assembly Impact Second Level Substrate Package Level Substrate Interconnect Level Handling / Manufacturing Process which does not adversely impact the embedded passive performance Reduction in the number of placement machines Need for placement equipment with higher flexibility Known good substrate Increased board thickness due to additional layers Increased thermal mass of substrates Need for placement equipment with higher flexibility Known good substrate Advancements in board handling due to increased adoption of ceramic substrates Increased thermal mass of substrates Equipment for integration of the passives on the termination Known good die Interconnect technologies for the passives on the termination Reliability understanding of integration of the passives on the interconnect Table 1: Impacts of embedded passive implementation at various assembly levels Two significant forces that have influenced board assembly processes for many years are the environmental and regulatory requirements. The most pressing legislation is the European Union Waste Electrical and Electronic Equipment (WEEE) and Reduction of Hazardous Substances (ROHS) legislation, which have already taken effect. The adoption of lead-free board assembly to meet these requirements is forcing conversion even in exempt industries such as Aerospace / Defense due to the supply base dynamics. This de facto compliance to lead-free materials for all product sectors may have certain impact on the reliability of electronic assemblies and create hidden costs for these industries, while the specific impact remains to be determined. With the Defense and Automotive industries forecasting a slower adoption timeline than most other sectors, component traceability and availability will be an issue. With the product emulators forecasting increasing Design-for-Take-Back requirements going forward, new opportunities in materials and processes will result. However, future environmental restrictions may result in further material changes and process changes. inemi Technology Roadmaps 9 January

12 PORT SnPb Pb-Free Pb-Free Pb-Free Pb-Free MED SnPb SnPb Mixed Mixed Pb-Free DEF SnPb SnPb SnPb SnPb SnPb AUTO SnPb SnPb Pb-Free Pb-Free Pb-Free OFF SnPb Pb-Free Pb-Free Pb-Free Pb-Free COMM SnPb SnPb Pb-free Pb-free Pb-free Table 2: Forecasted conversion to Lead-free by product A major concern identified in the inemi and ITRS roadmaps is a need for improved thermal dissipation. Power density is forecast to increase for portable and low-end consumer products. Because of this increase, the product sectors also forecast that the use of active cooling will become more predominant (See Table 3) PORT Both Both Both Both Both MED Passive Passive Both Both Both DEF Passive Passive Active Active Active AUTO Passive Passive Active Active Active OFF Passive Passive Both Both Both COMM all all all all all Table 3: Forecasted cooling method by product sector COMPONENT TRENDS Component technology advances continue to provide challenges to the board assembly environment. The maximum component I/O density, as shown in Figure 5, is defined as the maximum I/O package divided by the package area. All of the emulators show a significant increase in the maximum I/O density over time. Portables show the steepest increase in maximum I/O density. For Office Equipment and Defense, the maximum I/O density plateaus after Automotive and Communication Equipment products show consistent increases in maximum I/O density. This plateau (for Office Equipment products) is created by the high cost of fine line routing for PCB s and by a flattening of die size increases. Until a low cost routing solution for the PCBs is developed, more functionality will be modularized with system in package (SiP) solutions. inemi Technology Roadmaps 10 January

13 The increasing I/O per sq. cm will demand a further reduction in the device pitch. The Portable sector is predicting that the maximum I/O package on the board will utilize a 0.4 mm pitch until 2009 and a 0.3 mm pitch by 2011, A component issue, which is being aggravated with the introduction of higher reflow temperatures for lead-free, is the increased sensitivity to moisture sensitivity levels (MSL). Increasing reflow temperatures are likely to require additional tracking and / or monitoring tools. To combat this increase in MSL sensitivity, and to allow for the development of new materials and processes, most emulators are anticipating a phased approach by component vendors to 260 C reflow qualified parts based on component volume and thickness. The challenge for board assemblers will be tracking the allowable reflow temperatures by component and their associated process definition. Maximum Component I/O Density I/O per sq. cm PORT MED DEF AUTO OFF COMM Year Figure 5: Maximum Component I/O Density by product sector inemi Technology Roadmaps 11 January

14 Minimum Package Pitch for Area Array Packages 1.20 Pitch mm PORT MED DEF AUTO OFF COMM Year Figure 6: Minimum Area Array Package Pitch Greater silicon level and package-level integration through System on a Chip (SoC) and SiP technologies could potentially reduce the need for major advances in board-level assembly, unless simultaneous reduction in total product envelope (as in the case of portables) is called for. The level at which functionality is integrated (i.e. silicon, package or board level) would depend on design envelope, manufacturing flexibility and manufacturability, unit volume, performance and overall cost. PCB TRENDS A few key trends occurring with PCB technology that are affecting board assembly include: Higher use of flexible (especially for Portables) and low loss materials (especially for Communications and Medical) Availability of a low cost board technology to handle very fine pitch, high I/O devices Decreasing pad diameters impacting the reliability of the second level assembly Transition to embedded passives (in Portables) The higher adoption of flexible substrate materials is driven by electronics penetrating every aspect of our lives. The Portables product sector is forecasting increased use of flexible substrate materials. The higher application rate of flexible materials offers unique challenges when coupled with high I/O density devices and lead-free applications. For board assembly, inemi Technology Roadmaps 12 January

15 development of process and handling techniques to support these materials will be paramount to a successful introduction of the technology. One of the greatest challenges that PCB suppliers will face is the development of low cost board technology that enables routing out of high pin count devices with tight pitches (See the Substrates Chapter). As this challenge is met, second level assembly will see a rapid decrease in component pitch and an associated increase in package I/O count. The third major implication that board technology changes are having on second level assembly is the impact on second level reliability. With continued reduction in pitch, and likewise standoff, interactions between the PCB and the substrate will challenge the solder interconnect. Again, this trend coupled with the higher reflow temperatures and increased voiding of lead-free solders will offer unique challenges for assemblers. The above discussions focus on common drivers that affect all board assembly processes. The drivers that are specific to each board assembly process are discussed in the following paragraphs. ASSEMBLY MATERIALS The scope of materials issues discussed here includes all materials used in the second level board assembly process, including SMT solder pastes (no-clean and water soluble), BGA rework pastes, wave bar solder, wave solder fluxes, underfills, repair / manual soldering materials, heat sink attach glues and mechanical attach materials, die attach materials, encapsulants, and conformal coatings. Increasing component complexity will be a driver for advances in new materials. Increasing package density will challenge cleaning requirements and rework. Smaller components with lower standoff will be more difficult to clean using a water cleaning process, and additional cleaning process improvements may be required. Low component stand-off height will also challenge underfill chemistries in meeting fill time and voiding requirements. The negative impacts of lower joint height on solder joint reliability may create opportunities for new interconnect technologies and materials. This reliability challenge is made more complicated by more stringent reliability requirements for the Office / Communication and Automotive product sectors. SMT PROCESS For the purposes of this analysis, all SMT material application processes and reflow / cure processes (excluding part placement processes) will be considered. Environmental and regulatory changes such as RoHS are challenging SMT reflow processes (and to a lesser extent) printing and dispensing processes. These environmental and regulatory changes are resulting in significant challenges in achieving targeted NPI cycle time reductions, first pass yield improvement, and board assembly conversion cost reductions. Board assembly conversion cost targets are driving the need for greater efficiency of SMT processes. The transition to mixed lead-containing and lead-free production is challenging, and requires tightly inemi Technology Roadmaps 13 January

16 controlled production floor processes to handle added supply chain complexity. Reliability of such mixed assembly (lead-free components in a tin-lead assembly) is a subject of substantial study. Higher moisture sensitivity levels of components today due to reflow temperatures of 260C may negatively affect cycle times associated with SMT processes due to longer required bake-out schedules, and may negatively impact yields, product reliability, and board conversion costs resulting from moisture damage to production parts. With the adoption of lean manufacturing methodologies, high mix, low volume manufacturing is providing an impetus to reduce changeover / setup times and process cycle times. The trend is toward flexible tooling solutions, optimized production equipment sets, and optimized production line configurations. The miniaturization of components, increasing component density, and larger sized electronic assemblies are challenging the first pass yields of printing, reflow, and dispensing. The use of very thin and very thick board structures will also challenge printing, reflow, and dispensing processes. The use of advanced PCB materials is forecast to increase - such as the use of flexible circuits and low electrical loss materials, which may present unique handling and reflow challenges. In general, lead-free assembly is requiring tighter control of the reflow process window to ensure that maximum assembly temperatures are not exceeded and to minimize the temperature deltas across electronics assemblies. Other key drivers of the reflow process include reducing the total cost of ownership (including energy cost, nitrogen cost, and maintenance cost), requiring improved flux management systems, and improved traceability. PART PLACEMENT Part placement refers to all chip placement processes relating to the placement of components on a second level assembly including: Fine pitch placement, Odd-form placement, Press-fit connector, Chip placement (gantry), Chip placement (turret); for SMT, Pressfit, Wave, and manual processes. Increasing component complexity is driving changes to part placement efficiency. From prior ITRS roadmaps, semiconductors - while maintaining maximum die sizes - are projecting pin counts to rise above Without advances in technology, component pitches below 300 µm at the second level interconnect and below 70µm at the System-In-Package interconnect will negatively impact assembly yield. The adoption of embedded passives will require the development of new line configurations and operating methodologies for board assembly operations. WAVE AND SELECTIVE SOLDERING This section will include the roadmap for wave soldering and selective soldering technology, used for the attachment of plated through-hole (PTH) components. inemi Technology Roadmaps 14 January

17 A conventional wave solder machine is utilized to solder PTH assemblies in a wave soldering process. Both open and selective wave pallets can be used in this process. In a selective soldering process, PTH components are soldered using selective soldering equipment. There are many selective soldering methods such as: point to point soldering, mini-wave soldering, laser soldering, hot gas soldering, etc. The forecast in this roadmap is for all selective wave soldering technologies. Printed circuit boards (PCBs) are being designed with both through-hole and surface mount components. In general, pin in hole (PIH) usages are 5% or less vs. SMD in PCB designs in commercial product and 10-15% usage in the aerospace industry. The PTH percentage is expected to reduce slightly in the future (less than 5 %) as s migrate to contact interconnect devices (such as press-fit) for cost saving purpose. The continued use of both wave and selective soldering processes for soldering of PTH components are expected in the future. It is predicted that wave soldering technology will still be the dominant process for PIH component attachment. Currently, the utilization of conventional wave soldering is about 80% vs. 20% selective soldering. It is expected that the use of selective soldering will slightly increase in the future. In the year 2011, utilization of selective soldering should be about 30%. Environmental and regulatory changes (specifically the adoption of lead-free solder alloys) are the primary drivers going forward. The adoption of these new alloys (and flux systems) is requiring reassessment and re-optimization of wave and selective soldering process steps. The development of both water-soluble (WS) and no-clean (NC) Pb-free compatible fluxes are a key focus of materials suppliers. Two alloy systems are considered leading candidates to become standard in the industry: i) tin-silver-copper family; and ii) tin-copper family A conflicting challenge from the product emulators is the continued reduction in conversion costs. With PIH technology typically requiring manual labor for assembly, these products will continue to migrate to the countries with the most abundant labor markets. Furthermore, the adoption of Pb-free may come with equipment upgrade requirements. REWORK AND REPAIR In this analysis, the rework and repair processes consist of hand soldering, pin through-hole rework and ball grid array (BGA) rework. Product size reduction and densification continue to be the trend for the majority of the industry with Medical looking to implement the use of by 2017 and having embedded devices for portable products. As these parts get smaller, it would physically be impossible to rework by hand soldering. With embedded passives, tighter PCB fabrication processes would be required in order to achieve the necessary tolerances. inemi Technology Roadmaps 15 January

18 Year Auto Def Medical M0402 M Netcom Portable 0402 Embedded Embedded Embedded Embedded For through-hole components, the product emulators predict that the pitch will decrease over time - with the exception of the auto industry. This reduction in pitch would apply to soldered leadframe or press fit. If indicative of soldered leadframe, this will pose a challenge for barrel holefill and with pin-to-hole ratios on thick boards. The trend toward tighter component pitches is requiring increased component placement accuracy for rework. Figure 8, shows the projections of the product emulators to reduce the land pattern diameter. With this reduction - comes unique challenges in rework - from site dressing to defect free localized reflow. High component pin counts and larger component body sizes will challenge current rework placement and reflow techniques and impact rework yields. The higher lead-free process temperatures forecast by all the product sectors will narrow the process window for rework. This driver will be most significant for the larger products in the Networking product sector. Maximum Component Density Components per sq. cm PORT MED DEF AUTO OFF COMM Year Figure 7: Maximum Component Density by product sector inemi Technology Roadmaps 16 January

19 Land Diameter with Vias for BGA 600 Land Diameter With Vias BGA microns PORT MED DEF OFF COMM Year Figure 8: Land Pattern reduction by product sector ROADMAP OF QUANTIFIED KEY ATTRIBUTE NEEDS The quantification of key attributes has significantly expanded since the 2004 roadmap. These attributes have been broken into: Business Issues o Research and Development Trends o Technology Transfer Trends Cross Cutting Technology o Assembly Materials Forecast Process Technology o SMT Process Interconnect Deposition Technology Forecast Reflow Technology Forecast o Pick-and-Place Technology Forecast o Dispense and Underfill Technology Forecast o Wave and Selective Soldering Technology Forecast o Rework and Repair Technology Forecast inemi Technology Roadmaps 17 January

20 BUSINESS ISSUES: RESEARCH AND DEVELOPMENT TRENDS Operation Today Time > > Future Concept / Definition Product Technology Development Design (Board Module) Design (Hardware Drivers) Design (System) Design (System Software) Design Maintenance -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP -CDM-SUPP Process Technology -EQUIP -EQUIP Development -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Process Research and -EQUIP -EQUIP -EQUIP -EQUIP Development -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Test Functional Development Manufacturing Test (AOI / X- EQUIP EQUIP EQUIP EQUIP EQUIP EQUIP Ray) Development -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Reliability Evaluation Compliance Testing Application Engineering Failure Analysis Key ODM SUPP EQUIP -CDM-SUPP -EQUIP -EQUIP Original Equipment Manufacture has primary resposibility Original Design Manufacture or developing and marketing products has primary responsibilty Electronics Service Provider has primary responsibilty Component supplier to board assembly has primary responsibility Equipment/materials supplier for board assembly has primary responsibility Combination of, ODM, & Component Suppliers responsibility Combination of, ODM/ & Equipment/Material suppliers responsibility Combination of Equipment/Materials suppliers and /ODM responsibility Combination of & responsibility Combination of and ODM responsibilty Table 4: Research and Development Trends inemi Technology Roadmaps 18 January

21 Business Issues: Technology Transfer Trends Operation Today Time > > Future Primary Source of Manufacturing Component Engineering DFx Parts Procurement Prototype Build & Test Process Integration -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Deployment Production Forecasting Volume Manufacturing Production Support Production Maintenance Manufacturing Tes (ICT) Product Test (Functional) Box Assembly System Test -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Product Phone Support / Problem Management Field Support Field Returns Distribution to End Customers ODM SUPP EQUIP -CDM-SUPP -EQUIP -EQUIP Key Original Equipment Manufacture has primary resposibility Original Design Manufacture or developing and marketing products has primary responsibilty Electronics Service Provider has primary responsibilty Component supplier to board assembly has primary responsibility Equipment/materials supplier for board assembly has primary responsibility Combination of, ODM, & Component Suppliers responsibility Combination of, ODM/ & Equipment/Material suppliers responsibility Combination of Equipment/Materials suppliers and /ODM responsibility Combination of & responsibility Combination of and ODM responsibilty Table 5: Technology Transfer Trends inemi Technology Roadmaps 19 January

22 CROSS CUTTING: ASSEMBLY MATERIALS FORECAST Parameter Metric Solder Pastes Bar Solder Wave Solder Flux Lead-free % US 15% 30% 50% 75% 90% Lead-free % WW 30% 60% 80% 85% 90% Halogen-free 80% 85% 90% 95% 95% Low Temp. Assembly <5% <5% <5% <5% <5% Recycle ratio <1% <5% 10% 25% 25% Alloys SAC SAC SAC Low Temp Low Temp Lead-free % US 15% 30% 50% 75% 95% Lead-free % WW 50% 75% 90% 95% 95% Recycle ratio <1% 5% 10% 25% 25% VOC free 25% 40% 50% 60% 90% Halogen free 90% 95% 95% 95% 95% Die Attach Performs Thermal conductivity 80% 85% 90% 90% 90% critical Low temperature capability <5% <5% <5% <5% <5% Matched CTE capability 0% 5% 7% 25% 50% Rework Paste Lead-free % US 15% 30% 50% 75% 95% Lead-free % WW 50% 75% 90% 95% 95% Low temperature rework <5% <5% <5% <5% <5% Repair Adhesives Polymer base <5% 5% 7% 10% 10% Die Attach Adhesives Polymer Pre-applied 3% 5% 5% 5% 5% Polymer Paste 97% 95% 95% 95% 95% Low K Silicon 15% 30% 50% 60% 60% Thermal Conductivity 25% 40% 45% 50% 50% Critical Underfills Lead-free FC in package (laminate) BGA balls only JEDEC BGA balls only JEDEC BGA balls only JEDEC 260, BGA balls only JEDEC 260, BGA balls only JEDEC 260, BGA balls only Encapsulants Lead-free FC in package (ceramic), BGA balls only Low-k ILD Pre-applied FC Large Die CSP JEDEC Low-k ILD JEDEC BGA balls only JEDEC nm tech Limited availability 25 mm convention 20 mm low-k Fluxing and Reworkable Reworkable Commercial 5C storage 1 week working life Pre-applied SnPb JEDEC (organic) JEDEC 260 JEDEC BGA balls only JEDEC nm tech JEDEC BGA balls only JEDEC nm tech JEDEC BGA balls only JEDEC nm tech JEDEC FC bump and BGA balls JEDEC and below nm tech JEDEC 260 JEDEC L3 JEDEC L2@ mm low-k 25 mm low-k 30 mm low-k 30 mm low-k Pre-applied Lead-free JEDEC 260 (organic) JEDEC 260 Reworkable 5% JEDEC 260 (organic) JEDEC 260 Reworkable 25% JEDEC 260 (organic) JEDEC 260 Reworkable >> 25% JEDEC 260 (organic) JEDEC 260 inemi Technology Roadmaps 20 January

23 Parameter Metric Potting Compounds Conformal Coatings Nano-materials Storage and use Low temp cure Refrigerator storage, Moisture resistance Large array (printing) Large array (dispense) Epoxies Urethanes Low-pressure Silicones Lead-free VOC Solids Content As fillers Small nm <100 nm JEDEC 260 Printing Low temp cure, Faster cycle time Soft epoxy chemical resistance Sb and halogen free flame retardants Sb and halogen free flame retardants UL/flame retardant Fast Tack, Faster Moisture cure Water based (low VOC) Increase solids % Small Commercial Quantities JEDEC 260 Printing JEDEC 260 Sb and halogen free flame retardants Sb and halogen free flame retardants UL/flame retardant Faster Moisture cure Compatible with Lead-free residues Water based (no VOC) Increase solids % Small Commercial Quantities Refrigerator storage, Moisture resistance JEDEC Printing JEDEC 260 Sb and halogen free flame retardants Sb and halogen free flame retardants UL/flame retardant Faster Moisture cure Compatible with Lead-free residues Water based (no VOC) Increase solids % Large Quantities? Refrigerator storage, Moisture resistance JEDEC Printing JEDEC 260 Sb and halogen free flame retardants Sb and halogen free flame retardants UL/flame retardant Faster Moisture cure Compatible with Lead-free residues Water based (no VOC) Increase solids % Refrigerator storage, Moisture resistance JEDEC Printing JEDEC 260 Sb and halogen free flame retardants Sb and halogen free flame retardants UL/flame retardant Faster Moisture cure Compatible with Lead-free residues Water based (no VOC) Increase solids %?? Table 6: Assembly Materials Technology Forecast PROCESS TECHNOLOGY: SMT PROCESS TECHNOLOGY Interconnect Materials Deposition Technology Forecast Parameter Metric Stencil Technology Enclosed Print head Printer Accuracy Mixed Component Technology 0.4 mm CSPs / 0201 with pin in paste 0.3 mm CSPs / 0201 with pin in paste 0.3 mm CSPs / 0201 with pin in paste with pin in paste with pin in paste Accuracy X & Y 6 sigma Aperature to fiducials (um) Repeatability X & Y6 sigma Aperture to Fiducials (um) Area Aspect Raito (AAR) Laser Cut Stencil Area Aspect Raito (AAR) Electroform material compatibility Compatible with all tin-lead and lead-free solder pastes Accuracy X & Y 6 sigma Paste to fids (um) Repeatability X & Y6 sigma Paste to fids (um) Accuracy Theta 6 sigma Paste to fids (deg) Repeatability Theta 6 sigma inemi Technology Roadmaps 21 January

24 Cycle Time On Board Paste Inspection Paste to fids (deg) Repeatability Print Pressure 6 sigma Paste to fids (N) Transport in, board alignment, transport out 6 seconds 5 seconds 4 seconds 3 seconds 3 seconds % of 18x18 board covered within cycle time 15% 75% 100% 100% 100% Programming Time 20 min/board 10 min/board 5 min/board Table 7: Interconnect materials deposition technology forecast 5 min/board 5 min/board Reflow Technology Forecast Parameter Metric Cross Conveyor Temperature Delta Performance Lead-free Processing Maintenance Uniformity at Peak temperature - LF profile ( C) Along Conveyor Uniformity at Peek temperature - LF profile ( C) Peak Temperature Repeatability of a given thermal couple ( C) Inert Capability scfh (ppm levels) Cooling rates solder joint reliability 6 /sec 6 /sec 6 /sec 6 /sec 6 /sec Flux Management flux collection Self Cleaning Self Cleaning Advanced LF flux chemistries to reduce contaminates Elimination of flux management Elimination of flux management Cost of Operation, Energy & Consumption Reduction in operating costs 70% 60% 50% 40% 40% Table 8: Reflow Technology Forecast inemi Technology Roadmaps 22 January

25 Process Technology: Dispensing / Underfill Technology Forecast GENERAL DISPENSE CATEOGORY Parameter Comments Dot Size Metal Filled Materials Solder Paste Best Case Scenario with common fluids 200µ 150µ 125µ 100µ 50µ Silver Flake Best Case Scenario with common fluids 125µ 100µ 75µ 50µ 50µ Dots per Hour Single Dispense Head - IPC >75000 Wet Dispense Accuracy Dot Placement 3 Sigma 75µ 50µ 25µ 25µ 25µ Fine Line Capability Typical Un-Filled Materials 100µ 75µ 50µ 25µ 25µ Process Control Dot or Line Verficaton Vision Based Vision Based Vision or Laser Vision or Laser UNDERFILL DISPENSE CATEOGORY Parameter Comments UPH 10 X10mm CSP single pass 200µ bump height Vision or Laser >10000 Volume Control As a % on 15mg dispense weight 5% 3% 2% 2% 1% Keep Out Zone Control Process Control Best Case Scenario for controlling wet out 500µ 250µ 200µ 175µ 150µ areas for no contamination Closed Loop Methodology for Volume Weight Scale Weight Scale Laser Scan Laser Scan Laser Scan ocntrol Table 9: Dispense and Underfill Technology Forecast PROCESS TECHNOLOGY: PART PLACEMENT TECHNOLOGY FORECAST Parameter Chip Placement Speed IC Placement Speed - Large Size IC IC Placement Speed - Medium Size IC IC Placement Speed - Flip Chip Chip Placement Speed IC Placement Speed - Large Size IC Placement Accuracy Chips Placement Accuracy Fine Pitch Rotation Accuracy Fine Pitch Component Pick reliability Minimum Placement Force Range Maximum Placement Force Range Metric CPH per square meter using the IPC 9850 standard for 0603 components CPH per square meter using the IPC 9850 standard for QFP 208 CPH per square meter using the IPC 9850 standard for SO ,000 15,000 16,000 17,000 20,000 1,200 1,500 1,600 1,700 2,000 5,400 6,750 7,200 7,650 8,000 CPH per square meter 5,000 6,000 7,000 8,000 10,000 CPH per square meter using the IPC 9850 standard for 0603 components CPH per square meter using the IPC 9850 standard for QFP ,000 15,000 16,000 17,000 20,000 1,200 1,500 1,600 1,700 2,000 Microns Microns Degrees % pick reliability Grams Grams inemi Technology Roadmaps 23 January

26 Parameter Comment Metric Speed - Throughput Chip Placement Speed Chip Placement - IPC 9850 cph per meter sq (0603) IC Placement Speed - Large Size IC IC Placement - IPC 9850 cph per meter sq (QFP 208) IC Placement Speed - Medium Size IC SO Placement - IPC 9850 cph per meter sq (SO-16) CPH per square meter using the IPC 9850 standard for 0603 CPH per square meter using the IPC 9850 standard for QFP 208 CPH per square meter using the IPC 9850 standard for SO-16 12,000 15,000 16,000 17,000 20,000 1,200 1,500 1,600 1,700 2,000 5,400 6,750 7,200 7,650 8,000 Accuracy Operational Features IC Placement Speed - Flip Chip Die Placement - 2 x 2mm CPH per square meter 5,000 6,000 7,000 8,000 10,000 Placement Accuracy Chips 6 sigma X,Y placement accuracy Microns Placement Accuracy Fine Pitch (leaded) 6 sigma X,Y placement accuracy / rotation Microns/degrees 55 / 0,8 50 / 0,7 45 / 0,6 40 / 0,5 40 / 0,5 Placement Accuracy for components with balls, bumps - CSP, BGA, FC 6 sigma X,Y placement accuracy / rotation Microns/degrees 60 / 0,8 50 / 0,7 40 / 0,6 35 / 0,5 30 / 0,5 Component Pick reliability Based on 0201 component packaged per EIA 481 DPMO specification 2,000 1, Placement Force - Chips Minimum Grams Placement Force - Fine Pitch Placement Force - Specialty Components Minimum Minimum Grams Grams Maximum Maximum Grams Grams 2,500 4,000 2,500 4,000 3,500 5,000 3,500 5,000 4,500 5,000 Feeder Capacity per Machine 8mm feeder/m Component height Larger electrolytics >10mm tall; Medium Sized IC Speed mm Component height Connectors, Modules on PCB; Large Sized Placement Speed mm Feeding Die From Wafer including die flip CPH 5,000 6,000 7,000 8,000 10,000 Changeover time in minutes Changeover time (different board width, 50 different minutes feeders, different nozzles) Preventative Maintenance Time based on 2000 hour operational time - 1 shift year hours/month Maintenance Skill Level Level 2 Level 1 Level 1 maintenance maintenance maintenance operator level operator level MTBF Machine MTBF (not including feeders) per SEMI-E10 Hours 1,200 1,500 1,800 2,000 2,500 MTBA (Mean time between assist) MTBA per Semi-E10 Hours MPBA (Mean placements per assist) Placements 80, , , , ,000 Advanced Calibration Tools limited stand alone machine fully integrated fully integrated fully integrated Table 10: Pick-and-Place Technology Forecast PROCESS TECHNOLOGY: WAVE AND SELECTIVE SOLDERING TECHNOLOGY FORECAST Parameter Metric Wave/Selective Solder Flux Wave/ Selective Lead- Free Alloy VOC free (%) Halogen free (%) Utilization % LF % SAC vs. other LF alloy 95/5 90/10 80/20 80/20 70/30 Minimum feasible PTH pitch in wave/selective soldering Mil [mm] 80 [2.00] 60 [1.50] 50 [1.27] 50 [1.27] 40 [1.00] Conventional/Selective Wave Soldering utilization % (conventional/selective) 80/20 75/25 70/30 70/30 65/35 SMT paste in hole/wave Soldering Utilization % < 5 % < 5 % < 5 % < 5 % < 5-10 % Pre-heat Process Temperature 0 C Wave pot Temperature 0 C Wave/Selective solder contact time second Environment process N 2 /Air 50/50 60/40 60/40 50/50 50/50 Table 11: Wave and Selective Soldering Technology Forecast PROCESS TECHNOLOGY: REWORK AND REPAIR TECHNOLOGY FORECAST inemi Technology Roadmaps 24 January

27 Hand Soldering Process Soldering Process Parameter Metric Solder iron peak temperature used C Total contact time sec SnPb Smallest lead-frame pitch to be reworked by hand mm Smallest type of discretes being reworked Solder iron peak temperature used C Total contact time sec Pb-Free Smallest lead-frame pitch to be reworked by hand mm Smallest type of discretes being reworked Type of wire alloy - SAC305 SAC305 SAC305 SAC305 SAC305 Area Array Package Rework and Repair Technology Forecast Soldering Process Parameter Metric Maximum package size mm Minimum package size mm Minimum rework pitch mm Target solder joint temperature C Target delta T across solder joints C <10 <10 <10 <10 <10 SnPb Typical rework profile length (time) min Number of allowable rework on PCBA # Type of rework (Conv/IR/Laser) % 100/0/0 100/0/0 100/0/0 75/25/25 75/25/25 Type of redress approach (NonContact/Solder Wick) % 25/75 25/75 25/75 25/50 25/25 Type of medium deposit (Paste on PCB/Paste on Part/Flux only) % 75/0/25 75/0/25 75/0/25 75/0/25 75/0/25 Preheat Temerature (topside board temperature) C >110 >110 >110 >110 >110 Maximum local laminate temperature allowed C <160 <160 >200 <160 <160 Currently observe secondary reflow of adjacent reflow (3.8mm away) - Yes Yes Yes Yes Yes No. of allowable BGA reball - No No No Yes Yes Maximum package size mm Minimum package size mm , 7 5, 7 Minimum rework pitch mm Target solder joint temperature C Target delta T across solder joints C Pb-Free Typical rework profile length (time) min Number of allowable rework on PCBA # Type of rework (Conv/IR/Laser) % 100/0/0 100/0/0 75/25/25 75/25/25 75/25/25 Type of redress approach (NonContact/Solder Wick) % 25/75 25/75 50/50 75/25 75/25 Type of medium deposit (Paste on PCB/Paste on Part/Flux only) % 75/0/25 75/0/25 75/0/25 50/25/25 50/25/25 Preheat Temerature (topside board temperature) C Maximum local laminate temperature allowed C Currently observe secondary reflow of adjacent reflow (3.8mm away) - Yes Yes Yes Yes Yes No. of allowable BGA reball - No No No No No Table 12: Rework and Repair Technology Forecast inemi Technology Roadmaps 25 January

28 CRITICAL INFRASTRUCTURE AND TECHNOLOGY ISSUES A broad spectrum of technology areas challenges the board assembly process. To aid in understanding the critical infrastructure and technology issues facing board assembly institutions, the roadmap was broken into several key sections. The first of these sections is the business issues, which addresses the inter-relationships between s, s, and the supply base. These relationships are addressed in terms of the R&D, technology transfer, manufacturing or conversion costs, and product technology requirements. The next area of the roadmap addressed is the cross cutting requirements of the assembly materials. This section is also associated with the final five sections of the roadmap, addressing the material requirements. The last areas of the roadmap are broken into the manufacturing processes. These areas are: Assembly Materials Microelectronics SMT Process Part Placement Wave and Selective Wave Press fit Rework and Repair BUSINESS ISSUES Business issues related to board assembly have been further broken into four key areas: Research and Development Technology Transfer Conversion Costs Product Technology The Research and Development section highlights the changing industry ownership roles to bring products to market and to advance the process and manufacturing knowledge (to make these products cost competitive). A key attribute not addressed in this section is the role of government, consortia, and academia. With progressive reductions in process development capability, and the increasing role of the and materials suppliers in R&D and process development, sharing of fixed costs through consortium activities at industry technical and trade associations and universities is bound to increase. Such activity is especially true for the generation of baseline process and reliability data. The second area, Technology Transfer, addresses the ownership to deploy technology around the world. This section is highly focused on the execution mechanisms and needs. In this section, the roles of the,, ODM (original design manufacturer), and equipment suppliers, are rationalized. inemi Technology Roadmaps 26 January

29 Conversion cost is the third area addressed in the business issues section. The conversion cost addresses those cost factors affecting the assembly costs. This includes the outsourcing to companies, but also addresses the migration to low cost geographies. The last section in the business issues addresses the effects of lower conversion costs. In past roadmaps, the reduction of conversion costs has been a key element in transferring business to low cost geographies and in renewing focus on yield, efficiency, and utilization. This section will discuss the key trends for all manufacturers on these soft issues. The technical concerns for improvements in conversion costs are addressed in each of the process areas. RESEARCH AND PRODUCT DEVELOPMENT Research and development continually battles with technology push vs. pull. When the technology is pulled by the consumers, a rapid development and adoption cycle takes place; however, with the push by government regulations or manufacturers, a more thorough collaborative industry development cycle takes place. The challenge to academia and industry organizations is to establish a supply chain management infrastructure for electronics manufacturing technology without threatening the consortia contributors competitive advantages. The migration of traditional responsibilities (such as design, process, and technology development) to providers is also creating a fundamental shift in the industry. As s leverage their Board Assembly partners to reduce their own fixed cost investment, they are becoming increasingly dependent on the provider to support their R&D needs. The need for close long-term partnerships and shared investment across the value chain will be critical to reducing Time to Add and NPI cycle times. Traditional / partnerships utilize designs conceptualized from the and manufacturing services contracted from the The benefits from this partnership by effectively leveraging the process and manufacturing knowledge within the, and through reduced fixed investment in equipment. The gains from the relationship by gathering learning experiences over a broad range of products from multiple s and by spreading the process and equipment development costs over a larger revenue base. However, with the development of these closer relationships, certain companies are beginning to develop and market designs to the. This trend started with camcorders and video recorders, but has advanced into all market segments, except medical and military Thus far, ODMs have been focused on optimizing existing product technologies to reduce manufacturing and BOM costs. However, there is a strong trend for ODM / companies to take the next step in providing new functionality for products and branding them to the. This trend is evident with the portable product sector; however just as before, the combination of the manufacturing and design knowledge will allow ODM / companies to take this effort to other sectors. The ramification of this trend toward ODM / design concept responsibility has implications with the hardware driver and system software designs. As is seen in Table 13, these companies have taken on this responsibility today. One unexpected implication associated with this trend by the ODM / is acceleration toward the ODM / companies supporting application services. These two trends begin to cloud the differences between ODM,, and s, with the major distinction being associated with the product branding. inemi Technology Roadmaps 27 January

30 To facilitate the transactions and collaboration between and / ODM, it is vital the IPC-2500 series of standards be adopted within and companies for the development of smart computer aided design (CAD) to support this transference of designs between manufacturers. The key issue is how to protect the intellectual property rights of both parties while maintaining the maximum freedom to conduct business with the least amount of interference. As time to market reduces, and more collaborative engineering tools develop, the / relationships will become closer, with deeper views into each other s knowledge bases. The challenge will be to establish these relationships while maintaining control over the respective parties intellectual properties. The issue of intellectual property is further complicated with the introduction of offshore manufacturing. Differences in legislation between countries may cause patent infringement in transferring intellectual property between businesses. The development, acceptance, and enforcement of ethics and binding contracts will be necessary for the electronics industry. Particular sensitivity to IP security is especially important when dealing with some emerging countries where IP protection is not enforced as rigorously as is ideally desired. An additional trend over the 2004 roadmap has been the accelerated shared responsibility of the product reliability within the / ODM. Typically, with manufacturing knowledge with the, a clear understanding of the product reliability requirements existed. However, as s moved away from manufacturing, the second level reliability responsibility is undergoing significant change. This trend is clear in Table 13 with the sharing increasing responsibility for reliability evaluation. inemi Technology Roadmaps 28 January

31 Operation Today Time > > Future Concept / Definition Design (System) Design (System Software) Process Research and -EQUIP -EQUIP -EQUIP -EQUIP Development -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Manufacturing Test (AOI / X- EQUIP EQUIP EQUIP EQUIP EQUIP EQUIP Ray) Development -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Reliability Evaluation Application Engineering Failure Analysis Key ODM SUPP EQUIP -CDM-SUPP -EQUIP -EQUIP Original Equipment Manufacture has primary resposibility Original Design Manufacture or developing and marketing products has primary responsibilty Electronics Service Provider has primary responsibilty Component supplier to board assembly has primary responsibility Equipment/materials supplier for board assembly has primary responsibility Combination of, ODM, & Component Suppliers responsibility Combination of, ODM/ & Equipment/Material suppliers responsibility Combination of Equipment/Materials suppliers and /ODM responsibility Combination of & responsibility Combination of and ODM responsibilty Table 13: Research and Development Infrastructure Trends Technology Transfer With process research and development transferring to companies and equipment / material / component suppliers, the manufacturing centers are becoming worldwide operations. Therefore, technology transfers between these centers need to become more efficient. Several significant changes were identified from previous roadmaps with primary sources of manufacturing, manufacturing test (ICT), product support / problem management, and field support. In the 2004 roadmap, it was identified that companies would become the primary sources for manufacturing in the near term. It is still true that outsourcing is a strong trend with companies and that the long term state would be for the / ODM to become the primary sources for manufacturing. This forecasted trend does open opportunities to and ODM manufactures to provide R&D services for the. As outlined, with process research and development being coupled with the equipment / material / component suppliers, the integration and deployment of process technology will require strong supplier relationships. It is anticipated that suppliers will develop deployment teams to allow for worldwide ramping of capabilities. In general, the ownership of technology transfer activities is becoming more segmented from the and highly coupled with the and ODM. However, the limited R&D resources inemi Technology Roadmaps 29 January

32 available at the are often resulting in short-term, tactical, and project oriented relationships between the suppliers,, and. This approach needs to transition to long-term and strategic collaborative relationships, with collaborative funding mechanisms where appropriate cost sharing occurs between s and s for product and process development. An emerging area is the use of DfX by the / ODM companies. The / ODM companies are being engaged early in the product development process in order to input into the design process and giving inputs in design for manufacturing / assembly / test (traditional DfX), and supply chain / environment and recycling (non-traditional DfX). Design for manufacturing (DFM) in the global outsourcing environment requires closer interactions and collaboration across the supply chain, including,, and the supply base. Industry standards need to be developed to facilitate and streamline the information flow. Operation Today Time > > Future Primary Source of Manufacturing Prototype Build & Test Production Forecasting Volume Manufacturing Production Support Production Maintenance Manufacturing Tes (ICT) Box Assembly System Test -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP -EQUIP Product Phone Support / Problem Management Field Support ODM SUPP EQUIP -CDM-SUPP -EQUIP -EQUIP Key Original Equipment Manufacture has primary resposibility Original Design Manufacture or developing and marketing products has primary responsibilty Electronics Service Provider has primary responsibilty Component supplier to board assembly has primary responsibility Equipment/materials supplier for board assembly has primary responsibility Combination of, ODM, & Component Suppliers responsibility Combination of, ODM/ & Equipment/Material suppliers responsibility Combination of Equipment/Materials suppliers and /ODM responsibility Combination of & responsibility Combination of and ODM responsibilty Table 14: Technology Transfer Infrastructure Trends Conversion Costs Conversion cost is defined as the cost, which takes a group of parts and converts them to a functioning electronic assembly. Conversion cost is the price of a completed PCBA (including inemi Technology Roadmaps 30 January

33 printed circuit assembly test, material procurement cost, etc.) minus the material cost. In this way, all costs associated with manufacturing and testing the assembly are considered. As discussed in the situational analysis, all product sectors are predicting a requirement for significant decreases in the conversion costs by One of the historical enablers for board assembly to hit these cost targets was the adoption of SMT to the product designs. The key enabler of the SMT technology has been the high level of automation brought to board assembly. However, as the conversion cost targets decrease further, it is anticipated that the automation brought forward by SMT will also be an enabler toward the commoditization of the board assembly business. This trend toward commoditization will be further supported by improvements in interoperability and increased speed of transition between companies. To decrease the conversion costs as required by the Product Emulators, it will be necessary to continue to focus on ways to reduce conversion costs through improved asset utilization and lower labor rates. providers are continuing to require equipment suppliers to incorporate flexibility into their product offerings to reduce the total capital cost investment. Improved production line efficiency is required and a continued need for skill based education in lean manufacturing techniques. However, it is unclear to what extent such conversion cost reduction requirements forecast by the Product Emulators take into consideration the increased costs of implementing the RoHS transition, which is accompanied by tighter process windows, increased energy consumption, increased materials costs, cost of associated data generation, process development, and learning curve costs due to migration to lower cost regions. Greater silicon level and package-level integration through System on a Chip (SoC) and SiP technologies could reduce the need for major advances in board-level assembly, unless simultaneous reduction in total product envelope (as in the case of portables) is called for. The level at which functionality is integrated (i.e. silicon, package or board level) would depend on design envelope, manufacturing flexibility and manufacturability, unit volume, performance and overall cost. This will impact the split between component cost and conversion cost. Closely linked to the need for reduced conversion costs has been the evolution of the electronics manufacturing business models, with the entrance of the highly competitive original design manufacturer (ODM) model. As labor continues to be deployed to lower cost geographies to reduce costs and to supply developing markets, the need to effectively transfer technology and expertise is critical for board assemblers. Equipment and data interoperability across multiple vendor equipment sets can enable this technology transfer to low cost geographies and will require continuing efforts by standards organizations (e.g. IPC, ISO). In addition, the industry will need to continue to develop copy exact processes to reduce technology transfer cycle time. The evolution of higher cost geographies (e.g. North American, Western European) business models toward lower volume manufacturing, system assembly, program management, and new service functions will require new skills sets, re-training of the workforce, and an increased focus on efficiency to compete with the low cost geographies. The transfer of the process knowledge to the low cost regions will create significant risks within the higher cost geographies. As with other industries that have made this transition to low cost inemi Technology Roadmaps 31 January

34 geographies, the product development will soon follow to these low cost geographies. In particular, product functionality is enabled by the process capabilities in the electronics market. However, unlike other industries which have made this exodus, the electronics industry is pervasive to every aspect of our lives and remains a key enabler toward the quality of life. Therefore, this transfer of technology from the higher cost geographies to the low cost geographies will be a transition of technical power and runs the risk of eroding the quality of life for the high cost geographies. Closely tied to the conversion cost and commoditization of board assembly is the forecasted reduction in time to add an and to reduce NPI Cycle Time. The industry need for reduced cycle / setup times is driving equipment suppliers to look at parallel processing options and closed loop control software. There is also a need for improved product data management across virtual partners within the supply chain to make these forecasts a reality. As outlined in the Situational Analysis, the defect levels need to be continually reduced with the adoption of new technology. However, with the conflicting trend of reduced pitch and increased I/O density, the ability of board suppliers to support this reduction in the defect level will be limited without significant disruptive advancements in interconnect technology. The hope lies within the nanotechnology developments to provide these advancements. Interconnect concepts using carbon nano-tubes or nano-wires are examples of such possible advancements. In the absence of the adoption of new interconnect technology, renewed focus on DfX guidelines are required to reduce escape rates and improve defect levels. Product Technology The industry will need to increasingly focus on second-level mechanical reliability as component pitches / stand-offs continue to get smaller, making the mechanical margin of safety smaller. There is a need for companies, s, and component suppliers to work collectively to develop proactive methods of ensuring mechanical reliability. This includes assessing potential component and product-level reliability issues at an earlier stage in the product life cycle. Additionally and companies need to renew focus on the development of Design for Assembly (DfA) guidelines and the development and adoption of new mechanical test methods. A continued development of virtual qualification modeling software is required to reduce timeto-market. With the development of lead-free processes for these technologies, it is required to continue development of new component materials to meet the (260 C) reflow requirements. Furthermore, these same environmental drivers will require more research and development funding for developing a fundamental understanding of lead-free solder material metallurgy, processability, and reliability. One of the greatest challenges that PCB suppliers will face is the development of low cost board technology that enables routing out of high pin count devices with tight pitches. As this challenge is met, second level assembly will see a rapid decrease in component pitch and an associated increase in package I/O count. Government and academic research funding, a significant enabler of future products, must be focused on helping to make this a reality. inemi Technology Roadmaps 32 January

35 Closely tied to the PCB substrate line and spacing requirement is the need to evolve the environmental stability of flexible circuits. As discussed in the Situational Analysis, it is anticipated that the use of flexible circuits will increase as electronics becomes more pervasive in our lives. There is not only the requirement to evolve the substrate, as addressed in the pick-andplace and interconnect deposition technology sections, the equipment flexibility needs to evolve to meet handling requirements for the use of flexible and other low loss substrate materials. ASSEMBLY MATERIALS The scope of Materials issues discussed here includes all materials used in the second level board assembly process, including: SMT Solder Pastes (No-Clean & Water Soluble) Heat Sink Attach Glues BGA Rework Pastes Mechanical Attach Materials SMT Glues, Die Attach Materials Wave Bar Solder and Flux Encapsulants Underfills Conformal Coatings Repair and Manual Soldering Materials Cleaning Materials Repair Glues 1. Solder Paste A challenge associated with lead-free transition is the concurrent advancement in miniaturization, therefore the need of using a finer solder powder in solder pastes. For a successful transition to lead-free soldering, the flux vehicle of solder pastes has to be capable of supporting the new alloy compositions and the higher processing temperatures. Several key areas for the fluxes follow: Higher fluxing power to compensate for the poorer wetting resulted from the higher surface tension of lead-free solders Higher fluxing capacity and lower corrosion to support the use of a finer solder powder Greater oxidation resistance to support 260 C reflow and further miniaturized solder paste deposit New flux chemistries which promote the formation of finer microstructures hence a more smooth solder joint Water soluble chemistries to support cleaning requirement with 260 C reflow No clean chemistries to support 260 C reflow with increased ability for ICT probing No clean chemistries which are compatible with conformal coating systems Flux chemistries compatible with zinc instability, fluxing power, and reliability requirements Lower flux activation temperature for low melting alloys such as eutectic BiSn The roadmap is also predicting another migration to lower temperature lead-free solder alloys in timeframe. This transition is based upon the need to lower the costs of the assembly materials, and decrease the processing temperatures once again. This transition to low temperature materials can only be accomplished once the lead containing materials are removed inemi Technology Roadmaps 33 January

36 from the process. Japan s JISSO roadmap is forecasting a similar transition. To be successful in this next transition, it will be necessary for the basic research to begin by and consensus gained in the industry to coordinate the transition. Due to the high tin content, lead-free solder joints often exhibit shrinkage cracks caused by the formation of large tin dendrites. At this point, however, there is no conclusive reliability data to show the impact of shrinkage cracks on reliability. Although the impact on reliability may not be considered very significant (at the present time) the subject warrants further study, especially under mechanical loading conditions, which may be more sensitive to surface defects. 2. Bar Solder There is a trend towards increased adoption of low silver content wave solder alloys, potentially for equivalent or better performance than high silver SAC alloys at a lower cost. The increasing volatility of silver pricing is accelerating this trend. In the longer term, there is a desire in the industry to develop lower melting point Pb-free alloys. 3. Wave Solder Flux The somewhat uncertain schedule for Pb-free implementation in automotive, medical, aerospace, defense and telecom infrastructure industries will require dual alloy capability for many board assembly materials. Wave soldering fluxes that have the ability to perform with tin lead and higher temperature lead-free applications will be important to these industries through Tendency towards greener materials will also drive VOC-free flux growth. 4. Die Attach Preforms It is expected that preform use will increase for die attach (driven by thermal conductivity requirements) with greater need emerging for matched CTE preforms to minimize CTE-driven stress build-up. 5. Die Attach Adhesives Die attach materials are categorized into four segments: polymer paste, soft solder paste, solder performs, and pre-applied polymer. Polymer paste die attach is the most common application approach since it is very versatile and wide product offering available to bond different surfaces and die sizes. Polymer based die attach, either paste or pre-applied, capable of meeting the parallel technology challenges of Flip Chip underfills (for heat and moisture resistance) and polymer technology to withstand the higher lead-free reflow temperatures, will be needed. Key drivers for die-attach technology trends include: Pb-free initiative higher reflow temperatures and new materials Increased power density - need for thermal management Use of stress sensitive low K silicon 6. Underfills and Encapsulants Board level underfills can be grouped into two main categories: CSP / BGA underfill and DCA underfill - which are required for different reasons. inemi Technology Roadmaps 34 January

37 Type CSP / BGA DCA (Direct Chip Attach) Purpose Improve vibration and impact resistance Maintain joint integrity during thermal and power cycling Increasing component complexity and lead-free conversion will continue to drive advances in new materials. Increasing package density and smaller gaps and pitches will challenge the application of underfills for the finer pitch packages. The drive for lower cost assembly and higher throughput will drive innovative adhesive and encapsulant solutions. Component density will continue to increase with device functionality and result in tighter geometries with limited area to apply adhesives, underfills, and encapsulants. The drive to smaller components will continue making it more difficult to clean using an aqueous process and require additional cleaning process improvements. Low component stand-off height due to miniaturization will also challenge underfill rheological properties in meeting fill time and voiding requirements. Lower joint heights increase solder joint strain, thus adversely affecting reliability and creating opportunities for new interconnect technologies, encapsulating materials, and thermal process considerations. Ultra-thin component packaging may present new challenges as encapsulants may induce adverse thermo-mechanical stresses. Increased reliability challenges are made more difficult as more stringent reliability requirements are forecast by the Networking and Automotive product sectors. As flip chip packages become common, coupled with a general trend toward lower cost laminate substrates and away from costly ceramic substrates, it will be more difficult to meet these forecast reliability needs. Designers and engineers should consider a holistic view of the composite structure and influences of assembly steps on mechanical stress: Substrate Type Thermal and Moisture Exposure Encapsulation Type Chemical Compatibility Material Properties Operating Conditions Assembly Approach Opportunities to reduce process cost and improve reliability will be investigated. Pre-applied underfills to both silicon and substrate are desirable to drive down cost. Selective encapsulation and bonding, such as corner bond, will offer alternatives to traditional underfilling methods, which fill the entire gap; cycle time and consistency are some of the issues to be resolved. In addition, the following are some underfill characteristics that are desirable for BGA packages: Compatible with ceramic packages (alumina and glass-ceramic) No board or component pre-heat required for dispensing No resin bleed-out Low temperature snap-cure No degradation at 100 C for > 7 years Reworkable at 125 C inemi Technology Roadmaps 35 January

38 7. Potting Compounds Green potting compounds will continue to be developed and qualified. 8. Conformal Coatings Conformal coatings include acrylics, urethanes and silicones Lead-free compatibility, VOC, and solids content are important parameters for conformal coatings. Solids content is indirectly coupled to reducing VOC content and there is a trend toward low, or, no VOC conformal coatings There is a need to tailor conformal coatings to specific flux chemistries The need to develop lead-free processes has resulted in higher tin containing terminations. Coupling this with the increased tin content of the SAC solders, there is a renewed focus on tin whisker formation and growth. One of the mitigation methods proposed is the use of conformal coatings. In order to support this as a solution, formulators need to accelerate development of coating materials that are compatible with the lead-free no-clean flux systems. 9. Nano-materials As the electronics industry moves forward with miniaturization and increasing functionality, there is an escalating demand on materials performance used in the manufacture of materials used in electronics assembly. One such method of improving the performance of some materials is the use of nano-particle fillers. There is no accepted international definition of a nano-particle, but one of the more common definitions is "a particle having one or more dimensions of the order of 100nm or less". Others define these as particles with sizes less than 1-micron. There is no strict dividing line between nano-particles and non-nano particles. The size at which materials display different properties from the bulk material is material dependant and can be claimed for many materials much larger than 100nm. Definitions certainly become more difficult for materials that are a very long way from being a sphere, such as carbon nano-tubes for example. One of the aims for these materials is to grow them into long tubes, certainly not nano in length, but as they have a diameter in the order of 3nm for a single walled tube, they have properties that distinguish them from other allotropes of carbon, and hence can be described as nano-materials. This sort of nano-material has led to the extension of the idea of nano-materials being considered as such if any one of their structural features is on a scale of less than 100nm, which causes their properties to be different from that of the bulk material. Since most of the fillers used in underfills, potting materials, and encapsulants are spherical, this is not always relevant. Both classes of materials (sub 100nm and greater than 100nm) are available commercially for synthetic (high purity, low alpha emissions) spherical fused silica. "Large nm" fillers having average particle diameters of 300nm-600nm have been used in commercial underfills for at least 5 years. These types of products enable underfills to fill gaps down to 25-microns (or possibly less). There are some applications where this type of product is used with a 10-micron gap. inemi Technology Roadmaps 36 January

39 The "large nm" synthetic fillers have increased sufficiently in volume to bring the selling price in line with other high purity fillers. Therefore, we are now in a situation where these large nm fillers can be used in commercial products with little impact on cost. The "small nm" fillers having average particle diameters of less than 100nm are now being used in commercial underfill products saw the introduction of the first products with small nm fillers (having average particle diameters of about 20nm). The use of these fillers is NOT being driving by small gaps between die / package and substrate since the large nm fillers can easily meet this demand. Rather, the small nm fillers are being introduced for specific performance improvements, such as mechanical strength / toughness improvements, optical clarity in filled systems, etc. The cost impact of the small nm fillers is significant - at about 5x to 10x the cost of traditional micron-size fillers. Large volume manufacturing capacities of these small nm fillers may be a point of concern if demand rises quickly. Parameter Definition Lead-free % US 15% 30% 50% 75% 95% Bar Solder Lead-free % WW 50% 75% 90% 95% 95% Alloy SAC/Sn-Cu SAC/Sn-Cu SAC/Sn-Cu SAC/Sn-Cu SAC /Sn-Cu Alloy Low Temp Low Temp Lead-free % US 15% 30% 50% 75% 90% Solder Pastes Lead-free % WW 30% 60% 80% 85% 90% Alloy SAC SAC SAC Low Temp. Low Temp Halogen-free 80% 85% 90% 95% 95% Recycle ratio <1% 5% 10% 25% 25% Wave Solder Flux VOC Free 25% 40% 50% 60% 90% Halogen free 90% 95% 95% 95% 95% Die Attach Preforms Thermal conductivity critical Matched CTE capability 80% 85% 90% 90% 90% 0% 5% 7% 25% 50% Parameter Definition Lead-free compatibility JEDEC +260 JEDEC JEDEC JEDEC JEDEC reflow, small die, JEDEC paste Die Attach Adhesives Lead-free compatibility JEDEC +260 reflow, large die, paste High thermal (polymer based) paste JEDEC Compatibility with Low-k ILD, paste JEDEC 90 nm tech Pre-applied polymer DA to silicon JEDEC JEDEC JEDEC JEDEC >20 W/MK >30 W/MK >50 W/MK >100 W/MK >100 W/MK Limited availability JEDEC 90 nm tech JEDEC 65 nm tech JEDEC JEDEC JEDEC 45 nm tech JEDEC JEDEC 32 and below nm tech JEDEC inemi Technology Roadmaps 37 January

40 Underfills Conformal Coatings Lead-free FC in package (Laminate) BGA balls only Lead-free FC in package (ceramic), BGA balls only JEDEC 260, BGA balls only JEDEC BGA balls only Low K ILD JEDEC 90 nm tech Pre-applied FC Large Die CSP Lead-free Limited Availability 25 mm conventional, 20 mm low K Fluxing and Reworkable 5C storage 1 week working life Pre-applied SnPb Reworkable <1% Compatible with Lead-free residues JEDEC 260, BGA balls only JEDEC BGA balls only JEDEC 90 nm tech JEDEC 25 mm Low K Pre-applied Lead-free Compatible with Lead-free residues JEDEC 260, BGA balls only JEDEC BGA balls only JEDEC 65 nm tech JEDEC JEDEC FC bump and BGA balls JEDEC FC bump and BGA balls JEDEC 45 nm tech JEDEC JEDEC FC bump and BGA balls JEDEC FC bump and BGA balls JEDEC 45 nm tech JEDEC 25 mm low K 30 mm low K 30 mm low K Reworkable 5% Compatible with Lead-free residues Reworkable 25% Compatible with Lead-free residues Reworkable 25% Compatible with Lead-free residues VOC VOC-Free VOC-Free VOC-Free VOC-Free VOC-Free Nano-materials Key Current Capability In Development Research Needed As fillers Small Commercial Quantities Small Commercial Quantities Table 1: Assembly Materials Technology Needs Large Quantities??? SURFACE MOUNT TECHNOLOGY PROCESS The SMT process has been split into several sections because of the level of complexity and unique requirements of the sub-processes. Assembly Materials Printing/Reflow Soldering/Cleaning Placement Wave Soldering Rework Dispensing Press-fit DCA INTERCONNECT MATERIAL APPLICATION: PRINTING The printing process has seven key metrics covering the materials, process, and equipment capabilities required to apply material to the PCB to create an interconnection. Stencil Technology On-board Post Print Inspection (2D) Print Head On-board Post Print Inspection (3D) Equipment Accuracy Cost of Operation Equipment Repeatability Total Set-up Time Cycle Time inemi Technology Roadmaps 38 January

41 One of the greatest challenges facing the SMT process is stencil capability. The mixing of technology on a PCB creates unique challenges to the assembler due to conflicting requirements. With mixed technology boards, non-eutectic ceramic packages require a minimum volume of solder to achieve the desired reliability. However when these packages are combined with small passives (such as the 0201 / packages) and fine pitch packages, which require smaller volumes of solder, the release of solder paste from the stencil becomes an issue. Board stability and dimensional accuracy are also critical to achieving printing and placement accuracy. The stability issue is further exacerbated for smaller components and finer pitches. Today, the stencil printing process is solving this problem by designing multi thickness or stepped stencils, which allow for depositing larger volumes in one region of the substrate and smaller volumes elsewhere. However, because of the dynamics of the paste roll and squeegee issues, a considerable keep-out area around the higher volume materials is required. It is projected by, that designers will need to begin violating these keep out regions - driven by the increases in frequency and I/O density. The industry will need to develop technologies that allow for increased transfer efficiencies in thicker stencils and smaller apertures. This development effort will require cooperation from the stencil manufactures as well as the equipment and material manufacturers to be successful. Proposed techniques of positive pressure printing, vibration, off contact, and vacuum printing need to be investigated to address this problem. It is projected that these immediate challenges will continue as I/C package sizes continue to increase and SIP packages become more common - while passives and no lead (QFN / MLF) packages decrease in size and lead pitch. This continued challenge to the paste deposition process will lead toward the development of new dispensing or patterning technology. Through patterning technology, interconnect material would be patterned on the PCB without the use of a mask, stencil or screen. It is forecast that by 2009, there may be an adoption of new patterning technology. This technology will allow processes to be data driven, allowing for rapid low cost changeover. However to make this a viable technology, a significant focus is required on the speed. The dispense speed must be less than 0.05 seconds per dot using standard available solder paste formulations (whereas solder paste cost cannot increase significantly to achieve patterning technology) and must be able to handle the spectrum of volumes. Furthermore, because of the smaller pitch and package size, it will be necessary to decrease the minimum deposit volume by 2.5 from today s state of the art. To meet the needs of these mixed technology boards of the future, development work needs to be accelerated and the capability brought to the manufacturing floor by. The challenges for both the stencil and patterning technology will be the decreased pitch and package size requirements. With the introduction of packages in, it will be necessary for the stencil designs to provide sub 12.5µm accuracy. This will require the stencil manufacturers to not only develop improved processes, but also to provide for measurement systems to ensure the process is in control. For the patterning technology, it will be necessary to begin the development of high-speed linear motor systems to support the improved accuracy. inemi Technology Roadmaps 39 January

42 Mixed technology boards bring tighter requirements for paste volume control. Over the past several years, the industry has seen the introduction of many standalone 3D paste inspection tools that provided 100% coverage. However, these tools are challenged with programming / set-up time, capital cost and cycle time issues, as well as measurement repeatability issues. To support the conversion cost targets for the future, inspection technology will need to be integrated with the printers - allowing for closed loop adaptive control of the process. Many of the printer equipment manufacturers have already begun this development effort and are offering 2D and 3D inspection systems. Historically the primary issue with any 2D and / or 3D post print inspection system integrated into the printing equipment is the impact on the printing process cycle time. Many high volume manufacturers cannot afford" the increased cycle time to their printing process resulting from 2D and / or 3D post-print inspection performed by the printing equipment. If the equipment is performing inspection, it cannot print boards and feed the up stream equipment. In 2006, printing equipment with dual process capability was introduced. This equipment is capable of performing several printing process overhead functions (any function not directly involving the printing of material onto the substrate) in parallel (at the same time). This parallel process equipment offers a significant improvement in printing process cycle time for some high volume manufacturers. Recently 2D post print inspection systems have been introduced that are integrated into the printing equipment and that can perform 100% post print inspection at line speeds on moderate sized boards (for example cell phone boards). This high-speed 2D inspection capability along with parallel process equipment provides significant improvements on the printing process cycle time. It is forecast that by 2008, the printer equipment manufacturers will begin to offer 3D volumetric inspection systems integrated into their platforms, solving the programming concerns. The key to adoption of this technology will be the release of these systems at costs, which allow for rapid financial payback. Operational costs for material application processes have made many advances in recent years with the development of paperless cleaning systems and enclosed print heads. However, in order for board assemblers to continue to hit future cost targets, it will be necessary for the cost of operation of the printer to decrease. inemi Technology Roadmaps 40 January

43 Solder Paste Printing Technology Parameter Metric Mixed Component Technology 0402 with pin in paste 0.4 mm CSP s / 0201 with pin in paste 0.3 mm CSP s / with pin in paste 0.3 mm CSP s / with pin in paste with pin in paste Accuracy X & Y 6 sigma Aperature to fids (um) Stencil Technology Repeatability X & Y6 sigma Aperature to fids (um) Area Asspect Raito (AAR) Laser Cut Stencil Area Asspect Raito (AAR) Electroform Enclosed Print Heads material compatibility Compatible with all tin lead and lead free solder pastes Vision alignment accuracy and repeatability at 6 sigma Repeatability X & Y6 sigma Paste to fids (um) Printer Accuracy Accuracy Theta 6 sigma Paste to fids (deg) Repeatability Theta 6 sigma Paste to fids (deg) Repeatability Print Pressure 6 sigma Paste to fids (N) Cycle Time Transport in, board alignment, transport out 10 seconds 6 seconds 5 seconds 4 seconds 3 seconds % of 18x18 board covered On Board Paste Inspection within cycle time 10% 15% 75% 100% 100% Programming Time 30 min/board 20 min/board 10 min/board 5 min/board 5 min/board Cost of operation (supplies, power, etc.) Reduction in operating cost 100% 70% 60% 50% 40% Total set up time Total time from product run to next product run 20 minutes 15 minutes 10 minutes 8 minutes 5 minutes Table 16: Printing Process Application Technology Needs Reflow The reflow process has seven key metrics covering the materials, process, and equipment capabilities required for the reflow process to create satisfactory interconnects. The seven metrics are: Temperature Delta Performance Cost of Operation Inert Capability Traceability Cooling Rates Changeover Time Flux Management The most significant challenge to the cost of operation has come with the implementation of Pbfree processes. With the reflow temperatures increasing by nearly 35 C, energy consumption will increase. Furthermore, with the reduced solderability of Pb-free materials compared with tin lead materials and the new learning curve associated with reflow processes and the associated conversion management, it is anticipated that there will be an adverse effect on defect per million opportunities (DPMO) in the near term. A study conducted by a major materials and equipment manufacturer forecasted 15.2% increase in reflow operating costs due to the Pb-free implementation. The reflow oven manufactures are exploring more efficient reflow technologies - possibly combining reflow technologies, such as thick film elements, microwave elements, positive thermal expansion elements, and induction heating with conventional convection reflow. In addition to the energy consumption associated with the ovens, as mentioned previously, the lead-free solders have lower wetting forces, resulting in process engineers increasing the use of inemi Technology Roadmaps 41 January

44 inert atmospheres, to open the process windows. Therefore, it is critical that oven manufacturers make further reductions in nitrogen consumption to reduce the overall cost of operation. As the flux chemistries evolve and improve, nitrogen usage will decrease; however, it will take several iterations to achieve the desired result. There have been discussions around the return to vapor phase technology, but at this time, it is only being considered for niche applications where convection ovens cannot sufficiently heat an assembly and maintain an acceptable temperature delta across the board.. The second area of concern is the traceability associated with the implementation of Pb-free soldering. For reflow, it is critical to link the profile on the oven to the job on the manufacturing line and ultimately the bill of materials to ensure product reliability associated with Pb and Pbfree assemblies. The industry has already reported cases where products were unknowingly assembled with inappropriate reflow profiles causing increased field returns. This issue will become more prevalent as typical high mix manufacturers come on the market. The current technologies are messy to interact with and not scaleable to support worldwide applications. Evolution of these capabilities as well as integration into the SMT lines is required to ensure success. The near term challenge is for equipment manufactures to focus on adoption of Extensible Markup Language (XML) standards published by IPC. XML will be the vehicle for fully closed loop control systems, which are forecast to be in place by Better predictive profiling, coupled with in-line monitoring and closed loop control, would be needed for reflow ovens of the future. Another area of focus for the reflow will be product changeover time. For most manufacturing lines, ovens are not the gate to throughput. However, as pick-and-place and printing processes begin to meet their changeover goals, the ovens will become a gate. In some applications, this gate is real today and compromises are being made by the process engineers to establish common profiles for all products on a particular manufacturing line. Therefore, this need will become significant in 2013 where the changeover time is forecast to be less than 10 minutes. One possible opportunity would be for the ovens to cascade the zone changeover as a previous assembly progresses through the oven. The technical challenge for this approach is to ensure that the re-set of zones does not alter the previous product s oven profile. In addition to these trends, the roadmap identified issues with the current flux chemistries and flux collection systems. The current flux collection systems need to focus on improvements to minimize maintenance down times. Furthermore, the flux chemistries need to take a green focus and eliminate the need for flux collection systems. Some new chemistries providing potential solutions to this problem may be based upon chiral ionic liquids (which are salts that are liquid at room temperatures), that can be tailored to the application. Even with the development of green flux chemistries, it is necessary to evolve the reflow ovens and chemistries to reduce the maintenance of the tunnels. The current self-cleaning systems are time and energy intensive. The impact of these systems on the total cost of operation does not provide sufficient return on investment to be widely adopted. There may be an opportunity for inemi to facilitate a consortium effort between the flux formulators and equipment manufactures addressing the issue. inemi Technology Roadmaps 42 January

45 Reflow Soldering Technology Parameter Metric Cross Conveyor Uniformity at Peek temperature - LF profile ( C) Along Conveyor Uniformity at Temperature Delta Performance Peek temperature - LF profile ( C) Peek Temperature Repeatability of a given thermal couple at 6 sigma ( C) Inert capabilities scfh (ppm levels) Cooling rates solder joint realiability 4 degrees/seco nd 6 degress/second Flux Management flux collection Single Pass Collection Self Cleaning Self Cleaning Advanced LF flux chemistries to reduce contaminates Elimination of flux management Cost of Operation, Energy & Consumption Reduction in operating costs 100% 70% 60% 50% 40% Traceability Change over time Ability to link process parameters to and chageovers to equipment Ttoal time from one product to the next with significant temerpature (profile) change GEM/SECS Auto collection of Dat logging XML data and connectivity SPC warnings Closed loop control Tracking of all products and material proceessed 25 minutes 20 miniutes 17 minutes 15 minutes 10 minutes Table 17: Reflow Technology Needs Cleaning The requirement for cleaning assembled printed circuit boards is driven by two factors: the type of solder paste or wave and hand soldering flux being used, and the end use of the product. If an active flux is used, it must be cleaned for product reliability reasons. A good deal of the fluxes being used today are no clean fluxes and do not require cleaning. However "no clean" fluxes are not "no residue" fluxes. Some amount of inactive residue remains on the assembled board with no clean materials. Some products and customers will require no clean inactive residues be cleaned because of end-product performance specifications. inemi Technology Roadmaps 43 January

46 There are two primary issues with a cleaning process: Capability to clean under miniature components Capability to have 100% clean ready for test assemblies exit the cleaning equipment Cleaning Technology Parameter Metric Under miniature components stand off height 200 comp comp. Test ready rinse/dry capability 100% Dry ready for test 100% Dry ready for test Table 18: Reflow Technology Needs 01005/.4mm CSP 100% Dry ready for test 01005/.4mm CSP 100% Dry ready for test 01005/.4mm CSP 100% Dry ready for test DISPENSING/UNDERFILL The Dispensing process covers a magnitude of applications and assembly materials. These range from SMA (surface mount assembly) glue and silver / solder pastes, to thermal interface materials (TIM) and underfills. To understand the capabilities and limits associated with each process, we have separated the applications into filled and unfilled materials. Underfill is as a separate process. We have also only focused on actual equipment parameters and challenges, although the dispensing process roadmap is closely connected to materials development. In the general dispensing category, five key metrics are identified. All of these are considered to require significant research and development focus in the next 3-5 years to meet industry expectations: Dot Diameter (Filled) Wet Placement Accuracy Dots per Hour Process Control Fine Line Capability (Unfilled) As outlined in the Situational Analysis and other sections, there is a move toward passives and a requirement for data driven interconnection processes. As such, both the speed of dispensing and dot size will need critical attention. In particular, the dot size of filled materials (such as solder paste) needs to decrease by a factor of 4, and the speed of dispense needs to increase by a factor of 3, to meet these requirements and to keep up with pick-and-place equipment. To support the moves to finer pitch and increased PCB density, the wet dot placement accuracy needs to reduce three fold. Current capabilities will reach their limits by Beyond this, significant investment in development would be required in materials filler contents and equipment speeds. In conjunction with this, a need is identified to monitor and control the process without becoming the bottleneck. With an increased requirement for optical, UV and thermal interface material deposition, as well as continued SiP and PoP (Package on Package) type packaging migration into the second level assembly, fine line dispensing and jetting capability is also considered to be a key area of development. Current capability is seen to need to improve by a factor of 10 or more. A significant need for development is required after 2009 to meet these requirements in both pump and jet technology - as well as the equipment capability specifically in the Z dimensional control. In the underfill process, four key metrics are identified. All four areas will require continued development, and two were acknowledged as requiring significant research focus. inemi Technology Roadmaps 44 January

47 UPH (based on 10mm sq. CSP) Volume Control (based on 15mg weight) Keep Out Zone Control Wet Out Zone Control Process Control The increased device placement speeds will require a five-fold increase in UPH. The challenge to the underfill application UPH is not so much the dispensing equipment but the flow out times of the materials - especially with larger CSP and lower bump heights. As component densities increase, there will be a need to control the keep out and wet out zones to reduce contamination of devices in close proximity to the packages. As the industry adopts larger dies, smaller and controlled dispensing volumes in the single digit nano-liter range, or lower mg weights will be required, especially in the medical electronics and portable electronics sectors, requiring closed loop weight measurement for process control. With the reduced dot size, the current process control method of dispensing a number of shots and measuring the weight becomes less effective. Research will be required to develop new control methods which measure both the shot volume but also the dot consistency. By 2009, it is forecast that this capability will be in place. The next challenge to the underfill process is the cure method. Historically, capillary underfills have required extensive cure times, forcing these processes to include long oven or batch processes. Today, snap cure materials are becoming available; however, in order to reduce the cost of operation, new technologies using nano-materials will be necessary. It will be through these nano-technologies that the material properties can be turned on and off, and thus truly instantaneous cures can be achieved at low temperatures. (See Quantified Key Attribute Needs Materials for further information). inemi Technology Roadmaps 45 January

48 GENERAL DISPENSE CATEOGORY Parameter Comments Dot Size Metal Filled Materials Solder Paste Best Case Scenario with common fluids 200µ 150µ 125µ 100µ 50µ Silver Flake Best Case Scenario with common fluids 125µ 100µ 75µ 50µ 50µ Dots per Hour Single Dispense Head - IPC >75000 Wet Dispense Accuracy Dot Placement 3 Sigma 75µ 50µ 25µ 25µ 25µ Fine Line Capability Typical Un-Filled Materials 100µ 75µ 50µ 25µ 25µ Process Control Dot or Line Verficaton Vision Based Vision Based Vision or Laser Vision or Laser UNDERFILL DISPENSE CATEOGORY Parameter Comments UPH 10 X10mm CSP single pass 200µ bump height Vision or Laser >10000 Volume Control As a % on 15mg dispense weight 5% 3% 2% 2% 1% Keep Out Zone Control Process Control Best Case Scenario for controlling wet out 500µ 250µ 200µ 175µ 150µ areas for no contamination Closed Loop Methodology for Volume Weight Scale Weight Scale Laser Scan Laser Scan Laser Scan ocntrol Key Current Capability In Development Research Needed Table 19: Dispense and Underfill Technology Needs PART PLACEMENT The part placement process has forecast 18 key metrics covering the placement speeds, accuracy, and operational capabilities. There are nine key metrics identified which will require attention over the next several years to support both the second level assembly and first level assembly technology needs forecast by the product emulators. In order to improve the process yields, focus on real time feedback systems and inspection technologies can offer the greatest benefit. Since the 2004 roadmap, pockets of line level feedback technologies have been developed; however, these technologies are dedicated to equipment sets and have not been brought into high mix manufacturing. Partnerships between inspection technology companies and pick-and-place vendors are occurring; however, interoperability across vendors is an issue. Since the 2004 roadmap, there has been an explosion on the market of paste inspection technologies. These systems have aided in the understanding of the correlation between paste defects and assembly defects. The next challenge for the industry is to monitor the incoming component quality real time, during the placement process. This challenge is further complicated by the need to have these inspection tools integrated into the placement equipment and to provide a reasonable return on investment. inemi Technology Roadmaps 46 January

49 As with first level assembly conversion cost reduction, second level assembly conversion cost reduction has been realized by the movement to low cost labor markets. With many of these benefits already realized, a renewed focus on productivity is necessary. The current forecast on the average mean time between assists (MTBA) shows a need for more than double the time between assists in the next several years. In order to achieve this goal, the human interactions for these assists must be eliminated. Furthermore, the level of assists increases exponentially as the manufacturing order run size decreases. To achieve these goals, interfaces that report real time performance of the line need to be adopted - and emphasized - in assembly manufacturing. It is forecast that the degradation in productivity in the placement process - in a high mix manufacturing process - has to improve by 50% by Again, the environmental regulations will have an impact in this process. To ensure environmental compliance, interoperability of the traceability and ERP systems will be necessary for large scale operations. These traceability requirements are becoming more common with medical, automotive, and military environments. With the adoption of flip chip technology for component packaging, the accuracy of the current flip chip equipment must be matched to the second level placement speeds. As outlined with the 2004 roadmap, an integration of odd form capabilities will challenge the industry. In particular, integration of press fit technology in the SMT process will improve productivity with the higher adoption of flexible tooling. Another challenge for the pick-and-place process will be to support the migration to flexible circuit assembly technologies. The portable product emulator is predicting flexible circuits to be the primary substrate by This will challenge the pick-and-place process since current technology has board handling utilizing pallets; new concepts for board handling are required. As always, board assembly is driven by conversion costs. In addition, pick-and-place equipment is the largest contributor to the capital equipment budget of most manufacturers, and it is becoming increasingly important for the equipment s to provide increased capabilities with aggressive pricing. With high mix manufacturing becoming more common, as described earlier, the feeder inventories of the board assembly operation are increasing. One key area that second level assemblers are looking for is significant cost reduction with the feeder bases. inemi Technology Roadmaps 47 January

50 Parameter Comments Metric Speed - Throughput Chip Placement Speed Chip Placement - IPC 9850 cph per meter sq (0603) IC Placement Speed - Large Size IC IC Placement - IPC 9850 cph per meter sq (QFP 208) IC Placement Speed - Medium Size IC SO Placement - IPC 9850 cph per meter sq (SO-16) CPH per square meter using the IPC 9850 standard for 0603 CPH per square meter using the IPC 9850 standard for QFP 208 CPH per square meter using the IPC 9850 standard for SO-16 12,000 15,000 16,000 17,000 20,000 1,200 1,500 1,600 1,700 2,000 5,400 6,750 7,200 7,650 8,000 Accuracy Operational Features IC Placement Speed - Flip Chip Die Placement - 2 x 2mm CPH per square meter 5,000 6,000 7,000 8,000 10,000 Placement Accuracy Chips 6 sigma X,Y placement accuracy Microns Placement Accuracy Fine Pitch (leaded) 6 sigma X,Y placement accuracy / rotation Microns/degrees 55 / 0,8 50 / 0,7 45 / 0,6 40 / 0,5 40 / 0,5 Placement Accuracy for components with balls, bumps - CSP, BGA, FC 6 sigma X,Y placement accuracy / rotation Microns/degrees 60 / 0,8 50 / 0,7 40 / 0,6 35 / 0,5 30 / 0,5 Component Pick reliability Based on 0201 component packaged per EIA 481 DPMO specification 2,000 1, Placement Force - Chips Minimum Grams Placement Force - Fine Pitch Placement Force - Specialty Components Minimum Minimum Grams Grams Maximum Maximum Grams Grams 2,500 4,000 2,500 4,000 3,500 5,000 3,500 5,000 4,500 5,000 Feeder Capacity per Machine 8mm feeder/m Component height Larger electrolytics >10mm tall; Medium Sized IC Speed mm Component height Connectors, Modules on PCB; Large Sized Placement Speed mm Feeding Die From Wafer including die flip CPH 5,000 6,000 7,000 8,000 10,000 Changeover time in minutes Changeover time (different board width, 50 different minutes feeders, different nozzles) Preventative Maintenance Time based on 2000 hour operational time - 1 shift year hours/month Maintenance Skill Level Level 2 Level 1 Level 1 maintenance maintenance maintenance operator level operator level MTBF Machine MTBF (not including feeders) per SEMI-E10 Hours 1,200 1,500 1,800 2,000 2,500 MTBA (Mean time between assist) MTBA per Semi-E10 Hours MPBA (Mean placements per assist) Placements 80, , , , ,000 Advanced Calibration Tools limited stand alone machine fully integrated fully integrated fully integrated Table 20: Pick-and-place Technology Needs WAVE AND SELECTIVE SOLDERING Wetting and solder joint reliability of lead-free materials will alter the acceptance criteria for solder appearance, microstructure, and hole-fill. Solid correlation of fatigue fracture resistance to solder hole-fill is the key to define these criteria. However, data on lead-free PTH solder joints reliability is limited. More research is required in this area. One of the more significant challenges (in the near term for the assemblers) will be to support the reduced conversion costs, while retooling the old factories with wave systems for the lead-free process. Furthermore, the assemblers are challenged with productivity issues caused by changeover of the lines to Pb-free. Additional productivity issues will affect the assemblers as they re-train the personnel on the acceptance criteria of Pb-free. The adoption of Pb-free may come with equipment upgrade requirements. During the conversion period, there is a slight increase in the equipment upgrade / replacement and production cost. Due to the immaturity of the Pb-free materials, the Pb-free wave and selective wave processes may have a drop in yield. However, it is expected that the Pb-free wave yield and operation cost will be the same as existing SnPb processes in the future. A conflicting challenge from the product emulators is the continued reduction in conversion costs. With pin in hole (PIH) technology typically requiring manual labor for assembly, these products will continue to migrate to the countries with the most abundant labor markets. Current flux usage varies in different product lines, ranging from 50% No-clean / 50% Watersoluble to 95% NC / 5% WS. WS flux is typically used in high end, high power, and wireless products to avoid ionic / organic contamination causing long-term signal reliability. However, inemi Technology Roadmaps 47 January

51 with the lower standoff on SMT components, overspray issues are becoming more significant with WS fluxes. Therefore, it will be necessary to advance the flux vehicles to resolve the contamination, electro-migration, leakage currents, and skin effects. No major change over time is expected on the percentage of utilization of pin-in-paste verses wave soldering. Due to the increased complexity of double-sided products, it will be necessary to advance the capabilities of selective solder systems. Furthermore, it is projected that with shrinking PTH connector pitch, the use of selective wave soldering will increase. It is expected that both conventional wave (plus wave pallet) will co-exist with selective wave soldering technology. As highlighted in the inemi 2004 roadmap, the challenge for the selective soldering systems is to offer low cost, compliant tooling. This trend will accelerate further improvement in achieving compatible solder hole-fill (especially on thicker PCBs with concern for contact resistance variation and high signal integrity). With the adoption of high cost alloys for lead-free processing, it is becoming more attractive for board assemblers to replace existing wave soldering equipment with selective soldering equipment. The reduction in through-hole technology is an enabler for this transition as well. A challenge for the industry will be to develop a selective wave pallet, design guideline. Standardization will dramatically reduce the defects at manufacturers and allow cost effective manufacturing processes to be established. It also needs to verify if the design guideline for wave soldering still remains the same for tin-lead and Pb-free wave soldering. This guideline needs to address reliability correlation to interconnection, hole / pin ratio, surface finish, thermal relief / solder theft, anti-pad / thermal strap design, and annual ring. Furthermore, the guideline development effort needs to address the reduced land patterns and new substrate materials forecast in the roadmap. A significant cost impact projected by the inemi roadmap is the increased use of inert atmospheres. This increase is projected because of lower wetting of the Pb-free alloys. To enlarge the process window, assemblers are beginning to increase the use of nitrogen. However, with this increased use comes a significant cost increase. Better low volume inserting methods are required with advances in flux chemistries to promote wetting of the solders. When Pb-free wave soldering processes becomes more mature and better lead-free wave soldering flux materials are available, it is expected that nitrogen usage will be dropped to existing tin-lead processes. Greater monitoring of the pot composition and contaminant levels will be needed to understand how contamination / composition changes over time, accompanied by tighter controls at the wave to prevent cross-contamination. inemi Technology Roadmaps 48 January

52 Parameter Metric Wave/Selective Solder VOC free (%) Flux Halogen free (%) Utilization % LF Wave/ Selective Lead- Free Alloy % SAC vs. other LF alloy 95/5 90/10 80/20 80/20 70/30 Minimum feasible PTH pitch in wave/selective soldering Mil [mm] 80 [2.00] 60 [1.50] 50 [1.27] 50 [1.27] 40 [1.00] Conventional/Selective Wave Soldering utilization % (conventional/selective) 80/20 75/25 70/30 70/30 65/35 SMT paste in hole/wave Soldering Utilization % < 5 % < 5 % < 5 % < 5 % < 5-10 % Pre-heat Temperature Process Wave pot Temperature 0 C C Wave/Selective solder second contact time Environment process N 2 /Air 50/50 60/40 60/40 50/50 50/50 Table 21: Wave and Selective Soldering Technology Needs PRESS FIT The scope of the Press-Fit / Compliant Pin issues discussed here includes placement of parts, insertion, retention, inspection of non-protrusion, material traceability, process traceability, repair, connector trends, and surface finishes. The Press-Fit / Compliant Pin connection is an interconnection technology that has been in use for decades to provide both an electrical and a mechanical connection. This technology is primarily in use in backplane / midplane designs as well as on the connectors that interface with these boards. As mentioned in the 2004 roadmap, s may migrate more to Press-Fit connections in order to avoid hole fill issues. This has not been observed yet, but may be on the horizon. 1. Placement The industry currently uses manual placement to load connectors onto the fab before the press operation. The operator is guided by a light station or a visual diagram (or both), to place the connector in the correct location and orientation. This slow process is manually intensive. There is very limited equipment in place currently that is fully integrated (pick, inspect, place, and press) to automate the placement of connectors on the boards. The ideal situation would be to have an integrated final inspection after the press (pick, inspect, place, press, inspect). One reason for the lack of equipment is the lack of standardization of connector trays. Connector inemi Technology Roadmaps 50 January

53 manufacturers tend to use trays that match their packaging, and an effort has not yet been made in the industry to standardize connector trays. This standardization will go a long way towards having machines that can automatically place parts for the press operation. As cost pressures increase, throughput will become more of a focus, and there will be more demand for automatic placement machines, provided that they can do some (if not all) of the following steps: pre-inspection of the parts, placement, and then an inspection before the connector goes to the press. The actual connector s true position and average offset of the wafers also play a role in the ability to place a connector properly. Having an automated process should eliminate some of this variability and report when there are issues. 2. Insertion The insertion operation is the most obvious portion of the press-fit process. The main concern with inserting (pressing) the connector into the board is making sure that the pins enter the holes correctly and provide the desired electrical connection. Issues observed are: Pushing the pin in without buckling the pin on the outside of the board (Accordion) Not pushing the barrels out (The separation of the inner layers / separation of traces is not visible. The barrel may stay in place separation may occur) Penetrating the barrel and cutting through the copper with the EON (Eye of the Needle) The second and third concerns are easily addressed by using the correct hole size for the connector pins. However, the first concern of buckling the pin has a large reliability risk due to lack of inspection means - the buckling issue is addressed later in the chapter. One other area of concern is the speed of the press. Insertion speed, EON design and board finish contribute to this type of failure. Currently, throughput issues are mitigated by adding more presses to the assembly line. This area is being researched by the press manufacturers as the speed of the press needs to be balanced with the risk of damage to the pins due to misalignment. 3. Retention Force Retention force is an indirect measure of normal force. It is a measure of both a good electrical and mechanical connection. The compliant pins of the connectors will become thinner, so ensuring a gas tight connection that is stable for life will be an area of concern. Thermal cycling also affects the long term retention force. 4. Inspection Inspection is one of the most critical areas of the press operation. Regardless of the type of deformation (accordion, smashed, etc), the primary concern is a connection that may pass an open / short test but fail in the field due to the connection opening up. This can occur because the pin can short to the top of the barrel and then consequently pass the electrical test. If the pins are long enough to protrude through the board, AOI or visual inspection can easily catch a pin that has not protruded through the board. inemi Technology Roadmaps 51 January

54 If the board is thick enough that the pins cannot protrude through the board, even when inserted properly, the inspection becomes tougher. Depending on the depth of the tip of the pin, different methods can be attempted, but there is currently no scaleable solution for all situations. Currently the feedback system of the press is used at many assembly sites to determine if the press was successful, but even this method is not 100% accurate. The following methods are in use or have been looked at, but none work in all situations. AOI inspection, but depth becomes a problem Glowing / reflective materials on pin tips (for AOI) Laser based inspection X-ray Contact used to measure depth Visual with microscopes Preloading holes with displaceable material The most difficult inspection of all in the press-fit process is when two connectors are pressed back to back on a thick fab with pins from each connector going into the same hole. There currently is no way of accurately determining if both connectors pins are inserted into the barrel. 5. Material and Process Traceability Customers are starting to require traceability of components used in a system and the process used to build a particular system. Software tools are showing up in the industry to address this issue. However, some areas of concern still exist. When one wafer is used to replace a defective wafer in a connector, how can this be captured? Wafers are not always identifiable to a specific lot. Statistical Process Control (SPC) will become utilized more as a means of reporting and process improvement Machines need I/O capability to report data to a central system 6. Repair The ability to rework an individual pin in a connector is a process that does not have much control built in it. Many sites use pliers to pull the pin even though most connector companies sell repair tooling. There may be a need in the future to develop common tooling to rework connectors, but for now, as long as keep-out zones are maintained, specialized tooling can be used. It would be beneficial if the connector companies designed in a grip area on the connector body to facilitate the removal. 7. Connector Trends While most of the connector issues are cost related, there are a couple of issues related to the press operation. The first is that the most challenging part of manufacturing a compliant pin connector is punching the eye of the needle. The carbide punches are becoming very small and having the correct hole punches ensures the compliancy of the pin. The other trend is that pins are spaced closer together over time, which increases the difficulty to meet the true position requirements. inemi Technology Roadmaps 52 January

55 8. Surface Finishes Many surface finishes are used across the board industry, but the one that is causing some concern now for the press industry involves the use of Tin. Due to the compression of the surface finish in the barrel, and the fact that some pins are coated with tin, the growth of tin whiskers is a concern. REWORK AND REPAIR The rework and repair processes are broken down into three processes: hand soldering, pin through-hole rework, and area-array package rework. Each process has key metrics identified. For hand soldering rework, 0.4mm lead-frame package is identified as the finest lead-to-lead pitch for both tin-pb and Pb-free processes. Reworking a 0.4mm pitch is currently doable. On the discrete side, some challenges are outlined for reworking More importantly, the question of whether to rework or not has been found to be product dependent; a rework process for is needed for high cost products. Developing a process for increasing hole fill has been identified as a major developmental need when using a minipot rework equipment. Aside from this, critical metrics for PTH rework are identified. Some developmental work is currently on going; however developing a process to remove and replace a through-hole part in a single step needs continued work. This single process is dependent on the type of part that is being reworked. The drive for a single process is to limit the total contact time that the board makes with the molten solder. Reducing the contact time would help sustain PCB laminate integrity and more importantly, to minimize the copper dissolution currently observed during the minipot rework of PTH connectors. A key metric is also identified for reworking PTH parts. Currently, 25% of the PTH parts are being reworked by hand for both SnPb and Pb-free. In order to increase throughput and consistency, this number is expected to drop to 5% by 2010 for SnPb and by 10% for Pb-free. Pb-free tacky flux appears to be in the early development stages. Testing results from multiple companies indicated that in some cases, flux evaporated too early in the soak reflow profile, causing solder wetting issues. To enhance wettability, some No-Clean (NC) flux may contain high corrosive ingredients that may cause electrical faults and electronic migration issues. Corrosion from Water Soluble (WS) flux is less sensitive as compared to NC, although the cleaning on WS flux residue needs special attention in low standoff locations. Furthermore, to enhance solder-ability, some fluxes may contain excessive resin (as thermal stabilizers) and may cause printability problems when applied with micro screens. For solder paste printing in a BGA rework process, the mini-stencil paste printing method is still widely used. Paste dispensing is an alternative printing technique. Dispensing is still plagued with the creation of long tail defects and many paste configurations have paste volume repeatability issues as compared to the stencil printing process. Paste printing directly on BGA balls has shown encouraging results and has less flux residue issues. This process is beneficial for small pitch packages that do not require special tooling or enhanced paste volume requirements. More automated printing equipment is needed to improve productivity. inemi Technology Roadmaps 53 January

56 Mini-stencil paste printing is still the major trend with 75% intended use until 2017 for both SnPb and Pb-free rework processes. There is a need to wait until the PCB cools to ambient temperature after redressing. Mini-stencil paste printing may have difficulties for 0.4mm pitch packages - such as chip scale packaging (CSP). Flux dipping is used to avoid the difficulties associated with paste printing. By considering that the solid solder contribution to the total volume of a solder joint is less than 5-10%, there is no significant standoff difference and correlation to reliability. The flux only process is expected to stay steady from now until Rework equipment will need to be capable of Pb-free processing. Since the process window for reflow has narrowed, there may be a need to develop special tooling (e.g. baffles in nozzle designs) and software control on rework temperature profiles. This is critical as package size to be reworked is expected to be >50mm for SnPb and Pb-free. Improved mechanical brushing processes are required to maintain PCB integrity during rework processes. This challenge is exacerbated by the introduction of Pb-free processing, due to the higher process temperatures. Lifted pads and mask damage can occur during the site redressing process. A non-contact vacuum site redressing method has been used more recently to help mitigate the lifted pads and mask damage. Currently, 25% are using a non-contact approach to redress the site versus the traditional solder wick and iron approach. This percentage is anticipated to grow to 75% for Pb-free site redressing. As with the SMT process, the MSL (Moisture Sensitivity Level) issue will play a significant role in the productivity and reliability of the rework process. Because of the potential of mixed technology entering the rework process, it will be necessary to identify on the package when moisture sensitivity issues are present. The industry needs to adopt standards (e.g. JEDEC) to facilitate a part MSL level coding standard. To further increase the productivity of the rework process, methodologies need to be developed which provide higher heat transfer rates. This roadmap is projecting the increased uses of laser technology in the future; however, the capital cost of laser systems is inhibiting the wider adoption of this technology. inemi Technology Roadmaps 54 January

57 Hand Solder Rework Soldering Process Parameter Metric Smallest lead-frame pitch to be reworked by SnPb hand mm Smallest type of discretes being reworked Smallest lead-frame pitch to be reworked by Pb-free hand mm Smallest type of discretes being reworked Pin Through Hole Rework Soldering Process Parameter Metric Type of preheat used - Convection Convection Convection Convection Convection SnPb Rework approach PTH rework by hand % Type of preheat used - Convection Convection Convection Convection IR Pb-free Rework approach PTH rework by hand % Note: Rework Approach Options: 1-Remove and replace within one cycle, 2-Remove in one cycle then replace in another cycle, 3-Remove in one cycle, remove solder (by hand), then replace in another cycle Key Current Capability In Development Research Needed Array Package Rework Soldering Process Parameter Metric Maximum package size mm Minimum package size mm Minimum reworkable pitch mm Target delta T across solder joints C <10 <10 <10 <10 <10 Typical rework profile length (time) min SnPb Number of allowable rework on PCBA # Type of rework (Conv./IR/Laser) % 100/0/0 100/0/0 100/0/0 75/25/25 75/25/25 Type redress approach (NonContact/SolderWick) % 25/75 25/75 25/75 25/50 25/25 Type of medium deposit (Paste on PCB/Paste on Part/Flux only) % 75/0/25 75/0/25 75/0/25 75/0/25 75/0/25 Maximum package size mm Minimum package size mm , 7 5 Minimum reworkable pitch mm Target delta T across solder joints C Typical rework profile length (time) min Pb-free Number of allowable rework on PCBA # Type of rework (Conv./IR/Laser) % 100/0/0 100/0/0 75/25/25 75/25/25 75/25/25 Type redress approach (NonContact/SolderWick) % 25/75 25/75 50/50 75/25 75/25 Type of medium deposit (Paste on PCB/Paste on Part/Flux only) % 75/0/25 75/0/25 75/0/25 50/25/25 50/25/25 Key Current Capability In Development Research Needed Table 22: Rework and Repair Technology Needs DIRECT CHIP ATTACH With the drive toward miniaturization, the process for direct chip attach directly onto the main boards is becoming another option in the board assembly process. Direct Chip Attach (DCA) includes both the wirebond version and the flip chip type of package attachment. For the purpose of this discussion, a flip chip is considered a package with a pitch <0.4mm. It is believed that at this pitch, the assembly process needs to change in order to accommodate a flip chip process. In other words, the flip chip package cannot be placed with a traditional SMT inemi Technology Roadmaps 55 January

58 process. In some cases, the flip chip needs to be flux dipped or flux applied to the bumps instead of the traditional screen printing process. For this section, it is assumed that the flip chip process is still a soldering process and not one of the other types of flip chip process techniques (such as anisotropic conductive adhesive, thermosonic or thermocompression bonding, etc.) Issues for the adoption of these technologies are largely the same as with any DCA process. The known good die issue can be a significant one, as the ability to rework the components is limited and the costs of scrapping the main boards can become prohibitive. Another issue, especially for the wirebond version, is the metallization to be used. As gold wire bonding typically requires thick soft gold finish on the board, while SMT processes require a thin layer of gold to prevent gold embrittlement of the solder alloy. Parameter Metric Wirebond Flip Chip Component Pitch um Die Material material type Si Si/SiGe Si/SiGe/GaAs Si/SiGe/GaAs Si/SiGe/GaAs Wire Type material Au, Al Au, Al Au, Al Au, Al, Cu Au, Al, Cu Die Stacking # of die Component Pitch um > Die Material material type Si Si Si/Ge/GaAs Si/Ge/GaAs Si/Ge/GaAs Key Current Capability In Development Research Needed Table 23: Direct Chip Attach Technology Parameters Gaps and Showstoppers BUSINESS ISSUES, GAPS AND SHOWSTOPPERS The roadmap is predicting another migration to lower temperature and lower cost lead-free solder materials in This transition is based upon the need to lower the costs of the assembly materials, and decrease the processing temperatures once again. This transition to low temperature materials can only be accomplished once the Pb containing materials are removed from the process. Japan s JISSO roadmap is forecasting a similar transition. To be successful in this next transition, it will be necessary for the basic research to begin by and consensus gained in the industry to coordinate the transition. Capillary underfill systems have been the incumbent within the component and board assembly industries and will continue to be the process of choice for non-space confined applications. However, capillary underfill technology will continue to be challenged by large die and components combined with thin bond lines, more brittle Pb-free solder interconnects, spheres and balls. Underfill and fluxes must also be compatible in order to provide limited voiding and good reliability. Underfill compatibility will require continuous attention since new fluxes are continuously being developed and qualified for Pb-free applications. CSPs and Wafer Level Packages (WLPs) used in handheld devices typically require underfill for drop-shock reliability. Pre-applied underfill to substrate / wafer and fluxing underfill (no-flow) inemi Technology Roadmaps 56 January

59 will be options to alleviate dispensing problems due increased component density and tight geometries. The Pb-free conversion has also influenced the technology needs of underfills. Higher temperature Pb-free reflow profiles require underfills to have improved thermal and hydrolytic stability. This may require advanced polymer technology beyond present day epoxy technology. Improved JEDEC performance will always be a focus for formulators and material suppliers; however, the drive to eliminate dry bagging must be balanced with the difficulty in solving low K sensitivity and Pb-free interconnection. Pre-applied underfill technology has had limited success in the board assembly industry. Preapplied technology often requires temperature during the bonding process. Pick-and-place and flip chip bonding technology are limited as compared with semiconductor packaging where thermocompression bonding is well established. Due to this lack of equipment infrastructure within the board assembly industry, pre-applied underfill will likely have limited adoption. No-flow underfill technology allows for dispensing or screen-printing of the underfill before the pick-and-place process. This technology provides great potential to eliminate the time intensive capillary underfill step. In the reflow process, while solder joints are forming, the no-flow material cross links forming an epoxy bond between the component / die and the substrate. This technology has been challenged by outgassing of the components and substrate materials and with placement / design inducing micro voids. Voiding can be reduced if a pre-dry step of components and board is employed but increases cycle time and cost. Furthermore, interconnect formation with filled no-flow is more challenging than with unfilled systems. During the die placement step, filler particles may become trapped between the solder joint and bond pad, preventing the required contact for solder wetting resulting in non-wets and opens. Filler inclusion in the joint also compromises joint integrity and may influence current density. Recent advancements with nano-partial fillers in no-flow underfills have improved modulus and CTE characteristics, allowing for better penetration of this technology. However, because of the component / die placement issues and outgassing issues, this technology still has limitations due to voiding defects created. Research into new solder mask materials and good wetting no-flow materials is necessary for this technology to become common. Since the no-flow and pre-applied systems are balancing the solder formation with the epoxy cure requirements, the Pb-free process offers further challenges. Understanding polymer kinetics as well as solder wetting in viscous organic liquids may require further exploration. Continued material development is required for these systems to provide reliable and robust interconnect formation as well as meeting 260C Pb-free processing requirements. Epoxy systems are well understood in board assembly; however, with the WEEE legislation it will be necessary to fund research toward the development of materials that allow for recycling. This is most significant for the end product, but it is also significant for the package. The future may lie with nanotechnology providing materials that release on command but otherwise provide a permanent and reliable bond. inemi Technology Roadmaps 57 January

60 The need to develop Pb-free processes has resulted in higher tin containing terminations. Coupling this with the increased tin content of the solder, there is a renewed focus on tin whisker formation and growth. Use of conformal coatings is considered one of the mitigation methods. To support this solution, formulators need to accelerate development of coating materials that are compatible with the Pb-free no-clean flux systems. Test metrics need to be created on Sn whisker acceptance criteria and the effect of conformal coating in entrapment of these whiskers. With respect to conformal coating materials, Pb-free compatibility, VOC, and solids content are important. Higher coating solids percentage materials are required to provide a more elastic material that can be deposited as a uniform, thinner coating. This will allow more selective coating systems to be designed, which will substantially reduce labor-intensive processes, such as masking, inspection, and rework. As with the packaging industry, the board assembly industry must support increased R&D spending to sustain the historical growth in product capabilities and cost reductions. With R&D responsibility transitioning to the companies, and more critically to low cost geographies, consortium activities, especially for industry baseline, data development through organizations such as inemi, are becoming more important, since it allows for the sharing of fixed costs associated with such activities. The migration of traditional responsibilities (such as design, process, and technology development) to providers is also creating a fundamental shift in the industry. As s leverage their board assembly partners to reduce their own fixed investment, they are becoming increasingly dependent on the provider to support their R&D needs. A gap exists in the tools for collaborative development efforts between the and. To support the future product functionality forecast by the Product Emulator Groups (PEGs), a showstopper exists for the PCB / substrate to provide a low cost fine line technology. Government, industry consortia, and academia need to concentrate research funding to solve this problem. CROSS CUTTING ISSUES, GAPS AND SHOWSTOPPERS There is a need for PCB suppliers to continue to improve the availability of high reliability Pbfree substrates (boards) capable of withstanding Pb-free assembly temperatures and reflow cycles, as well as prior pre-heat cycles, while maintaining dimensional stability. Initial versions of such laminates have been developed and commercialized and are undergoing improvement. As the Pb-free transition accelerates, component suppliers need to provide more information on the package s ability to handle Pb-free process temperatures. As with the Pb-free solders, the industry needs to develop a fundamental understanding of Pbfree solder material metallurgy, processability, and reliability. 1. Solder Paste Although SAC is the current favorite choice for Pb-free solder, work is required today on the next generation of solder materials that promise a higher reliability and a wider process window. inemi Technology Roadmaps 58 January

61 With the government funding of nano technology materials underway, the next challenge for board assembly will be to take this leading edge technology into mainstream manufacturing. As was seen with conductive epoxies and the transition to Pb-free, migration from the status quo will be a struggle. inemi and other consortia need to fill the gap of bringing these technologies to market by developing projects which explore the emerging technologies while spreading the burden of the costs. 2. Reliability With the emergence of the Pb-free solders, the impact on the long term reliability is not completely understood. More work in this area needs to be done, as well as the possibility of more reliable alloys. PROCESS TECHNOLOGY GAPS AND SHOWSTOPPERS The widening range of required paste volume deposited on mixed technology assemblies is pushing traditional stencil design rules to their limit and prompting the use of alternative solutions (improved stencil material quality, use of step stencils, and use of double pass printing). There is a need for stencil technology to handle increasing fine pitch array package styles. Other paste application technologies (such as dispensing or jetting) also need to be developed to offer a robust process for paste deposition. For the reflow process, there is a gap in being able to support the cost targets within the transition to Pb-free due to increased energy consumption and short-term yield issues. This conversion cost gap is further exacerbated by the need for increased traceability of material and processes to handle increasing high-mix, low-volume and increased part numbers associated with the introduction of Pb-free. The and manufacturers need to work on creative, engineered solutions that address these gaps near term, while full turnkey solutions need to be developed in the long term. With the trend identified by the PEGs of increased operating frequencies in products, and the increased use of flexible circuits, a gap in the equipment supply base exists to support material handling of flexible / low loss substrates. Continued gaps exist in the development of automated printing, dispensing, placement, and rework equipment to handle pitch requirements below 70 µm (at current process speeds) and associated second level assembly. Larger body sizes to 70 mm will also provide challenges to rework processes and placement processes. Development of reworkable underfills will be necessary to enable the further adoption of these packages and fine pitch area array technology. Product cleanliness will become more significant as pitches decrease. A gap exists in providing an industry standard for ion chromatography testing as related to product reliability. This lack of standard can be correlated to longer new product introduction and higher field reliability testing. The Dispensing and Printing Deposition equipment development is tied to Materials innovation more than any other portion of board assembly. Equipment enhancements are gated by the inemi Technology Roadmaps 59 January

62 ability of materials to obtain the same advanced levels in capability, especially when it comes to micro level dispensing. Since the last inemi roadmap was published, there has been a significant shift from traditional needle dispensing to Jet Dispensing. Industry collaboration between materials suppliers and equipment vendors is crucial to ensure that materials development matches the dispense methodology applied. The development of nano-fillers for filled metallic compositions such as solder paste will need to be employed to allow for the smaller volumes of deposited materials the industry is expecting from data driven as well as printed applications. In addition to this, current closed loop control such as weight scale is no longer an efficient way to maintain volume controls. Significant development is required in both deposition and measurement technology. Pb-free wave and selective soldering requires an increase in the process temperature. However, the existing wave flux materials are not well designed for Pb-free, high temperature processes. At high process temperatures, wave soldering flux material is burned off and results in poor solder quality. More research is needed to improve the flux material for Pb-free wave and selective soldering processes. The maximum operating temperature of the components is around 260 C. A minimum solder pot temperature of 260 C is needed for Pb-free wave soldering processes. Higher solder pot temperatures have been used for thick boards (>0.093 ) and high-end products. In addition, the temperature difference between preheating and wave is higher for Pb-free wave soldering than tin lead wave soldering. Therefore, component suppliers need to pay more attention to the component thermal shock issue during Pb-free wave and selective soldering process. Challenges were identified for two of the three rework processes: PTH rework, and area array rework. For PTH rework, complete hole-fill and copper dissolution mitigation for a Pb-free process are two areas in need of development. The development effort should be focused on process and equipment advancements. Area array rework had several gaps identified as the product moves towards a Pb-free process. The two key technology gaps acknowledged were: 1) preventing adjacent components undergoing a secondary reflow process and, 2) having a workable flux system for a flux only rework process. For both tin-lead and Pb-free rework processes, reducing the temperature delta across the solder joints / package was identified as a showstopper. New rework equipment technology is needed to aid in reducing delta T as well as minimizing temperature impact on adjacent components. The main need in press-fit technology is for a means to test for proper insertion of a pin when two pins are inserted into the same hole. inemi Technology Roadmaps 60 January

63 Figure 9: Press Fit Illustration Figure 9 shows that the bottom pin can be bent and still maintain contact with the barrel during the assembly and testing process. Without a means of being able to accurately identify which one of the pins is bent, this defect can reach the field and then open up. Another issue that will need to be addressed is the need for automatic placement of connectors. As the industry becomes even more cost competitive, this need will become more pronounced in order to improve throughput. One of the first steps in automating the process is to standardize the connector trays between companies for the machine. The ideal automated process involves the following steps: pick, inspect, place, press, and final inspection. The use of optical interconnects will also generate challenges for board assembly materials, methods and equipment. inemi Technology Roadmaps 61 January