Atomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices

Size: px

Start display at page:

Download "Atomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices"

Stephen Stephens
6 years ago
Views:

International Conference on Characterization and Metrology for ULSI Technology March 15-18, 2005 Atomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices Yoshi Senzaki,

1 International Conference on Characterization and Metrology for ULSI Technology March 15-18, 2005 Atomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices Yoshi Senzaki, Kisik Choi, Paul D. Kirsch, Prashant Majhi, Byoung Hun Lee SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline 1. Introduction 2. ALD of High-k Dielectric High-k dielectric ALD processes Electrical properties of MOS devices Scaling the Hf-based dielectric 3. ALD of Metal Gate ALD Metal Nitrides - TiN, HfN, HfSiN, TaN Work function evaluation

3 MOSFET Device Goals for 45 nm node and beyond Application EOT (nm) CET (nm) Jg (A/cm 2 ) High Performance (HP) </= 0.8 </= 1.2 </= 100 Low Standby Power (LSTP) </= 1.6 </= 2.4 </= 2.2x10-3 Density of interface traps (D it ) </= 5x10 10 # / cm 2 ev High frequency (100kHz) CV hysteresis </= 10 mv V t ± 0.2V of control SiO 2 with same EOT V t stability ± 10mV of unstressed film Mobility >/= 90% of SiO 2 at EOT 0.8nm Defect Density </= 0.14 defects / cm 2 Thermal stability (physical and electrical) at 1000ºC, 5 sec Thickness uniformity (3 sigma) </= 4% Reliability comparable to SiO 2

4 Factors That Influence Metal Electrode Properties Poly Why: Ease of integration Effect: Stress?, Reaction with electrode if no barrier layer? Why: prevent interaction between Electrode and Poly; Effect: Stress?, Reaction with metal electrode? Metal diffusion through electrode grain boundary and pile up at TIL? Overlay effect if electrode very thin? Barrier/Cap Layer Metal Electrode Top Interface Layer (TIL) Dielectric Why: Control WF, EOT scaling (no poly depln) Effect: main contributor to WF, Crystallinity, grain orientation, thickness effect? Overlay effect if TIL (intentional) very thin? Why: Unintentional (due to reaction of metal with dielectric); Intentional (dual metal integration and EWF control via overlay effect) Effect: controls EWF if TIL forms Bottom Interface Layer (BIL) Why: High-k for scaling Effect: reaction with metal to form TIL + Fermi level pinning, fixed charges shift Vfb shift.

5 Introduction: Why Metal ALD? Why metal electrodes? poly electrode depletion limits device scaling poly electrode can interact with high-k materials Why ALD metal electrodes? Excellent thin film thickness uniformity control Excellent composition control Little damage to gate oxide (compared to PVD) Low temperature deposition with low impurity Conformality at nanoscale structures and potentially 3-D devices Multiple potential applications for ALD metal films Metal gate electrode: TaN, TiN, W, Ru.. Cu diffusion barrier/adhesion promoter: TaN, Ta, TaSiN, TiN, WN.. Cu seed layer: Cu Plug for via hole: W, WN x Barrier: TiN, Ti

6 Gate ELECTRODE Specifications Application EWF (n metal) EWF (p metal) CMOS on bulk Si 4.1 +/ /-0.05 CMOS on FDSOI, FINFET 4.4 +/ /-0.05 Gate stack subjected to S/D dopant activation anneal (1000 C, 5 sec) V t ± 0.1 V of control SiO 2 with same EOT V t stability ± 10mV of unstressed film Mobility >/= 95% of SiO 2 Density of interface traps (D it ) </= 5x10 10 # / cm 2 ev High frequency (100kHz) CV hysteresis </= 10 mv Reliability comparable to Poly/SiO 2 Defect Density </= 0.14 defects / cm 2 Thickness uniformity (3 sigma) </= 4%

7 ALD Processes: Metal-Organic Liquid Precursors for HfO 2 Hf-t-Butoxide Hf(C 4 H 9 O) 4 Dep. Rate: 0.24Å/cycle TEMAHf (Tetrakisethylmethyl amino hafnium) Hf(NMeEt) 4 H 9 C 4 O H 9 C 4 O Hf OC 4 H 9 OC 4 H 9 Dep. Rate: 0.89Å/cycle Less impurities in the HfO 2 films Lower leakage current of HfO 2 --> Precursor of choice N Hf N ECS Proceedings, 2003 N N

8 Precursor Co-injection ALD Concept for HfSiOx A+B(g) Introduction of A+B(g) onto the substrate surface Introduction of A(g) + B(g) onto the substrate surface Formation of an A+B(s) monolayer surface A+B(S) Formation of an A+B(s) monolayer surface Introduction of C(g) onto A+B(s) surface C(g) Introduction of C(g) onto A+B(s) surface Formation of C(s) monolayer surface C(S) Formation of C(s) monolayer surface 8

9 HfSiOx ALD Precursors N N N N Hf Si Hf N N N N TEMAHf TEMASi Chemical compatibility -> suppresses gas phase reaction J. Vac. Sci. Technol. (A), vol. 22, p.1175 (2004).

10 HfSiO x ALD Coinjection vs Nano-laminate Precursor coinjection Hf/Si pulse/purge + Oxidizer pulse/purge Nano-laminate HfSiO x Si Hf pulse/purge + Ox pulse/purge + Si pulse/purge + Ox pulse/purge HfO 2 SiO 2 HfO 2 SiO 2 HfO 2 Si high temperature anneal HfSiO x Si

11 Leakage Current (J g ) Reduction of Hf(Si)O J g (V fb -1) [A/cm 2 ] HfO 2 HfSiO SiO 2 /PolySi EOT (Å) J g reduction: x vs. SiO 2 /PloySi

12 Mobility Progress with HfO 2 and HfSiO Mobility - 1MV/cm (cm 2 /V-s) Univ SiO 2 HfO2 HfSiO 140 HfO2 "B" 120 HfSiO "B" HfSiO "A" 100 HfO2 "A" SiON ref [4] 80 SiO2 ref EOT (Å) HfO 2 and HfSiO show mobility results similar to nitrided oxide Significant improvement relative to historical dataset [4] P.A. Kraus et al., Semiconductor Fabtech v. 23, p. 73 (2004).

13 Mobility Progress at Peak and High Field * P.A. Kraus et al., Semiconductor Fabtech v. 23, p. 73 (2004). Mobility (cm 2 /V-s) Univ SiO2 HfSiO HfO2 Univ SiO2 SiON ref [4] Electric Field (MV/cm) SiON * HfSiO EOT (nm) µ pk (cm 2 /V-s) µ(1mv/cm) (cm 2 /V-s) J g (A/cm 2 ) (V t +1V) or (V fb -1V) HfSiO performs similarly to SiON but with scaling benefit

14 N Content in Interfacial SiON Layer Mobility (cm 2 /V-s) Univ SiO2 1 HF Last+HfO2 Chem Ox+HfO2 NH3+HfO Electric Field (MV/cm) 1. Mobility: NH 3 N in interfacial layer degrades mobility. 2. EELS: High N content near Si substrate (inversion layer) % (peak µ) -15% (1MV/cm µ). EELS Intensity (a.u.) (b) Si SiON HfO Hi-k Position (nm) Electrode e- PolySi 3 Hf N O Si 2

$Last\HfO 2 \TiN O 3 \HfO 2 \TiN NH 3 \HfO 2 \TiN 5 nm$ 5 nm 10 nm After processing (1000C-5s), SiO(N) T phy

[rather than physical thickness screening effect]

15 Similar Physical Thickness in SiO x and SiON HF Last\HfO 2 \TiN O 3 \HfO 2 \TiN NH 3 \HfO 2 \TiN 5 nm 5 nm 10 nm After processing (1000C-5s), SiO(N) T phy is similar (TEM is ±2Å) Suggests fixed charge from N [rather than physical thickness screening effect] degrades mobility Consistent with peak / high field mobility results

Scaling the Hf-based dielectric Blanket a) ox pulse only

Last - Precursor A HF Last - Precursor B Bulk HfO2 9.

c-si XRR Density (g/cc) 9 8 7 6 5 Hf Coverage (RBS) Hf/cm

16 Scaling the Hf-based dielectric Blanket a) ox pulse only a-si Chem Ox - Precursor A NH3 - Precursor A HF Last - Precursor A HF Last - Precursor B Bulk HfO g/cc b) 5 ALD cyc c) 15 ALD cyc c-si a-si c-si a-si c-si XRR Density (g/cc) Hf Coverage (RBS) Hf/cm 2 1.4x x x x x x x ALD Cycle Number 2 nm d) 23 ALD cyc Scaling to below 2.0 nm feasible

17 HfSiO Nitridation Improves V t Stability V TH (mv) No N 8% N % N % N % N 2 Stress Condition Vg=V TH +1.2V improves Time (sec.) 20% Silicate

TiN Film Characterization Surface oxide that drops to 5-8% in the bulk RMS roughness ~0.8 nm Ti/N ~1.0-1.

19 TiN Film Characterization Surface oxide that drops to 5-8% in the bulk RMS roughness ~0.8 nm Ti/N ~ depending on technique Aproximate Atomic Concentration 100% 80% 60% 40% 20% 0% SiO2 Sputter Equivalents Ti N Si C O F Yield Channel

20 ALD-TiN MOSCAP Data 2.5E-06 ALD TiN on ALD HfOx (4,6,8,10 nm) CAPACITANCE ( f ) 2.0E E E E-07 EOT = 1.5 nm Vfb = V EOT = 2.2 nm Vfb = V EOT = 2.9 nm Vfb = V EOT = 3.6 nm Vfb = V V fb = Φ ms -Q f /ε ox EOT V fb : flat band voltage Φ ms : gate work function Q f : interface charge density 0.0E VOLTAGE (v) Electrode Gate Dielectric Φ ms ' [V] Nf [chg/cm 2 ] Work Function Φ m [ev] 100 A ALD-TiN ISSG x10e A ALD-TiN ALD-HfOx x10e A ALD-TiN MOCVD-HfOx x10e Marginal dependence of Work function and N f on the gate dielectric material

21 Transistor Characteristics of ALD TiN on ALD HfSiOx (40 A) C ap acitan ce [f] 8.0E E E E E E E E E+00 C-V (n/pmos) of ALD TiN on HfSiOx (40 A) nmos pmos Voltage [V] Current [A] 1.00E E E E E E E E E E E-13 Id-Vg (n/pmos) of ALD TiN on HfSiOx (40 A) nfet pfet Voltage [mod Vg] Ig-Vg (n/pmos) of ALD TiN on HfSiOx (40 A) DIE 3,1 DIE 5,1 DIE 6,2 DIE 4,2 DIE 2,2 DIE 1,3 DIE 3,3 DIE 5,3 DIE 7,3 DIE 8,4 DIE 6,4 DIE 4,4 DIE 2,4 DIE 1,5 DIE 3,5 DIE 5,5 DIE 7,5 DIE 8,6 DIE 6,6 DIE 4,6 DIE 2,6 DIE 3,7 DIE 5,7 DIE 7,7 DIE 6,8 DIE 4,8 DIE 3,1 DIE 5,1 DIE 6,2 EOT = 2.0 nm V fb (n) = V V fb (p) = 0.45 V Jg (n) ([Vfb-1]) = 5 e-3 [A/cm 2 ] 1.0E E E E E E E E E E E E-14 Current [ A ] Voltage [V]

22 Demonstration of High Performance with High-k and TiN (Mid-Gap) Gate NMOS with 30A HfSiO+ALD TiN PMOS with 30A HfSiO+ALD TiN nA/um nA/um Ioff (na/um) Ioff (na/um) Ion (ua/um) Ion (ua/um) 85 nm baseline exhibits high performance Mobility (e/h) NOT a showstopper NEED band-edge metals

23 HfN Film Analysis < 5% Carbon in the film High concentration of surface oxide that quickly drops to ~2% Atomic Concentration (%) As-dep Oxygen oxidized Hf Si Nitrogen Hf Carbon Sputter Depth (Å) Yield Channel

24 C-V and I-V curves of HfN/HfSiO/SiO 2 stack 8.0x Capacitance (F) 7.0x x x x x x x10-11 Frequency: 100 khz CET: 2.27 nm RMS Error: 0.8% Voltage (V) Measured Model Current density (A/cm 2 ) CET=2.27 nm J@V fb -1V= 4E-3 A/cm Voltage (-V) HfN 15nm /HfSiOx 3nm/SiO 2 2nm dot size: 5e -5 cm 2

25 C-V and I-V curves of HfSiN/HfSiO/SiO 2 8.0x Capacitance (F) 7.0x x x x x x x10-11 Frequency: 100 khz CET: 2.17 nm RMS error: 0.8% Measured Model Voltage (V) Current density (A/cm 2 ) CET:2.17 nm J@V fb -1V=2.75E-5 A/cm Voltage (-V) HfSiN 15nm /HfSiOx 3nm/SiO 2 2nm dot size: 5e -5 cm 2

26 Work Function of ALD Metal Nitrides Flat Band Voltage, Vfb [V] HfN 4.44eV Nf W.F -1.42E+11 /cm ev 4.48eV Nf W.F HfSiN 4.48eV 8.69E /cm2 ev TiN 4.45eV N f 1.32E11/cm 2 W.F ev EOT [nm]

27 XRD and XRR of ALD TaN x Intensity (Counts) Si TaNx on 1KA SiO2/Si TaNx on native oxide Refelectivity theta Theta (degrees) -XRD confirmed amorphous nature of films (even after annealing up to 900 C) - XRR density ~ 8g/cc; half of bulk value

ALD TaN Deposition Temperature Effect 1E+06 1E+05 Deposition at 200 C Si Deposition temperature: 200 C Counts/Sec 1E+04 1E+03 TaN (75C/200C on bare Si) 1Torr, 150sccm NH3, 700sccm Ar line at :

28 ALD TaN Deposition Temperature Effect 1E+06 1E+05 Deposition at 200 C Si Deposition temperature: 200 C Counts/Sec 1E+04 1E+03 TaN (75C/200C on bare Si) 1Torr, 150sccm NH3, 700sccm Ar line at : cycles: 80 optprobe: 88A TEM: no much of a film 29Si 29Si+14N Ta+C Ta+N Ta+O 1E+02 1E+01 1E Depth (nm) 5 nm Si Counts/Sec 1E+06 1E+05 1E+04 1E+03 1E+02 1E+01 TaN (75C/350C on bare Si) 1Torr, 150sccm NH3, 700sccm Ar line at : Optiprobe : 139A Ta+C Ta+O Si Deposition at 350 C Ta+N Si+N 29Si 29Si+14N Ta+C Ta+N Ta+O - Dep rate is strongly dependent on temp. (~1.5 Å/cycle at 350 C and ~ 0.25 Å/cycle at 200 C) - TaN film deposited at 200 C resulted in discontinuous film - SIMS data with high silicon count at the surface confirms TEM data 1E Depth (nm)

29 350 C ALD TaN Properties of ALD-TaN Linear growth of TaN Film on bare Si at 350 C Film Thickness (A) R 2 = # ALD Cycles AES data: carbon content in TaN film is high Atomic Concentration (%) O C N Sputter Depth (Å ) Si Ta - Linear increase of thickness with # of ALD cycles. Dep rate > 0.1nm/cycle - The TaN film has a surface oxide and ~10% O in the bulk - The N : Ta in the bulk is nearly 1 : 1 - C present at a similar % ~ 1:1:1 C:N:Ta

30 METAL ELECTRODE: Thickness Effect Effective work function(ev) TiN/SiO 2 TiN/HfSiO x TiN/HfO 2 n+ poly/dielectric No TiN 0 ALD TiN TiN islands TiN ALD cycles Effective work funciton (ev) ALD TaN HfSiOTiNcap HfO2TiNcap TaN thickness (A) Work Function of ALD TiN saturates around 200 cycles at ~4.7 ev Work Function of ALD TaN saturates < 50 Å at ~4.8 ev

31 High-k (HfSiOx) Surface Treatment Effects on Work Function of Metal Electrodes TiN 100A TaN 100A HfN 100A W o r k f u n c i t o n ( e V ) No PDA NH3 PDA NH3 PDA + HF dip PDA method Work function Oxide charge NH3 PDA + HCl dip N2 PDA Fixed charge (1E 10/cm 2) W o r k f u n c i t o n ( e V ) Work function Oxide charge No PDA NH3 PDA NH3 PDA + HFNH3 PDA + HCl dip dip PDA method N2 PDA F i x e d c h a r g e ( 1 E 1 0 / c m 2 ) W o r k f u n c i t o n ( e V ) No PDA NH3 PDA NH3 PDA + HFNH3 PDA + HCl dip dip PDA method Work function Oxide charge N2 PDA F i x e d c h a r g e ( 1 E 1 0 / c m 2 ) HCl treatment helps reduce TiN Work Function by more than 0.2eV TaN is relatively independent on dielectric modification

32 Thermal Stability of Ru on HfSiOx and SiO 2 HRTEM cross section analysis

33 C-V and I-V curves for Ru/HfO 2 vs Ru/HfSiOx R u / H fs io x (2 0 % S io 2 ) R u / H fo 2 C (pf) Jg (A/cm ) E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E V g R u / H fo 2 R u / H fs io x V g

34 Conclusions 1) HfO 2 and Hf x Si 1-x O 2 ALD processes scale physical thickness below ~2nm utilizing metal-amide precursors and ozone. 2) ALD chemistry proceeds similarly on multiple surface preparations including HF last without growth incubation. 3) Promising high field mobility more than 85% of universal SiO 2 mobility has been achieved at EOT ~1nm with x Jg reduction.

35 Conclusions (cont d) 5) ALD metal gate electrodes such as TiN, HfN, HfSiN deposited on HfO 2 and HfSiOx showed mid gap characteristics. 6) Thickness dependency of Work Function of metal electrode was observed for ALD TiN. 7) PVD Ru is thermally more stable on HfO 2 as compared with SiO 2 and HfSiO x.

X-Ray Reflectivity Study of Hafnium Silicate Thin Films Prepared by Thermal Chemical Vapor Deposition

X-Ray Reflectivity Study of Hafnium Silicate Thin Films Prepared by Thermal Chemical Vapor Deposition Hideyuki YAMAZAKI, Advanced LSI Technology Laboratory, Toshiba Corporation hideyuki.yamazaki@toshiba.co.jp