Enabling Tool and Process Technologies for Advanced Devices

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1 Enabling Tool and Process Technologies for Advanced Devices June 26 th, 2012 Tokyo Gert Leusink TEL Technology Center America, LLP 1

2 Outline Emerging Technologies and SPE needs Process and Integration Development Enabling Tools Summary and Outlook 2

3 Emerging Technologies driving SPE needs Emerging Technologies Logic FEOL - FinFET/Tri-Gate, nanowire - Ge, III V, CNT, Graphene MOL - Self Aligned Contacts - Low-k Spacers BEOL - Liner for Cu Fill for <14nm - Through Si Via - CNT interconnect? Memories ST-RAM, ReRAM, MIM, Planar 3D Process Equipment Needs: Deposition and Treatments Etch Precise control of conformality, composition, thickness, structure, particles High-k, Capping Layers, Gate Metals, Barriers, Liners, Fill Thermal budgets: RMG, ULK, TSV Single wafer vs batch / Cluster vs Air Break Precise control ion and electron energies Isotropic vs anisotropic, Selectivity Cleans Precise control, surface, selectivity Single wafer vs Batch / Cluster vs Air Break Flexibility, extendability, 450mm scaleability Low Cost 3

4 Process and Integration Development Partnership needed to: 1) Share Cost and Risk (shared tools, resource, facilities) 2) Reduce Development Time Equipment Partnership Materials Device Oscilowski Semicon West

Partnership Model 14/11nm Materials Development JDP s SEMATECH CNSE IDM s Metrology Materials Beta tool design & delivery Material & Process Development Integration Production tool & CIP

5 Partnership Model 14/11nm Materials Development JDP s SEMATECH CNSE IDM s Metrology Materials Beta tool design & delivery Material & Process Development Integration Production tool & CIP Demo JDP Agreement TEL Location Albany Japan JDP s for early engagement in 14 and 11nm research Fast cycle time: 2-4 weeks from chemical install to M1 data 5 Oscilowski Semicon West 2011

6 Process and Integration Development High-k and Capping Layers integration Metal Gate integration Back-end-metal Liner integration 6

7 High-k and Metal Gate Process Integration Development Clustered development capability for Early Identification of clustering needs High-k SPA-N UV-O interfacial oxide UVRF LPA UV assisted SiO 2 High κ deposition MOCVD and ALD Plasma nitridation (SPA) Post Nitridation Anneal (LPA) High-k nitridation anneal Metal Gate deposition ALD/CVD TiN, TiAlN, Ti, TaN Metal 1 Metal 2 7 Wajda et al, ECS Fall 2006

XPS thickness [nm] UV-O Interfacial Oxide Layer UV lamp intensity and time dependence Herman s model 4th layer 3rd - layer 2nd layer 1st layer silicon oxygen 0.18nm 0.18nm 0.18nm 0.23nm 1.2 1 0.8 0.

8 XPS thickness [nm] UV-O Interfacial Oxide Layer UV lamp intensity and time dependence Herman s model 4th layer 3rd - layer 2nd layer 1st layer silicon oxygen 0.18nm 0.18nm 0.18nm 0.23nm UV=0% UV=5% UV=20% UV=100% 0.2 DHF Last (XPS 4A ) oxidation time [sec] 6A Temp:450C, Press:~0.03torr, O2:150sccm UVRF process enables further scaling of High-k stack Wajda et al, ECS Fall

9 Intensity[-] Vacuum vs Air Transfer SPA-N PNA (XPS) Initial(w/o anneal) Transfer in vacuum Transfer in air 3min Transfer in air 30min N1s spectrum Transfer in vacuum to anneal Transfer in air before anneal Transfer in air 60min Main peak After SPA-N Sub peak After anneal Binding Energy[eV] Vacuum transfer results in higher N1S peak 9 Wajda et al, ECS Fall 2006

10 J g (A/cm 2 )@ Vg=V fb -1V Cg [ F/cm 2 ] Optimizing Si, N and Anneal for EOT control in HfSiON gate dielectric Cluster w/lpa O2 partial pressure split Pa 0.2Pa TaSiN / HfSiON / SiO 2 stack (69pts) 2Pa EOT (nm) 15%N ( :23%N) 3.5E E E E E E E E+00 Optimized stack achieved 8A EOT LPA 1000 EOT 0.82nm 0.92nm EOT 1.1nm 0Pa 0.2Pa 2Pa Vg [ V ] 10 Wajda et al, ECS Fall 2006

Capacitance Density ( F/cm 2 ) ASFD High-k Capping Layers: Position Dependence Capacitance Density ( F/cm 2 ) Capacitance Density ( F/cm 2 ) 3.0 3.0 3.0 2.5 2.5 2.5 2.0 2.0 2.0 1.5 1.

11 Capacitance Density ( F/cm 2 ) ASFD High-k Capping Layers: Position Dependence Capacitance Density ( F/cm 2 ) Capacitance Density ( F/cm 2 ) Bottom Cap Reference 0.5 Barium Lanthanum Yttrium Gate Voltage (V) 1.0 Middle Cap Reference 0.5 Barium Lanthanum Yttrium Gate Voltage (V) 1.0 Top Cap Reference 0.5 Barium Lanthanum Yttrium Gate Voltage (V) Most shift obtained with closer proximity of cap layer to IL bottom cap > middle cap > top cap Irrespective of position in the gate stack the higher group electronegative cap layers provides the most shift Tinv scaling is adversely impacted in bottom cap samples 11 Jagannathan et al, ECS Spring 2009

12 Correlation of Band Alignments (by XPS) with Flatband Voltage (unannealed samples) V fb and Si band bending vs. cycles of bottom La 2 O 3 and bottom HfO 2 Band Alignments measured by XPS on identical sister wafers (with 30Å TiN) are consistent with Vfb shifts observed in the MOSCAPs M. Di et al. App. Phys. Lett. 2010, J. App. Phys Clark et al, ALD

13 Gate Metal: EOT reduction effect by Al addition into TiN HfO 2 Gate (First) HfSiON (Gate First) ΔEOT 2.2Å ΔEOT 0.5A 0.9Å EOT reduction depends on High-K. 13 Nakamura et al ECS Fall 2011

14 Gate Metal: EOT reduction effect by Al addition into TiN HfO 2 (Gate First) HfO 2 (Gate-last) ΔEOT 2.2Å ΔEOT 0.5Å The EOT reduction depends on integration: Gate-last flow has less EOT reduction, due to lower thermal budget after metal gate. 14 Nakamura et al ECS Fall 2011

15 Vfb [V] Gate Metal: Vfb shift difference between HfO 2 and HfSiON -0.2 Gate-First HfO 2 HfSiON ΔVfb 130mV ΔVfb 25mV TiAlN TiAlN Positive TiN HfSiON shift Positive shift TiN HfO 2 The Vfb shift direction is the same. The shift is ascribed to Al induced dipole at HK/IL HfO 2 showed larger Vfb shift than HfSiON. 15 Nakamura et al ECS Fall 2011

Vfb [V] Gate Metal: Vfb shift difference between Gate-first vs Gate-last. -0.2 Gate-first on HfO 2 Gate-last -0.3-0.4 ΔV fb 130mV TiAlN TiN Negative shift by V + o TiAlN ΔV fb 100mV -0.5-0.

16 Vfb [V] Gate Metal: Vfb shift difference between Gate-first vs Gate-last Gate-first on HfO 2 Gate-last ΔV fb 130mV TiAlN TiN Negative shift by V + o TiAlN ΔV fb 100mV TiN Positive shift by Al-dipole ΔG 0 Al > ΔG 0 Ti Al addition into Ti could make more V o+. The V fb shift direction depends on integration Negative V fb shift for Gate Last is ascribed to positively charged V o 16 Nakamura et al ECS Fall 2011

Al Hf less Al Hf Hf least Al Gate First Gate Last HfSiON has less Al diffusion than

17 The reason for the Vfb shift difference ~Al diffusion into the IL~ Backside SIMS HfO 2 /TiAlN HfSiON/TiAlN HfO 2 /TiAlN/TiN SiO2 HfO2 TiAlN TiN O Ti O Ti Ti O more Al Hf less Al Hf Hf least Al Gate First Gate Last HfSiON has less Al diffusion than HfO 2 Gate Last has less Al diffusion than Gate First 17 Nakamura et al ECS Fall 2011

18 Jg (A/cm 2 ) 1.E+00 Scaling ASFD (ALD) HfO 2 : Advantage of DADA 1.E-01 No Anneal 1.E-02 1.E-03 DADA HfO 2 HfO 2 + PDA Densification from Anneal 1.E EOT (nm) Lower C, More SiO/HfO intermixing, larger grain size/more texturing from DADA DADA process shows improved scaling versus as deposited films as well as films undergoing post-deposition anneal 18 Clark et al, ECS Spring 2011

19 ASFD-HfO 2 Anneal Time Effect of DADA Increasing DADA anneal time appears to increase crystallinity and ordering in the film. As Dep 40 cycle 2 step DADA with 800 o C Anneals SiON interface 10 Seconds 20 Seconds 40 Seconds 19 Clark et al, ECS Spring 2011

20 Adding Zr for Higher-k DADA: Fiber Plots Vs. Zr/(Zr+Hf)% Fiber plots (at phi=45 o ) of ALD Hf x Zr 1-x O 2 films as a function of Zr % for a) T(111) or d=2.95å and b) M(-111) or 3.15Å peak. 20 Tapily et al, ECS Spring 2012

21 Barrier, Liner and Seed Process Integration Development Clustered development capability for Early Identification of clustering needs CVD-Ru Cu-Seed Pre-Clean Ion or radical assisted Barrier Deposition Ionized PVD Ru Deposition CVD Cu Seed / Fill Ionized PVD PVD-Barrier Pre-Clean Cu-Fill 21

22 Metal cap CVD Ru provides selective deposition. EM lifetime enhancement on Ru capped Cu wiring. CVD Ru metal cap 2.7nm Yang, et.al. IITC Ishizaka et al, AMC 2011

23 Contact application CVD Ru enables void free gap-fill for contact hole. Cu contact resistance is about 1/3 of W contact. via160nm 1650nm (A/R=10) Seo, et.al. AMC Ishizaka et al, AMC 2011

24 TSV application Successful Direct Plate approach for low CoC Ta barrier / Ru 3nm / Cu 50nm Ta barrier / Ru 3nm 5 X 50 m via Joint work with SEMATECH 24 Ishizaka et al, AMC 2011

18-20nm width, AR 10 Cu Filling Performance

25 18-20nm width, AR 10 Cu Filling Performance with Ru liner Observed bottom up deposition from the beginning of deposition. DD structures were filled as well with Cu dry-fill process. ILD (k=2.4) DD filled with DryFill M1 (plated Cu) 25 Ishizaka et al, AMC 2011

26 Capacitance [a.u.] Electrical Performance Cu DryFill with Ru liner RC product with Cu dry-fill is lower, especially at narrower structures 8 7 Cu dry-fill on CVD Ru ~5% Conventional scheme (PVD barrier/seed & ECP) ~10% A B W C Pitch D nm width 60nm width Resistance [a.u.] 26 Ishizaka et al, AMC 2011

27 Enabling Tools Cleaning Processing (COR) Deposition (CVD-Ru) Plasma Processing (SPA/RLSA) Ion beam processing (GCIB) 27

28 Certas TM COR (Chemical Oxide Removal) First step is a non-plasma reaction between a mixture of HF and NH 3 gases and the SiO 2 which forms a solid reaction product on the surface Second step is evaporation of the solid reaction product by heating the wafer. COR Module Surface Micro Etch NH 3 /HF adsorption onto wafer surface Wafer temp. 20~80 NH 3 HF Post Heating Module Heat up to 100~200 Evaporate etch by-product from wafer surface Post mix Wafer NH3 NH3 HF HF NH3 HF (NH4)2SiF6 N2 SiF4 H2O SiF4 HF NH3 HF N2 SiF4 NH3 Wafer Water Heater 28 Saito et al, SSPV, (2009), pp

29 Certas TM COR (Chemical Oxide Removal) 29 Saito et al, SSPV, (2009), pp

30 CVD Ru Solid precursor & thermal CVD Precursor Delivery System VLV Solid precursor delivery system UHV/Clean chamber Very effective precursor trap Ampoule High purity film High speed deposition Excellent step coverage Long maintenance cycle Precursor recycle / low CoC C,O<0.1at.% 30wph/ch. Temp. controlled delivery line and Chamber wall Vacuum Stage Heater Ishizaka et al, AMC

31 Next Generation Plasma Source Slot Plane Antenna (SPA) or RLSA (Radial Line Slot Antenna): High Density (~10 12 /cm 3 ) Low Electron Temp. ( 0.7 ~ 1.5eV) Wide Process Window (7~1000Pa) Optional bias to accelerate ions 31 Tian et al, J. Vac. Sci. Technol. A 24 (4), 2006

32 Electron Density (cm-1) SPA/RLSA Plasma Characteristics Electron Temperature (ev) 1.0E+13 Electron density Electron Temperature Plasma Generation area 1.0E E GHz Cutoff Density ( cm -3 ) Distance from window (mm) Wafer Diffusion area Distance from window (mm) Separated plasma generation and process regions Process region: Diffusion area Low T e (as low as <1 ev) High plasma density n e Low self-bias (Vdc,Vpp) Control of T e (EEDF) control of plasma chemistry in treatments (oxydation, nitridation) and etch Tian et al, J. Vac. Sci. Technol. A 24 (4), 2006 Wafer 32

Features of RLSA Plasma Etch An ideal source has a

population while maintaining a constantly low bulk T e

ionization from dissociation a sufficient n e can lead to a

soft-etch No change in Si recess by extending OE No aspect

33 Features of RLSA Plasma Etch An ideal source has a sufficient ionization population with a reduced dissociation population while maintaining a constantly low bulk T e Generic RF (ICP and CCP) cannot energetically decouple ionization from dissociation a sufficient n e can lead to a higher T e hard to control the plasma chemistry, selectivity and damage. RLSA plasma features enable highly selective and anisotropic soft-etch No change in Si recess by extending OE No aspect ratio dependent etching due to low re-dissociation of by-products due to low bulk T e. Mori et al. in AVS 55 th, PS-TuM10,

etch mechanism Precision LSP trimming of

layer APC control Angstrom-scale uniformity

Production-proven precision LSP (location

34 Yield Enabling Gas Cluster Ion Beam Technology Unique surface modification and etch mechanism Precision LSP trimming of nonuniformity thickness/depth for critical layer APC control Angstrom-scale uniformity enabled. Production-proven precision LSP (location specific processing) thickness control. Used in 40-50% WW FBAR/SAW RF filter production clear yield/roi benefit. Scaling driving new critical needs for precision integrated thickness/depth control. 34

35 Summary and Outlook Collaborative model for development and integration of new materials is demonstrated New tool concepts are being introduced to meet the needs of future process technologies for deposition, treatments and etch Future Challenges and Opportunities Meet increasing demands for extendability, flexibility and cost 450mm transitioning 35

36 Acknowledgements IBM SEMATECH CNSE TTCA, TELAT/LPDC Yamanashi 36

37 CONFIDENTIA L Thank You! 37

Integrated Process Technology Development for the sub 7nm Era

Integrated Process Technology Development for the sub 7nm Era July 12, 2017 Alex Oscilowski President TEL Technology Center, America, LLC. TEL s Global R&D Operations Korea U.S. imec (Belgium) TEL Technology