A novel test method for robustness assessment of very small, functional ultra-thin chips embedded in flexible foils

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1 A novel test method for robustness assessment of very small, functional ultra-thin chips embedded in flexible foils Nagarajan Palavesam 1, 2 Christof Landesberger 1, Christoph Kutter 1, Karlheinz Bock 2 Contact nagarajan.palavesam@emft.fraunhofer.de 1 Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT, Munich, Germany 2 Technische Universität Dresden, Dresden, Germany Abstract We present a new test method developed, by merging Acoustic Emission testing and Ball-Breaker Test, to study the fracture strength of very small, ultra-thin chips integrated in foils. The test method is particularly useful for strength and mechanical reliability assessment of components for wearables, flexible electronics and portable devices. Statistical results from the breaking tests revealed an increase in robustness of the ultra-thin chips of up to 3% due to embedding in foils. 1 Introduction The growing interest in lighter and thinner devices possessing mechanical flexibility and capable of delivering high performance over the recent years is well known. Ultra-thin Silicon Integrated Circuits (Si-ICs) are competent of accomplishing the aforementioned objectives [1]. Ultra-thin Si-ICs are promising candidates to replace their relatively thicker and rigid counterparts in a range of emerging fields such as portable and handheld devices, Wearables, Large Area Electronics, Flexible Lighting, Displays, Robotics, Sensors in addition to established fields such as personal computers, home appliances, Automotive electronics and RFIDs [2-3]. Several international research groups have been reporting about mechanical strength and flexibility of ultra-thin Si chips since many years [4-5]. Nevertheless, majority of the standard test methods followed to measure the breaking strength of the ultra-thin silicon chips require sample sizes different and very often bigger (~15 mm 2 ) than that of the functional Si-ICs (~4 mm 2 ) used in electronics components. Therefore, the results obtained from these tests may not be used as a norm for the reliability estimation of Si-ICs. The quest for miniaturisation has resulted in the evolution of ultra-thin, flexible Si-ICs having sub 5 µm thicknesses. Assembly and processing of these ultra-thin chips is a highly challenging task [6]. One way of handling ultra-thin Si-ICs is by integrating them in flexible foil layers to create chip-in-foil packages. Besides, experimental as well as numerical Finite Element Method analyses have demonstrated an increase in the fracture strength of ultra-thin chips (up to 19%) due to embedding in foils [7-8]. Thus, embedding of ultra-thin chips in foils is advantageous for their handling as well as mechanical reliability. However, precise measurement of fracture strength of ultra- 122

2 thin chips when integrated in foils is complicated and no test standard exists to the best of our knowledge. In order to accurately detect the instance of breaking and to measure the fracture strength of ultra-thin chips and especially ultra-thin chip-in-foil packages, we have developed a new testing scheme by combining Acoustic Emission (AE) testing, which has long been predominantly used for non-destructive testing of materials, with Line-Load Test. The test method has been successfully utilised to measure the fracture strength of very small sized ultra-thin chips and chip-in-foil packages realized from chips having two different thicknesses (12 and 2 µm). The paper is organized as follows. Section 2 briefly describes the existing test methods and the motive for the proposed test method. Basic principle of Acoustic Emission testing is presented in section 3. The developed test setup is explained in section 4. The integration technology used for preparation of functional flexible ultrathin chip foil package technological demonstrators and test samples is narrated in section 5. Results from the uniaxial flexural tests for various cases are plotted in the form of statistical Weibull plots and discussed in section 6. Section 7 is dedicated to the conclusion remarks followed by acknowledgements and references. 2 Motivation for the new test method Fracture strength of Si chips is generally measured using uniaxial and biaxial bending tests. Uniaxial bending tests are more sensitive to the damages occurring during dicing, on the sidewalls and the edges of the chips, while biaxial bending tests are more sensitive to the damages occurring on the surface of the chips during back grinding. Biaxial point load test methods such as the ball-breaker test have been manifested to determine the fracture strength of very small sized samples [9]. However, the ball-breaker test measures the fracture strength of Si chips by analysing mainly the surface quality of the Si chips and neglects the impact of the sidewall quality on the fracture strength of the Si chips. Sidewall quality is more dominant than surface quality in determining the fracture strength of the chips under uniaxial loading conditions and when the chips are prepared using different dicing techniques [1]. Thus, the need for a test method capable of testing the fracture strength of very small sized Si-ICs under uniaxial load conditions is evident. In 25, M.Y. Tsai and C.S. Lin determined the fracture strength of real IC chips (thickness - 15 µm) under uniaxial load conditions using the Line-Load Test method [11]. The Line-load test can also be applied to measure the fracture strength of chip-in-foil packages prepared from chips having thicknesses above ~25 µm. During the test, the load sensor in the universal testing machine follows the force feedback from the chip and plots the force feedback as a function of time. When the chip fracture happens, a slight drop in the force feedback occurs as can be noticed on the load-time curve in Fig. 1 (a). However, for chip-in-foil packages with comparatively thinner chips (chip thickness < 25µm), most of the commonly used load sensors fail to read the drop in the force feedback and consequently show no 123

3 Smart Systems Integration, Munich, Germany, 9 1 March 216 Drop in load curve due to chip fracture Acoustic Emission Signal (db) Load (N) 2 Chip thickness 28 µm Total package thickness 15 µm No change in load curve; Chip fracture not detected by Load sensor Peak amplitude short burst AE signal due to chip fracture Acoustic Emission Signal (db) Load (N) Chip thickness 12 µm 5 Total package thickness 12 µm Time (s) Peak amplitude short burst AE signal due to chip fracture 6 (b) Breaking test of 12 µm ultra-thin chip-in-foil package Load (N) Acoustic Emission Signal (db) 9 3 Acoustic Emission Signal (db) (a) Breaking test of 28 µm ultra-thin chip-in-foil package Load (N) Time (s) Fig. 1. Load-time curve plotted by the load sensor and the corresponding AE signal for ultra-thin chip-in-foil packages having chip thicknesses of (a) 28 µm and (b) 12 µm drop in load-time curve, thus failing to identify the chip fracture (Fig. 1 (b)). Hence, the chip fracture is not detected and the fracture strength of those chip-in-foil packages may not be measured. Therefore, the line-load test requires further modification to measure the fracture strength of chip-in-foil packages prepared from chips thinner than 25 µm. An auxiliary system consisting of an AE sensor can be added to the line-load test setup and by correlating the peak amplitude short burst AE signal with the corresponding load value on the load-time curve, the exact fracture strength can be obtained (Fig. 1 (b)). 3 Principle of Acoustic Emission testing Acoustic Emission is the phenomenon of production of acoustic waves due to the redistribution of the materials caused by irreversible changes in their internal structure. Internal changes, for example plastic deformation, crack formation and propagation, impact, erosion and corrosion, generate transient elastic waves due to the sudden release of elastic energy. The transient elastic wave originated from the internal structural change will propagate in the material structure until it reaches the surface and interact with the surface to create a surface motion. When the AE sensors are mounted on the surface of the material, the surface motion can be acquired by the sensors. AE sensors convert the captured surface motion into electric signal. The electrical signal can be further processed and used to identify the moment of failure occurrence. When the surface area of the material to be tested is too small, sensors can be attached to an adjacent body in physical contact with the sample. AE sensors can be used for monitoring failures occurring once (burst AE) or repeatedly (continuous AE). AE testing has long been used as a quality assurance and failure identification tool in a variety of sectors such as systems involving heavy metal structures, Civil Engineering, Geology, Material Science, industrial process monitoring and machine condition analysis to name a few [12-15]. Inspired by the multitude of applications already utilising AE testing for failure analysis and driven by the urge to test the reliability of ultra-thin flexible electronic components for emerging technologies, we 124

$decided to utilise the concept of AE to examine the mechanical fracture of ultra-thin chip-in-foil packages by combining AE testing with the Line-Load Test.$ The ultra-thin chip-in-foil package sample to be tested was placed on a 7 mm thick soft PDMS (Polydimethylsiloxane) platform.

The ultra-thin chip-in-foil package sample to be tested was placed on a 7 mm thick soft PDMS (Polydimethylsiloxane) platform.

4 decided to utilise the concept of AE to examine the mechanical fracture of ultra-thin chip-in-foil packages by combining AE testing with the Line-Load Test. 4 Test setup description and test procedure The test setup is exhibited in figure 2. The ultra-thin chip-in-foil package sample to be tested was placed on a 7 mm thick soft PDMS (Polydimethylsiloxane) platform. The PDMS platform was made from Sylgard 184 Silicone Elastomer cured at 8 o C for 12 minutes. The test setup used for the experiments was realised by combining the following instruments: (1) Inspektmini from Hegewald & Peschke Meß- und Prüftechnik GmbH (the universal testing machine for applying the load) and (2) ASCO-DAQ2 from Vallen Systeme GmbH (the AE detection system to detect the AE signals originating from the fracture of the samples). Line load was applied onto the ultra-thin chip-in-foil package samples using a 1 mm long stainless steel cylindrical rod having a diameter of 1 mm. The speed of load application was 1 mm/min. Due to the line load exerted on the test sample, the ultrathin chip cracked at its Fracture Strength. The a transient elastic wave emitted from the fracture of the chip was captured by the AE sensor, mounted on the loading frame of the test setup, and was plotted as the peak amplitude short burst AE signal (Fig. 1). The signal was plotted in real-time alongside the force-time curve. The accurate fracture strength of the samples were determined by matching the peak amplitude short burst AE signal with the corresponding load value on the load-time curve. 5 Integration technology for thin chip foil package 5.1 Technology demonstrator The technological concept of thin chip foil package is based on a three layer embedding technology by which the fragile IC is located in the centre of the laminate structure. Figure 3 (a) illustrates the process flow of the technology. By a first processing step, ultra-thin microelectronic devices were bonded onto a film substrate in face-up orientation. Then, the devices were embedded in a planar polymer layer, which was structured by a photolithographic process. After opening of vias above the IC contact pads, a thin film metal deposition and patterning process was carried out (b) Load AE Sensor Loading rod Sample PDMS platform Fig. 2. (a) Schematic of test setup (b) Test setup during a breaking test 125

which resulted in a fan-out routing for the I/O contact pads. Finally, the top wiring layer was covered by a polymer film layer.

Figure 3 (c) shows the flexibility of the fan-out film package of the embedded 25 µm thin ultra-thin microcontroller IC [16]. 5.

[17]. The chips were 3.22 mm long and 2.47 mm wide. Two different chip thicknesses (12 and 2 µm) were used to create the chip foil package test samples.

The key difference between the two methods lies in the method of preparation of grooves on the wafer prior to grinding.

5 which resulted in a fan-out routing for the I/O contact pads. Finally, the top wiring layer was covered by a polymer film layer. The concept resulted in a chip-in-foil package where fragile ICs were embedded in a plane-parallel polymer laminate of an overall thickness between 8 µm and 15 µm (Fig. 3 (b)). Figure 3 (c) shows the flexibility of the fan-out film package of the embedded 25 µm thin ultra-thin microcontroller IC [16]. 5.2 Test samples Ultra-thin Si chips having daisy chain structures prepared using Dicing-by-Thinning technology were used to create the chip foil package test samples reported in this paper [17]. The chips were 3.22 mm long and 2.47 mm wide. Two different chip thicknesses (12 and 2 µm) were used to create the chip foil package test samples. The chips were singulated using two techniques namely, Wafer Sawing and Plasma Dicing. The key difference between the two methods lies in the method of preparation of grooves on the wafer prior to grinding. In wafer sawing, a wafer saw is used to cut the wafer into individual chips whereas in plasma dicing, lithographically patterned grooves are dry etched using SF6 plasma to singulate the chips. Fig. 4 (b) (c) Fig. 3. (a) Process flow for preparation of functional technology demonstrator of flexible Thin Chip Foil Package (b) Concept for face-up thin chip foil package (c) 25 µm thin microcontroller IC technological demonstrator Wafer Sawing Plasma Dicing Fig. 4. Scanning Electron Microscopy image of sidewalls of wafer sawn and plasma diced chips 126

6 confirms that wafer sawn chips are prone to more sidewall damages and edge chipping than plasma diced chips. Polyimide (PI) foil substrates having a thickness of 5 µm were used as the base and encapsulation layers while 12.5 and 25 µm thick PI film substrates were used as cavity film substrates for the chip-in-foil package. The film substrates had no wiring lines as the mechanical reliability testing required no electrical connection as well as functionality of the chips. The chips were pick and placed onto the cavity film substrates which were then laminated with PI encapsulation layer to create the chipin-foil packages. The total package thickness was ranging between 12 and 14 µm (a) Weibull Probability plot for Fracture Strength of ultra-thin chip-in-foil packages Influence of Dicing technique: Plasma dicing vs. Wafer Sawing Fracture probability Chip thickness - 2 um Plasma Diced Wafer Sawn Fracture Strength (N) (b) Weibull Probability plot for Fracture Strength of ultra-thin chips and chip-in-foil packages Impact of chip thickness and embedding Fracture probability Chip type - Wafer Sawn 12 um Bare chips 12 um Embedded chips 2 um Embedded chips Fracture Strength (N) Fig. 5. Weibull probability plots for Fracture Strength of ultra-thin chips and chip-in-foil packages (a) with different dicing techniques and (b) with various chip thicknesses 127

7 6 Results: Fracture Strength Analysis of chip-in-foil packages 6.1 Influence of the dicing technique: Plasma Dicing vs. Wafer Sawing The statistical Weibull probability plots of the breaking tests for Plasma Diced and Wafer Sawn chips integrated in foil packages is depicted in figure 5 (a). The chip thickness for both the chip types was 2 µm and the package thickness was 14 µm. It can be noticed that the Wafer Sawn chip-in-foil packages (Mean fracture strength N) have 1% lower fracture strength than the Plasma Diced Chip foil packages (Mean fracture strength N). The lower fracture strength of wafer sawn chipin-foil packages resulted from the relatively more sidewall damages on the wafer sawn chips than plasma diced chips. 6.2 Impact of chip thickness: 12 µm vs. 2 µm Figure 5 (b) displays the Weibull probability plot for chip-in-foil packages having chips of two different chip thicknesses, 12 and 2 µm diced using a wafer saw. Interestingly, thinner 12 µm chips possessed higher fracture strength than 2 µm chips (Mean fracture strength: 12 µm N; 2 µm N). The smoother edges with reduced sidewall damages of 12 µm chips caused by their longer Chemical Mechanical Polishing duration (about 1.5 times longer than 2 µm chips) helped increase their fracture strength. 6.3 Effect of embedding: 12 µm bare chips vs. chip-in-foil packages To briefly exemplify the advantage of embedding of ultra-thin chips, uniaxial breaking tests were conducted for 12 µm bare chips and chip-in-foil packages. The mean fracture strength of bare chips and chip foil packages were 4.45 N and N respectively. The statistical results (Fig. 5 (b)) indicated that the mean fracture strength of the chips improved by up to 3% when integrated in foils due to the stress compensation provided by the foils. 7 Conclusion The reported test method, devised by combining Acoustic Emission testing and Ball Breaker test, is simple, easy to use and is efficient in precise mechanical reliability evaluation of ultra-thin components widely used in emerging as well as traditional electronic components manufacturing. The method has been successfully implemented to measure the fracture strength of very small sized ultra-thin chips, having very low thicknesses (12 and 2 µm), integrated in flexible foils. Statistical results from various breaking tests to analyse the effect of embedding, the influence of the dicing technique and the impact of chip thickness on the breaking strength of chips integrated in chip foil packages were presented in the form of Weibull plots and discussed along with the integration technology of the ultra-thin chip foil package. The drastic increase in fracture strength of ultra-thin chips resulting from the embedding in foils was also demonstrated. 128

8 Acknowledgements This work was funded by the Bavarian Government under contract no. VI/3-3622/452/3 and the European Commission under the grant agreement PITN-GA CONTEST. References [1] Burghartz, Joachim. Ultra-thin chip technology and applications. Springer Science & Business Media, 21. [2] Bock, Karlheinz, et al. "Multifunctional system integration in flexible substrates." Electronic Components and Technology Conference (ECTC), 214 IEEE 64th. IEEE, 214. [3] Mahsereci, Yigit et al. "An Ultra-Thin Flexible CMOS Stress Sensor Demonstrated on an Adaptive Robotic Gripper." Solid-State Circuits, IEEE Journal of, vol.51, no.1, pp , Jan. 216 [4] Schönfelder, Stephan, et al. "Investigations of strength properties of ultra-thin silicon." Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 25. EuroSimE 25. Proceedings of the 6th International Conference on. IEEE, 25. [5] Van Den Ende, Daan A., et al. "Mechanical and electrical properties of ultra-thin chips and flexible electronics assemblies during bending." Microelectronics Reliability (214): [6] Feil, Michael, et al. "The challenge of ultra thin chip assembly." Electronic Components and Technology Conference, 24. Proceedings. 54th. Vol. 1. IEEE, 24. [7] Palavesam, Nagarajan et al. "Investigations of the fracture strength of thin silicon dies embedded in flexible foil substrates." Design and Technology in Electronic Packaging (SIITME), 214 IEEE 2th International Symposium for. IEEE, 214. [8] Palavesam, Nagarajan et al. "Finite element analysis of uniaxial bending of ultra-thin silicon dies embedded in flexible foil substrates." Ph. D. Research in Microelectronics and Electronics (PRIME), th Conference on. IEEE, 215. [9] Guojun, Hu et al. "Characterization of silicon die strength with application to die crack analysis." Electronic Manufacturing Technology Symposium (IEMT), 28 33rd IEEE/CPMT International. IEEE, 28. [1] Schoenfelder, Stephan, et al. "Investigations of the influence of dicing techniques on the strength properties of thin silicon." Microelectronics reliability 47.2 (27): [11] Tsai, M. Y., and C. H. Chen. "Evaluation of test methods for silicon die strength." Microelectronics Reliability 48.6 (28): [12] Dunegan, H., and D. Harris. "Acoustic emission-a new nondestructive testing tool." Ultrasonics 7.3 (1969): [13] Lockner, D. "The role of acoustic emission in the study of rock fracture." International Journal of Rock Mechanics and Mining Sciences & Geomechanics Abstracts. Vol. 3. No. 7. Pergamon, [14] Barré, Sébastien et al. "On the use of acoustic emission to investigate damage mechanisms in glass-fibre-reinforced polypropylene." Composites Science and Technology 52.3 (1994): [15] Li, Xiaoli. "A brief review: acoustic emission method for tool wear monitoring during turning." International Journal of Machine Tools and Manufacture 42.2 (22): [16] Landesberger, Christof et al. "Novel processing scheme for embedding and interconnection of ultra-thin IC devices in flexible chip foil packages and recurrent bending reliability analysis." Accepted for publication at 216 International Conference on Electronics Packaging (ICEP). [17] Landesberger, Christof et al. "New dicing and thinning concept improves mechanical reliability of ultra thin silicon." Advanced Packaging Materials: Processes, Properties and Interfaces, 21. Proceedings. International Symposium on. IEEE,

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