Innovative Substrate Technologies in the Era of IoTs

Transcription

1 Innovative Substrate Technologies in the Era of IoTs Dyi- Chung Hu 胡迪群 September 4, 2015 Unimicron

2 Contents Introduction Substrate Technology - Evolution Substrate Technology - Revolution Glass substrate Integration of Substrate Embedded Interposer Carrier (EIC) Embedded High Density Film (ehdf) Conclusion Q and A

3 Packaging Requirement in the Era of Everything Connected Cloud Big Data IoT Cloud: High Performance Low Power Low cost Sensors: Low Cost Small form factors Low power Performance Heterogeneous integration

4 Unimicron CSP Product Roadmap- Evaluation Embedded Function EPS FC PoP EAS High Density FCCSP Ultra Thin Ultra Thin CSP (UTS) FC PoP Bond On Line UTS-Embedded Pattern Coreless UTS-EP (3 ~ 8 layers) High Cu pillar PoP UTS-EP (Protrusion bump) Finer, Thinner Multi- Functionality

5 Glass as Substrate and as Interposer Material

6 Glass as a Candidate for Substrate Larger panel size than Si wafer Potential lower material cost and less process flow Insulator, no liner required. Can start with thin glass, no substrate thinning required. CTE from 3~10ppm/ available Smooth surface Fine line process : L/S 3/3µm 300mm Silicon Wafer 500mm Glass Panel ~200 packages (20mm 14mm) ~800 packages (20mm 14mm)

7 Million Dollar Questions: How to get cost effective glass via? How to fill the glass via cost effectively? 7

8 How to Evaluate the Glass Via? TGV Diameter: Top Bottom Taper ratio TGV Roundness TGV Quality Crater Chipping Crack Surface Roughness Via Position Accuracy Via Forming Speed 106µm 75µm 70µm 30µm Glass Via Few years ago

9 TGV by Via Mechanics (Example 1) Glass thickness: 100µm Via Size: 36µm (T), 30µm (B) Taper Ratio: 83% Via Pitch: 100 µm Via Top Via Bottom Top View Cross Section view *: Courtesy of Via Mechanic, Ltd

10 TGV by LPKF (Example 2) Glass thickness: 100µm Via Size: 20µm (T) Via Pitch: 50 µm 20µm glass via Glass Via, Top View 25µm on 50µm pitch *: Courtesy of LPKF, AG

11 TGV and Blind Via by Corning (Example 3) Thickness: ~100µm 700µm Space edge to edge 24µm Type of Vias: Aspect RaKo: Hole Diameter: Blind Via, Thru Via ~ 3-10:1 100µm 20µm 10µm Fully pa6erned wafer with 100,000s of holes 90µm 35µm 100µm 330 µm Thru- holes on thin glass Thru- Holes on thick glass 40µm 35µm 120µm 225µm Blind- holes 120µm deep Blind- holes 225µm deep *: Courtesy of Corning Co.

12 Progress of Glass TGV Via Throughput Throughputs Improvement Years Note: The TGV throughput data is via pattern dependent.

13 Glass Via Filling Technology Via in Via Direct Cu conformal plating on glass Filled Via in Glass Conformal plating for TGV metallization. D=30µm Glass 100µm 300µm Glass 200µm Direct Cu plating Via in via Filled via Unit: µm

14 Glass as Laminated Core Replacement Material Development of 2+2 glass Substrate ABF TGV Filling Via in via laser drilling

15 508x508 mm Glass Panel Demonstrator Full panel glass can be processed through the HVM line. Glass thk.= 100~200µm Glass size = 508mm 508mm 508mm 508mm IMAPS 2014, Yu Hua Chen, Shaun Hsu, Urmi Ray, Ravi Shenoy, Kwan-Yu Lai, Aric Shorey, Rachel Lu, Windsor Thomas, Dyi-Chung Hu Unit size : 20mm x 20mm

16 Warpage Comparison between Glass and Organic Substrate Glass core have ~3x better flatness (R <0.5mm) than organic core (R <1.5mm). Glass Organic substrate Core Material Core Thickness 200µm 200µm Panel Size 508mm 508mm 508mm 508mm R value 0.490mm 1.367mm Std. Dev mm 0.273mm Core Material CTE 3.17ppm/ 3ppm/

17 Challenges of Fine Line (L/S 2µm) Technology in Panel Large panel level exposure system High resolution and sensitivity photoresist materials Thickness uniformity of photoresist on panel Control of seed layer removal Availability of dielectric materials Warpage during asymmetric build. *: Dyi Chung Hu. etc, ICEP Japan April 2015

18 Fine Line in Double Dielectric Layers on Glass Substrate - Demostration Two layers of fine copper lines on glass substrate; by panel level optics. Lin width 1.9µm 1.8µm 1.7µm Glass D2 D1 Cu trace height on the 2 nd layer: ~ 3µm BUF *: Dyi-Chung Hu. etc., ICEP, Japan April 2015

19 Glass as Interposer Material TPV Via Diameter (µm) 30um 20um 10um 5 um IC Fab Si Interposer Glass Via/Hole Interposer type (Filled Via) 5um 10um 20um Line Width (µm) 30um

20 The Glass Interposer Specification Glass interposer specifications Glass Interposer Schematic 12 Glass Wafer Size Design 21 mm x 14 mm Connection Pad Pillar D: 20 µm Pillar pitch: 40 µm Cu pillar height: 4 µm Glass Interposer I-1 passivation Dielectric thickness: 6 µm I-1 metal Line/space: 3 µm / 3 µm Pad f: 40 µm, Cu thickness: 3 µm Substrate Side Chip Side TGV TGV D: 25 µm, TGV depth: 100 µm *: Corning Glass

21 Solutions Needed for Next Generation Substrate TPV Via Diameter (µm) 70um 30um 10um 5um Low Cost Solution needed IC Fab Si Interposer Laminate Substrate: Substrate PCB 5um 10um *: Dyi-Chung Hu, GIT 2014, Invited Talk 20um Line Width (µm) 30um

22 Current Major Solution Proposals for Fine Line Substrate 2.5D interposer (TSMC, UMC..) Silicon/Glass Substrate fine line RDL on both sides. (GIT/Unimicron, NTK, Shinko..) 2.1D substrate (Altera, Shinko, Kyocera..) Glass Interposer 2.1D EMIB EMIB (Intel) EIC; Embedded interposer Carrier (/Unimicron) ehdf (/SiPlus) EIC ehdf *: Edit

23 Die Last High Density Interconnection Substrate Solutions Types Glass Interposer 2.5D Interposer 2.1D Interposer Solder Joins on Substrate side Through holes Z- Profile Organization 1 1 GIT/Unimicron, NTK, Shinko 1 2 TSMC, UMC, Global Foundry, ASE, SPIL, Amkor,. 0 1 Altera, Semco, Shinko, Kyocera EMIB 0 1 Intel EIC 0 1 Unimicron ehdf 0 0 SiPlus/Unimicron

24 Unimicron Embedded Interposer Carrier Technology (EIC)

25 Chip on Interposer on Substrate vs. FC-EIC CoIoS FC-EIC *:USP Patent Chip on Interposer on Substrate: (CoIoS) Interposer need double side RDL/Bumping and assembly process. Four testing steps are used: Interposer, carrier, Interposer+carrier, chip+interposer +carrier. FC-EIC : Flip Chip Embedded Interposer Carrier Interposer need to be embedded into the substrate. Only two testing steps are used: interposer, and interposer+carrier. Risk of thin wafer handling process is reduced..

26 EIC-Silicon/Glass/Ceramic Structure Cross Section View- Examples Laminated Substrate Laminated Substrate I0 Silicon Interposer Glass Interposer An Innovative Embedded Interposer Carrier for High Density Interconnection ECTC 2013,, TJ Tseng, YH Chen, W Lo Embed Glass Interposer to Substrate for High Density Interconnection ECTC 2014,, YP Hung, YH Chen, RM Tain, W Lo

27 Electrical Measurement and Reliability Test of EIC-Glass Substrate Open/Short Test of the EIC substrate. Pass 50 TGV vias, total resistance around 11 Ohms. Resistance stable after 1000X TCT test Chip side R e sista nc e ( Ω) Upper limit: 10% Lower limit: 10% sample 1 daisy chain 4~ Daisy Chain No Substrate Side TCT(X)

28 Solutions for Next Generation Substrate IoS (Integration of Substrates) TXV Via Diameter (µm) 70um 30um 10um 5um IC Fab Si Interposer Laminate Substrate PCB Integration of Substrates (IoS) Low cost Solution needed 5um 10um 20um 30um Line Width (µm)

29 Integration of Substrates Embedded High Density Film (ehdf) Solder-less and Core-less Solution

30 New Structure of Embedded High Density Film (ehdf) Conventional Structure CoIoS Embedded High Density Film (ehdf) Z-height reduction High Density Film Laminate Substrate Thin and Flat Remove all solder joints Remove all through holes

31 ehdf SiP Solution Advantages A green solution: not only Pb free but free of Pb. A true die last solution. Satisfy both fine line and thick line requirements of substrate. Good electrical performance: short interconnection length. (electrical signal no need to go through cores and solder joints) Less Materials used: no core and no solder joints inside the ehdf substrate Compatible with current OSAT infrastructure. ehdf Cost reduction advantage by: Remove core of interposer; (TXV and copper filling constitute 30% of interposer cost.) Remove solder joining process; without the cost of solder, the cost of assembly process and assembly yield loss. Reduce individual test of interposer, substrate and PCB; from multiple tests to one final test. Large panel (500x500mm up) process possible for further cost down.

32 Conclusions Substrate technology are under great changes due to the progress of the Moore s Law in semiconductor and the society is entering the era of IoTs, i.e. more heterogeneous integration. Low cost solutions for both in high end and in low end are needed. New substrate materials such as glass is starting to find some applications in electronic packaging. New packaging technology such as InFO-WLP, EMIB, SWIFT, EIC and ehdf technologies are emerging to meet the customer requirements. Cost reduction solutions is the key. It is a challenging time and also opportunity time for all the material, equipment and substrate makers. And there are still many innovative solutions needed to meet the challenging in the electronic packaging industry.

33 Thanks You for Staying to the last Talk of the Day!

34 Appendix: Terminology Technology Details Company InFO-WLP EMIB SWIFT EIC ehdf Integrated Fan Out Wafer Level Packaging Embedded Multi-die Interconnect Bridge Silicon Wafer Integrated Fan out Tech TSMC Intel Amkor Embedded Interposer Carrier Unimicron Embedded High Density Film SiPlus, Unimicron IoS Integration of Substrates SiPlus, Unimicron