Novel electron beam lithography technique for submicron T-gate fabrication

Size: px

Start display at page:

Download "Novel electron beam lithography technique for submicron T-gate fabrication"

Marilyn Morris
6 years ago
Views:

1 Novel electron beam lithography technique for submicron T-gate fabrication M. M. Ahmed a) and H. Ahmed Microelectronics Research Centre, Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE, United Kingdom Received 8 August 1996; accepted 17 January 1997 Submicron T gates have been fabricated using the high resolution electron beam lithography technique. The footprint of the T gate has been written in high molecular weight poly-methyl methacrylate PMMA, whereas the top of the T gate is defined in AZ PF 514. A 400 nm thick layer of PMMA was first exposed and developed followed by the spinning of AZ PF 514. A wide line defining the top of the T gate was written in this resist which after development gave a T-shaped cross section. As both the bottom and the top of the T gate are dealt with independently, therefore, the technique provides a high degree of control and flexibility in the fabrication process. Moreover, the possibility of shorting of the top of the T gate with the Ohmic metallization is virtually impossible. Consequently, the process is a very good candidate for low-noise GaAs metal-semiconductor field-effect transistors MESFETs fabrication in which a narrow drain-to-source gap is required. GaAs MESFETs with T-shaped gates have been fabricated and characterized by dc measurements American Vacuum Society. S X I. INTRODUCTION In order to achieve a high operating frequency and high transconductance, a short gate length is essential for metal semiconductor field effect transistors MESFETs and high electron mobility transistors HEMTs. 1 The reduction in gate length also results in a decrease in the feedback and input capacitances, and short transit time. 2 However, the improvement in the noise figure with the improved saturation velocity and cutoff frequency is limited because of the high gate resistance associated with the submicron pyramid gate. 3 To obtain a low gate resistance while still retaining a very short footprint, a T-shaped cross-section gate has been developed. 4,5 T-shaped gate fabrication using the multilayer resist process has been reported by many authors. 6 8 In this technique polymethylmethacrylate PMMA and its methacrylic acid copolymer PMMA-MAA are used as a low LO and high HI sensitive resists, respectively. Two or three coating of these resists as HI/LO or LO/HI/LO, and use of tailored energy deposition provide a T-gate profile. However, resist intermixing during spinning and baking reduces the process latitude for this method. In a multilayer resist process T-gates down to 100 nm are successfully fabricated. But the process is not directly applicable to FET mass production, because it is difficult to define the submicron footprint reproducibly in thick resist typically 1 m, due to electrons scattering. Hybrid lithography technique ion beam and electron beam lithography is also used for submicron T-gate delineation. 9,10 In this technique a thick resist layer typically 1.2 m is exposed by an ion beam which penetrates partially into the resist and defines the wide upper part of the T gate, while the lower part of the T gate is defined by an electron beam. T-gate fabrication has also been demonstrated using the sandwich structure. 11 In this process a Electronic mail:mansoor@giki.sdnpk.undp.org a critical thickness of a light metal e.g., Al is deposited between two coatings of the resist and the backscattered electron signal allows the alignment through the thin metal layer. But this technique is not very successful because of its complexity and the bubbling of metal during heat treatment. Vanbremeersch et al. 12 and Atwood 13 have fabricated T gates using the etched dielectric to define the footprint. Later Nummila et al. 14 used the same technique and made the T gates as small as 60 nm. Ren et al. 15 have demonstrated the fabrication of submicron T-gates GaAs MESFETs using a simple low temperature SiN x deposition and etchback process. In this study, T gates have been fabricated using two different positive-working electron-sensitive resists. The foot of the T gate was defined in a thin layer of PMMA by a high resolution electron beam machine and developed in a mixture of IPA and MIBK. The top of the T gate was defined in AZ PF 514, another electron sensitive resist and the developer used was AZ 400 K. This is a water based developer and does not attack PMMA. Since both the resists were exposed and developed independently using different developers, the process therefore, provides a high degree of control and flexibility in T-gate fabrication. II. BASIC TECHNIQUE INVOLVED IN T-GATE FABRICATION T-gate fabrication using the two-step lithography technique is outlined schematically in Fig. 1. A 400 nm thick layer of PMMA was first spun on the chips and hard baked at 180 C. Hard baking provides a robust mask for subsequent gate-recess etching. To define the gate length of the device, 0.2 m lines were written by the EUCLID at 60 kv with the beam diameter better than 400 Å. After development a 1 m thick layer of AZ PF 514 resist was applied, and the 306 J. Vac. Sci. Technol. B 15(2), Mar/Apr X/97/15(2)/306/5/$ American Vacuum Society 306

307 M. M. Ahmed and H. Ahmed: EB lithography technique 307 FIG. 2. SEM micrograph showing a cross-sectional view of a 0.2 m wide line written in PMMA. FIG. 1.

chips were then baked at 80 C, which is well below the glass transition temperature of PMMA. For the top opening of the T gates, 0.

Although the incident beam of electrons penetrated down to the substrate, 16 yet, there was no harm done to the bottom layer, because the top layer was developed in a water based developer AZ 400 K

2 307 M. M. Ahmed and H. Ahmed: EB lithography technique 307 FIG. 2. SEM micrograph showing a cross-sectional view of a 0.2 m wide line written in PMMA. FIG. 1. The schematic diagram of T-gate fabrication sequence. a Resist coating for stem of T; b EB exposure and development; c resist coating for top of T; d EB exposure and development. chips were then baked at 80 C, which is well below the glass transition temperature of PMMA. For the top opening of the T gates, 0.6 m wide lines were written again at 60 kv on the top of the previously developed PMMA lines. Although the incident beam of electrons penetrated down to the substrate, 16 yet, there was no harm done to the bottom layer, because the top layer was developed in a water based developer AZ 400 K which was ineffective to PMMA. The AZ PF 514 is a chemically amplified resist, therefore, a 2 min postbaking at 80 C was also given prior to the development in order to complete the chemical reactions. III. OPTIMIZATION OF DOSE FOR T-GATE LITHOGRAPHY Submicron lines have been written in PMMA with variable electron beam dosage and examined in SEM. Figure 2 shows a cross-sectional view of PMMA opening at 15 C m 2, whereas Fig. 3 represents variation in the line profiles as a function of electron beam dosage constant development time. As illustrated in Fig. 3, W 1 and W 2 are the linewidths at the resist surface and bottom, respectively. The minimum dose required to clear the resist down to the substrate is 11 Cm 2. At this dose the resist has overcut profile and remains as it is up to the dose of 13.5 C m 2, after which it becomes vertical. By further increasing the dose the profiles become undercut. An overcut profile provides the shorter gate length and good connectivity, while an undercut profile gives a longer gate length and poor connectivity, because of the thinning of the top edge of the stem of T, which is inherent to the liftoff metallization. The electron beam dosage above the unity marker Fig. 3 on the y axis shows the overcut profiles, whereas the portion of curve under the unity line represents all those values which give under-cut profiles. The dependence of line profiles on electron beam dosage for AZ PF 514 resist was also studied, and the results are plotted in Fig. 4. There is no appreciable variation in W 1 as a function of dosage; it becomes constant after the dose of 0.11 C m 2. However, the increasing trend of W 2 with electron beam dosage shows that the undercut is more pronounced with the higher doses. A dose of 0.15 C m 2 is seen to be optimum for T-gate lithography. Figure 5 shows a FIG. 3. Variation in line profiles as a function of electron beam dosage in PMMA. JVST B - Microelectronics and Nanometer Structures

308 M. M. Ahmed and H. Ahmed: EB lithography technique 308 FIG. 4. Variation in line profiles as a function of electron beam dosage in AZ PF 514.

ALIGNMENT STRATEGY FOR UPPER AND LOWER PARTS OF T GATES The top and the bottom patterns were aligned on each other by two sets of registration marks: a Coarse registration marks these were four 30 m

These alignment markers were of the same metallization as that of Ohmic, so the process is fully compatible with the microwave device fabrication.

3 308 M. M. Ahmed and H. Ahmed: EB lithography technique 308 FIG. 4. Variation in line profiles as a function of electron beam dosage in AZ PF 514. cross-sectional view of a line in AZ PF 514 resist, written with a dose of 0.15 C m 2. It has a decent undercut profile for the lift-off metallization. IV. ALIGNMENT STRATEGY FOR UPPER AND LOWER PARTS OF T GATES The top and the bottom patterns were aligned on each other by two sets of registration marks: a Coarse registration marks these were four 30 m big crosses located at the four corners of the 400 m 400 m field. b Fine registration marks these were 4 m big squares inside the 200 m 200 m field. These alignment markers were of the same metallization as that of Ohmic, so the process is fully compatible with the microwave device fabrication. The final alignment was made by viewing the fine registration marks with 8 m 8 m scanned field, which appeared to FIG. 5. SEM micrograph showing a cross-sectional view of a line written in AZ PF 514 resist. FIG. 6. An end view of a 200 nm long and 30 m wide Ti/Au T gate. be adequate for accurate calibration and orthogonality adjustment. Figure 6 shows an end view of a 200 nm long and 30 m wide T gate. The thickness of gate metallization, Ti/Au was 450 nm. SEM examination of five different chips revealed that the overlay accuracy is better than 50 nm, which is inside the acceptable margin, i.e., 100 nm, whereas the yield of this system was about 80%. 17 Since the bottom layer of the resist PMMA protects the Ohmic metallization when the top of the T gates are being written, therefore, the chance of shorting of the top of the T gates with the Ohmic metallization is virtually impossible. Furthermore, as the top and the bottom of the T gates are dealt with independently the technique, therefore, provides an extra control on T-gates fabrication in low-noise GaAs FET technology. V. GaAs MESFETs Wafers were grown by molecular beam epitaxy on a semi-insulating GaAs substrate. The layer structure of the wafer, from bottom to top, consists of an AlGaAs undoped buffer layer, 1.5 m undoped GaAs smoothing layer, and finally a 0.2 m Si doped GaAs layer cm 3 ). The working chip s dimensions were 5 5 mm 2 and each chip contained 12 four finger MESFETs, a transmission line model TLM for contact resistance measurements and two recess measurement structures. The total working area was mm 2. A mesa was fabricated by an optical lithographic process. The mesa was 25 m 100 m with 50 m long crosses at the corners of each field of m 2. Etching was carried out in a solution of 50% diluted citric acid and hydrogen peroxide 10:1 by volume. Ohmic contact delineation was accomplished by electron beam lithography. Ohmic metallization layers, AuGeNi/Au 100/200 nm were evaporated at a base pressure of Torr in a single sequence without breaking the vacuum. Liftoff was completed in hot acetone 40 C. The contacts were alloyed by rapid electron beam J. Vac. Sci. Technol. B, Vol. 15, No. 2, Mar/Apr 1997

309 M. M. Ahmed and H. Ahmed: EB lithography technique 309 FIG. 7. SEM micrograph showing a global view of a four finger MESFET. annealing at a temperature of 420 C.

After gate lithography, the gate recessed was carried out in H 2 SO 4 :H 2 O:H 2 O 2 solution.

4 309 M. M. Ahmed and H. Ahmed: EB lithography technique 309 FIG. 7. SEM micrograph showing a global view of a four finger MESFET. annealing at a temperature of 420 C. TLM measurements yielded a specific contact resistance of cm 2. Drain-to-source spacing was 1.5 m. After gate lithography, the gate recessed was carried out in H 2 SO 4 :H 2 O:H 2 O 2 solution. The target drain current was achieved by intermittent drain-source I V measurements during the recess process. The oxide layer was trimmed off in diluted HCl acid before Schottky metal evaporation. Gate metallization, Ti/Au 30/420 nm, was then evaporated at a base pressure of Torr and the extra metal was lifted off in acetone. Airbridges were then fabricated to interconnect the inner and outer sources. For airbridge fabrication a single coat of Shipley TF-20 resist was spun on, which gave a 5 m thick uniform layer of the resist. Airbridge postgeometry together with the bond pads were exposed in contact under the UV lamp, operated at 310 W. The exposed pattern was developed in a Shipley MF 319 developer without postbake in order to have a maximum slope. 18 The diffraction of UV light from the edges of mask caused a lateral exposure of the resist resulting in a rounded profile which was further smoothed with heat treatment. After heat treatment a relatively thin layer of Shipley S-1813 resist was applied, baked at 85 C for 10 min and blanket exposed, then another layer of the same resist was spun on it, making a total thickness of 2 m, exposed and developed in the same developer. Prior to the development the chips were soaked in chlorobenzene for 2 min to get an undercut profile. The idea behind the blanket exposure is to achieve a smooth and sharp edge profile of the airbridge, with the isotropic penetration of developer. Finally, airbridge metallization layers, Ti/Au/Ag/Au 1.6 m, was evaporated and lifted off in acetone. An oblique view of a complete four finger MESFET is shown in Fig. 7. The output characteristic of a 200 nm long T-gate GaAs MESFET is shown in Fig. 8 a, whereas the Schottky response of the same device which was observed during the I V measurement is given in Fig. 8 b. A very low gate current shows a good nature of Schottky barrier and minimal contamination at the metal semiconductor interface. 19 The FIG. 8. Direct current characteristics of a 4 25 m GaAs MESFET having 200 nm long T gate. a Shows the output characteristics and b gives the gate current vs drain-to-source voltage by considering gate bias as a parameter. electrical functionality of each T-gate finger was confirmed by the I V characteristics. If any of the gate finger is not making a Schottky contact, the channel will not deplete fully and the device as a whole will not exhibit a complete pinchoff. VI. CONCLUSION A novel electron beam lithographic technique has been developed for the fabrication of submicron T gates. This technique employed two different electron beam resists which are exposed and developed independently. The stem of the T gate is defined in high resolution electron beam resist, PMMA, and the bar of the T gate is written in AZ PF 514. Each process is completed separately with exposure and development because both resists are of different chemical nature. T-shaped gates are finally achieved with liftoff metallization and the technique is compatible with microwave device fabrication sequence. Submicron GaAs MESFETs have been fabricated with T-shaped Schottky gates and characterized by dc measurements. JVST B - Microelectronics and Nanometer Structures

5 310 M. M. Ahmed and H. Ahmed: EB lithography technique R. K. Watts, Submicron Integrated Circuit Wiley, New York, K. L. Tan, R. M. Dia, D. C. Streit, T. Lin, T. Q. Trinh, A. C. Han, P. H. Liu, P. D. Chow, and H. C. Yen, IEEE Electron Device Lett. 11, P. M. Smith, M. Y. Kao, P. Ho, P. C. Chao, K. H. G. Duh, A. A. Jabra, R. P. Smith, and J. M. Ballingall, IEEE MTT-S Dig. 1989, P. C. Chao, W. H. Ku, P. M. Smith, and W. H. Perkins, IEEE Electron Device Lett. 4, A. Marten, H. Schenider, H. Schweizer, H. Nickel, W. Schlapp, R. Lösch, H. Dämbkes, and P. Marschall, J. Vac. Sci. Technol. B 9, R. C. Tiberio, J. M. Limber, G. J. Galvin, and E. D. Wolf, Proc. SPIE 1089, N. Samoto, Y. Makino, K. Onda, E. Mizuki, and T. Itoh, J. Vac. Sci. Technol. B 8, L. Luciani, L. Gentili, E. D. Fabrizio, B. Gabbrielli, and S. P. A. Telettra, Microelectron. Eng. 17, K. Hosono, H. Minami, H. Kusunose, T. Fujino, T. K. Nagahama, H. Morimoto, and Y. Watakabe, J. Vac. Sci. Technol. B 7, R. G. Woodham, J. R. A. Cleaver, H. Ahmed, and P. H. Ladbrooke, J. Vac. Sci. Technol. B 10, S. G. Bandy, Y. G. Ghai, R. Chow, C. K. Nishimoto, and G. Zdasiuk, IEEE Electron Device Lett. 4, J. Vanbremeersch, E. Constant, J. Zimmermann, I. Valin, P. Godts, and A. Leroy, Electron Lett. 26, A. Atwood, Proc. SPIE 1263, K. Nummila, M. Tong, A. A. Ketterson, and A. Adesida, J. Vac. Sci. Technol. B 9, F. Ren, S. J. Peaton, J. R. Lothian, and Abernathy, J. Vac. Sci. Technol. B 11, J. C. H. Phang, Ph.D. dissertation, University of Cambridge, UK, M. M. Ahmed, Ph.D. dissertation, University of Cambridge, UK, R. Williams, Modern GaAs Processing Methods Artech House, Boston, M. M. Ahmed, H. Ahmed, and P. H. Ladbrooke, J. Vac. Sci. Technol. B 13, J. Vac. Sci. Technol. B, Vol. 15, No. 2, Mar/Apr 1997

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative