TSV Interposer Process Flow with IME 300mm Facilities

Transcription

1 TSV Interposer Process Flow with IME 300mm Facilities Property of Institute of Microelectronics (IME)-Singapore August 17, 2012

2 Outline 1. TSV interposer (TSI) cross sectional schematic TSI with BEOL, TSI with BEOL and IPD, TSI with RDL. 2. Process flows and examples for TSI wafer fabrication and TBDB for thin wafer handling. TSV formation BEOL RDL UBM and micro-bumping Thin wafer handling and back side TSV revealing Backside RDL and UBM 3. Summary 2

3 TSI with BEOL T[6]=1-2μm T[8]=1-2μm T[7]=1-2μm Cu/Ni/Au Al T[4]=1-2μm T[3]=1-2μm T[2]= 1-2μm T[1]=1-2μm T[5]=1-2μm 16μm>W>2μm S>2μm 16μm>W>2μm Si substrate 28-Aug-12 TSV ø10μm 10um (Cu) ~100μm Polyimide BS RDL Front side (FS): TSV + upto 4 BEOL layers + UBM Backside (BS): 1 layer RDL layer + C4 bump BS UBM 3

4 TSI with BEOL and IPDs T[6]=1-2μm T[8]=1-2μm T[7]=1-2μm Cu/Ni/Au Al T[5]=1-2μm T[4]=1-2μm T[3]=1-2μm T[2]= 1-2μm T[1]=1-2μm MIM capacitors Resistors 16μm>W>2μm TSV ø10μm Si substrate 28-Aug-12 10um (Cu) ~100μm Polyimide BS RDL Front side (FS): TSV + upto 4 BEOL layers + MIM capacitors + Resistors + UBM Backside (BS): 1 layer RDL layer + C4 bump BS UBM 4

5 TSI with RDL FS UBM 3 rd FS RDL T=5-7μm T=5-7μm T=3μm polyimide 2 nd FS RDL 1 st FS RDL Liner oxide H 100µm TSV ø10µm Cu B/S BS UBM Front side (FS): TSV + up to 3 layers RDL layers + UBM Backside (BS): 1 layer RDL layer + C4 bump 5

6 Process Flow for TSV Fabrication 1. Hard mask deposition 2. TSV patterning and etching 3. Liner oxide deposition 4. Barrier and seed layer deposition 5. Cu ECP and annealing 6. CMP Key challenges: 1. TSV etching: small scallop, uniformity, straight profile 2. Liner oxide: high step coverage 3. Barrier and seed layer: high step coverage 4. Cu ECP: void free, seam free, small over burden 5. CMP: small oxide loss, uniformity 6

7 TSV Formation Challenges Challenges Examples How to deal with? TSV etching 1. Uniformity control 2. Scallop control 3. Profile control Botch etching recipe optimization, gas flow, pressure, cycling time, RF power, etc. Liner oxide CVD 1. Step coverage 2. Scallop smoothing SACVD O3 TEOS Upto 50% step coverage Smooth the scallop. B/S layer PVD Step coverage Seed layer discontinuity PVD process optimization. Min 5% step coverage is Required. ECP 1. Void-free 2. Low overburden Void in TSV ECP recipe tuning. 7

8 Good Example: Through Si-Via Formation - Modules/Integration 3D-AFM Post-CMP Eval. TSV Etcher (Silvia); Unifire Straight profile (~90 o ) High cross wafer uniformity (<2%) Low scallop (<50nm) D/H ~5μm/50μm Clean (Akrion) + CVD Liner (InVia) Pre-Clean Optiimization High step-coverage (Side>50%; Bottom >20%) PVD B/S (Endura, Charger) Step-Coverage Gap-Fill Co-optimization Cu CMP (Reflexion) Good post-cmp control Proper removal rate Accurate end point detection Post-CMP Topography (AFM) <50nm Furnace Cu Anneal Well Optimized Temp. Profile Cu ECP (Raider) Void free Low overburden (~2.5mm) Low mounds (<3mm) X-ray Via Fill Evaluation 8

9 Process Flow for BEOL Fabrication 1. M1 dialectical layers Si 3 N 4 /SiO 2 deposition 2. M1 pattern, etch and clean 3. M1 seed layer PVD, Cu ECP and CMP 4. M2 dielectric deposition 5. Via 1 and M2 pattern, etching and clean 6. Via 1 and M2 seed layer PVD, Cu ECP and CMP 7. M3, M4, and Al pattern Key challenges: 1. Diametric etching: uniformity, high SiO2 etching selectivity to Si3N4 2. ECP: void free 3. CMP: small oxide loss, uniformity 9

10 Process Flow for RDL Fabrication PR PR 1. Seed layer deposition and PR patterning Polyimide 2. Cu plating PR 3. PRS and Seed layer etching 4. Polyimide passivation and patterning 5. Seed layer deposition and PR patenting 6. Cu ECP to form 2 nd RDL 7. Repeated RDL process to form RDL and passivation Key challenges: 1. RDL PR patterning: fine line/space smaller than 5μm/5μm 2. RDL ECP: Micro loading effect 3. Passivation opening lithography process: tapered via profile, via size uniformity 4. Seed layer etching: etching uniformity, small undercut 10

11 RDL Process Challenges Challenges Examples How to deal with? RDL PR patterning 1. Need fine line/space less than 5μm/5μm 2. Uniform and complete de-scum process Fine line PR patterning PR material improvement. Patterning optimization. ECP Micro-loading effect Plated thickness difference among different pattern densities. ECP recipe optimization Passivation opening 1. Need tapered via profile, via. 2. Size uniformity. 3. De-scum Profile that is not suitable for next RDL seed layer deposition. PVD process optimization. Min 5% step coverage is Required. Seed layer etching rate and uniformity control Seed layer etching caused undercut and line width shrinkage ECP recipe tuning. Design CD bias. 11

12 Example: RDL formation Modules / Integration PVD for Seed Layer Suss Track Spin-Coat & Soft Bake Ultratech Stepper PR Patterning Cu ECP (Semitool) Cu Electroplating PRS (Suss Track) PR lift off Seed Layer Patterning (GPTC Metal Spray Etcher) Wet-Etch Seed layer Line Width/Space ~ 5mm/5mm Line Width/Space ~ 3.5mm/2.5mm PR Mold Patterned On Ti/Cu Seed Layer (SL) ECP Cu RDL After SL Etch off 12

13 Process Flow for UBM / Landing Pads or Micro-bumping PR 1. Passivation opening 2. Seed layer deposition 3. PR patterning to define the UBM area PR Key challenges: 1. Fine pitch thick PR patterning 2. Seed layer etching: etching uniformity, small undercut 4. UBM plating (Cu/Ni/Au) 5. PR strip and seed layer etching 13

14 UBM and Micro-bumping Process Challenges Challenges Examples How to deal with? Thick PR patterning 1. Straight profile 2. Size control 3. Uniform and complete de-scum process Litho process optimization De-scum process control ECP loading effect 1. Better design rule to control the density uniformity. 2. ECP process tuning to improve plating thickness uniformity. 14

15 UBM, Micro-bumping and Micro-joining Modules / Integration Bottom Wafer Landing Pad (Raider ECD) Landing pads Stack: ~5µm-Cu / ~0.3µm-Au Pitch: X=50µm, Y=30µm Top Wafer Micro-bump Formation: (Bottom Plate & Patterning; Raider ECD Cu-Pillar / SnAg, Flux coater, Reflow Furnace, Clean) Micro-bumps Stack: 10µm-Cu / 10µm-SnAg Pitch: X=50µm, Y=30µm Au-Surface SnAg Cu-Base Flux Coat Reflow Clean Cu-Pillar CD~20mm Chip-to-Chip Bonding (TCB/FET300) Top-Chip Bottom-Chip 15

16 Thin Wafer Handling + Backside Revealing (BSR) Si-carrier Si-carrier Si-carrier 1. Temporary bonding 2. Device wafer thinning 3. Passivation Si-carrier Key challenges: 1. TTV control 2. Void free through-out the whole process 3. Chipping and cracking free during de-bonding 4. CMP 16

17 TBDB Approach Thin Wafer Handling and Challenges Challenges How to deal with? Result and remark TTV control Adhesive Carrier wafer 1. Coating optimization 2. Back grinding and CMP process optimization 1. <8μm for 100μm adhesive 2. <5μm for 50μm adhesive 3. <3μm for 30μm adhesive Edge cracking during BG Cracks 1. Edge trimming on device wafer before bonding 2. Bonding process optimization No edge cracking and chipping Void in adhesive 1. Dehydration bake and pre-bake for both device and carrier wafer 2. Bonding process optimization No void or delamination after bonding and RDL process De-bonding damage Edge chipping 1. EZR process optimization 2. De-bonding process optimization De-bonded successfully without edge cracking or chipping 17

18 Si-carrier Backside RDL and UBM Si-carrier Si-carrier 1. Backside TSV revealing 2. Backside RDL formation 3. Polyimide passivation and opening Si-carrier 4. Backside UBM formation 5. De-bonding 18

19 Reliable TSV integration process flow i-line TSV patterning TSV etching and cleaning Liner oxide deposition PVD barrier and seed layer deposition ECP process for TSV void-free filling CMP Target Deliverables BEOL and RDL process Thick Cu damascene process Fine line PR patterning process for Cu plating RDL passivation Thin wafer handling, backside RDL and micro-bumping Device wafer preparation Carrier wafer choice and preparation Temporary bonding optimization Wafer thinning down optimization to minimize device wafer TTV Si recess etching with high selectivity to SiO 2 CMP process to reveal TSV with minimized oxide loss PVD process which is compatible with temporary bonded wafers Curing 19

20 Thank You. Q & A 20