New Materials and Processes for Advanced Chip Manufacturing
|
|
- Prosper Elliott
- 6 years ago
- Views:
Transcription
1 New Materials and Processes for Advanced Chip Manufacturing Bob Hollands Director Technical Marketing EXANE BNP Paribas Tech Expert Access Event London June 27, 2013
2 Outline New Materials: Moore s Law Enablers Major Trends in Thin Film Deposition The ALD Technology Platform as a Response FinFET related challenges and Metal ALD PEALD as a Low Temperature Enabler Summary and Conclusions 2
3 Scaling will increasingly be enabled by New Materials and 3D Technologies Scaling enabled by Litho Scaling enabled by Materials IEDM 2002 IEDM 2003 Low-k Strained Si Scaling enabled by 3D Chipworks 2012 IEDM 2007 High-k FinFET 3D SIC 3D Memory 3
4 Increasing Introduction Rate of New Materials BEOL FEOL Starting Mat l Al-Cu SiO, SiN Si (B)PSG Al-Cu SiO, SiN Si,epi Si(O)N TiW WSi, MoSi (B)PSG Al-Cu SiO,N Si,epi TiSi Si(O)N Ti/TiN WSi, PtSi (B)PSG Al-Cu SiO,N Si,epi TaO SOP SiOC Ta/TaN Cu SiOF CoSi Si(O)N Ti/TiN W (B)PSG Al-Cu SiO,N Si,epi SiC LaO ZrO Hf(Si)O AlO Porous SiOC SOI SiGe TaO SOP SiOC Ta/TaN Cu SiOF NiSi Si(O)N Ti/TiN W (B)PSG Al-Cu SiO,N Si,epi
5 Higher Capacitance, Lower Leakage New Materials and Processes: Moore s Law Enablers Higher Mobility, Lower Resistance High-k and Metal Gates DRAM, RF, decoupling capacitors Less Cross Talk, Faster Interconnect Strain and new Channel Materials New metal contacts Smaller Feature Sizes (Porous) Low-k Materials Improved Metals Sub-Rayleigh limit patterning using SDDP 5
6 ALD enables new materials and 3D Front-End Operations New materials and 3D applications require more precise and controlled thin film deposition Compared to conventional deposition techniques ALD offers superior: Conformality Step coverage Interface control The ALD market offers strong growth opportunities: High-k metal gate, FinFET Spacer defined double patterning Other emerging applications ASMI is a leading player in the ALD market Developing ALD technology since 1999 Strong IP position Number 1 in high-k gate and strong position in SDDP 6
7 What is Atomic Layer Deposition (ALD)? Front-End Operations Step 1: (Metal) Precursor Chemi-sorption Step 2: Purge Step 3: Reaction to Oxide/Nitride with O 2, H 2 O, NH 3 co-reactant Step 4: Purge and repeat 7
8 Key strengths of ALD relative to conventional deposition Uniformity Step Coverage Min Max TiN 29 nm SiO 2 <1% 3σ <0.7% M-m SEM s Courtesy of Philips Research Labs Interface Control Composition Control Atomically engineered interfaces to optimize leakage current, reliability and work-functions Te V. Pore (2010) Ge 100 Sb Excellent composition control for ternary alloys such as GST and STO 8
9 ASM s unique Materials Development Capabilities ASM Microchemistry (Fi) Pre-cursor Exploration Process Feasibility Basic Materials R&D Cooperative R&D Projects N+ 3 ASM Belgium Process Development Process Integration 15 7 nm Cooperative R&D Projects N+2,3 ASM Europe ASM America ASM Japan ASMGK (Korea) N+1,2 Product Development, Product Engineering, Product Marketing, Cooperative R&D Projects 9
10 Outline New Materials: Moore s Law Enablers Major Trends in Thin Film Deposition The ALD Technology Platform as a Response FinFET related challenges and Metal ALD PEALD as a Low Temperature Enabler Summary and Conclusions 10
11 Major Trends in Thin Film Deposition and ASM s Vision for ALD Thin Film Needs: New materials Thinner films Interface engineering 3D conformality Lower thermal budget Integration Capabilities Subtractive and Damascene patterning Etching Gap fills Clustering ALD is a whole new technology platform for enabling new materials! ALD PEALD.. 11
12 FinFET Challenges: ALD enables Further Scaling in 3D IMEC, 2011 Materials properties and channel length must be uniform over fin height Conformal coverage required ALD technology has become critical for HK and MG layers 12
13 ASM Front-end Products ALD Pulsar XP ALD for high-k Cross-flow reactor Solid source delivery system EmerALD XP ALD for metal gates Showerhead reactor Pulsar XP EmerALD XP 13
14 PEALD as an enabler of Lower Temperature Budget Front-End Operations LT SiO 2 SiO 2 SiN SiCN Deposition Temperature 50 o C 260 o C 360 o C 360 o C Application FEOL SDDP Gate spacer SDDP (LT) Gate spacer Low WER Gate spacer Low temperature deposition of SiO 2 and Si 3 N 4 opens up wide potential application space 14
15 Litho-formed Resist Pattern New Materials enabling Lithography Spacer Defined Double Patterning Depo of SiO 2 at 50C 44nm 22nm Pitch Conformal SiO 2 Anisotropic Etch Pitch/2 Resist Left Center Right ASM, ALD conference 2008; SPIE conference 2009 Uniform CD s: Spacer Thickness NU <1%, 3σ 15
16 ASM Front-end Products PEALD and PECVD Front-End Operations XP8 High productivity single wafer tool for both PEALD and PECVD applications RC3 RC4 RC5 RC6 Accommodates up to 8 chambers for PEALD or PECVD PEALD and PECVD can be integrated on the same platform RC2 RC1 RC8 RC7 16
17 Outline New Materials: Moore s Law Enablers Major Trends in Thin Film Deposition The ALD Technology Platform as a Response FinFET related challenges and Metal ALD PEALD as a Low Temperature Enabler Summary and Conclusions 17
18 Summary Scaling is increasingly enabled by new materials and 3D technologies ALD enables new materials and 3D The ALD market offers strong growth opportunities Adoption of more ALD and PEALD applications in HVM continues ASMI #1 position in ALD for High-k gate 3D FinFET s drive adoption of ALD, not only for the dielectric, but also for metals Strong inroads into patterning applications with PEALD XP8, high productivity system for PEALD applications Drive Innovation, Deliver Excellence 18
19 Drive Innovation, Deliver Excellence
New Materials as an enabler for Advanced Chip Manufacturing
New Materials as an enabler for Advanced Chip Manufacturing Drive Innovation, Deliver Excellence ASM International Analyst and Investor Technology Seminar Semicon West July 10 2013 Outline New Materials:
More informationCMP Defects and Evolution of PCMP Cleans
CMP Defects and Evolution of PCMP Cleans March 27, 2017 Iqbal Ali iali@linx-consulting.com (408)839-9924 SPCC & PCMP Conference, Austin, TX Agenda 1. Introduction to Linx Consulting 2. Where Have We Been
More informationLow temperature deposition of thin passivation layers by plasma ALD
1 Low temperature deposition of thin passivation layers by plasma ALD Bernd Gruska, SENTECH Instruments GmbH, Germany 1. SENTECH in brief 2. Low temperature deposition processes 3. SENTECH SI ALD LL System
More informationTHE IMPACT OF 3D DEVICES ON THE FUTURE OF PROCESS MATERIALS TRENDS & OPPORTUNITIES
THE IMPACT OF 3D DEVICES ON THE FUTURE OF PROCESS MATERIALS TRENDS & OPPORTUNITIES L. Shon Roy K. Holland, PhD. October 2014 Materials Examples Process materials used to make semiconductor devices Gases
More informationALD systems and SENTECH Instruments GmbH
ALD systems and processes @ SENTECH Instruments GmbH H. Gargouri, F. Naumann, R. Rudolph and M. Arens SENTECH Instruments GmbH, Berlin www.sentech.de 1 2 Agenda 1. Company Introduction 2. SENTECH-ALD-Systems
More informationLecture 8. Deposition of dielectrics and metal gate stacks (CVD, ALD)
Lecture 8 Deposition of dielectrics and metal gate stacks (CVD, ALD) Thin Film Deposition Requirements Many films, made of many different materials are deposited during a standard CMS process. Gate Electrodes
More informationInterconnects. Outline. Interconnect scaling issues Aluminum technology Copper technology. Properties of Interconnect Materials
Interconnects Outline Interconnect scaling issues Aluminum technology Copper technology 1 Properties of Interconnect Materials Metals Silicides Barriers Material Thin film Melting resistivity point ( C)
More informationContact Resistance Reduction using Advanced Implant and Anneal Techniques for 7nm Node and Beyond
Contact Resistance Reduction using Advanced Implant and Anneal Techniques for 7nm Node and Beyond Fareen Adeni Khaja Global Product Manager, Front End Products Transistor and Interconnect Group NCCAVS
More informationEmerging Materials for Front End IC Process
Emerging Materials for Front End IC Process Mark Thirsk Linx Consulting +1 617 273 8837 mthirsk@linx-consulting.com Device Making Unit Operations - 2007 100% 0.065 Total = 12,229,682 80 0.09 60 40 0.13
More information2006 UPDATE METROLOGY
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS METROLOGY THE ITRS DEVED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS
More informationInterconnects OUTLINE
Interconnects 1 Interconnects OUTLINE 1. Overview of Metallization 2. Introduction to Deposition Methods 3. Interconnect Technology 4. Contact Technology 5. Refractory Metals and their Silicides Reading:
More informationLecture Day 2 Deposition
Deposition Lecture Day 2 Deposition PVD - Physical Vapor Deposition E-beam Evaporation Thermal Evaporation (wire feed vs boat) Sputtering CVD - Chemical Vapor Deposition PECVD LPCVD MVD ALD MBE Plating
More information450mm Metrology and Inspection: The Current State and the Road Ahead. Rand Cottle (CNSE), Nithin Yathapu (GF), Katherine Sieg (Intel)
450mm Metrology and Inspection: The Current State and the Road Ahead Rand Cottle (CNSE), Nithin Yathapu (GF), Katherine Sieg (Intel) Outline Program Update Demonstration Testing Method (DTM) Equipment
More informationInvestor presentation 24 April 2013
Investor presentation 24 April 2013 2009 ASM Proprietary Information Safe Harbor Statements All matters discussed in this business and strategy update, except for any historical data, are forward-looking
More informationNonplanar Metallization. Planar Metallization. Professor N Cheung, U.C. Berkeley
Nonplanar Metallization Planar Metallization Passivation Metal 5 (copper) Metal 3 (copper) Interlevel dielectric (ILD) Via (tungsten) Metal 1 (copper) Tungsten Plug to Si Silicon Caps and Plugs oxide oxide
More informationManufacturer Part Number. Module 2: CMOS FEOL Analysis
Manufacturer Part Number description Module 2: CMOS FEOL Analysis Manufacturer Device # 2 Some of the information is this report may be covered by patents, mask and/or copyright protection. This report
More informationRenesas Electronics, 2 IBM at Albany Nanotech, 3 IBM T. J. Watson Research Center, 4 IBM Microelectronics, and 5 GLOBALFOUNDRIES
Effective Cu Surface Pre-treatment for High-reliable 22nmnode Cu Dual Damascene Interconnects with High Plasma Resistant Ultra Low-k Dielectric (k=2.2) F. Ito 1, H. Shobha 2, M. Tagami 1, T. Nogami 2,
More information200mm Next Generation MEMS Technology update. Florent Ducrot
200mm Next Generation MEMS Technology update Florent Ducrot The Most Exciting Industries on Earth Semiconductor Display Solar 20,000,000x reduction in COST PER TRANSISTOR in 30 years 1 20x reduction in
More informationMetallization. Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance
Metallization Interconnects Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance RC time delay Inter-Metal Dielectric -Prefer low dielectric constant to reduce capacitance
More informationMetallization deposition and etching. Material mainly taken from Campbell, UCCS
Metallization deposition and etching Material mainly taken from Campbell, UCCS Application Metallization is back-end processing Metals used are aluminum and copper Mainly involves deposition and etching,
More informationMetallization. Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance
Metallization Interconnects Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance RC time delay Inter-Metal Dielectric -Prefer low dielectric constant to reduce capacitance
More informationALD and CVD of Copper-Based Metallization for. Microelectronic Fabrication. Department of Chemistry and Chemical Biology
ALD and CVD of Copper-Based Metallization for Microelectronic Fabrication Yeung Au, Youbo Lin, Hoon Kim, Zhengwen Li, and Roy G. Gordon Department of Chemistry and Chemical Biology Harvard University Introduction
More informationAtomic Layer Deposition(ALD)
Atomic Layer Deposition(ALD) AlO x for diffusion barriers OLED displays http://en.wikipedia.org/wiki/atomic_layer_deposition#/media/file:ald_schematics.jpg Lam s market-leading ALTUS systems combine CVD
More informationAtomic Layer Deposition of Novel High Dielectric Constant Materials
Atomic Layer Deposition of Novel High Dielectric Constant Materials Adam Kueltzo # & Julie Lam * Thornton Fractional North High School # and Maine East High School * August 2, 2007 University of Illinois
More informationProcese de depunere in sistemul Plasma Enhanced Chemical Vapor Deposition (PECVD)
Procese de depunere in sistemul Plasma Enhanced Chemical Vapor Deposition (PECVD) Ciprian Iliescu Conţinutul acestui material nu reprezintă in mod obligatoriu poziţia oficială a Uniunii Europene sau a
More informationState of the art quality of a GeOx interfacial passivation layer formed on Ge(001)
APPLICATION NOTE State of the art quality of a Ox interfacial passivation layer formed on (001) Summary A number of research efforts have been made to realize Metal-Oxide-Semiconductor Field Effect Transistors
More informationEffect of barrier layers on the texture and microstructure of Copper films
Mat. Res. Soc. Symp. Proc. Vol. 766 2003 Materials Research Society E2.2.1 Effect of barrier layers on the texture and microstructure of Copper films Tejodher Muppidi and David P Field School of MME, Washington
More informationIntegrated Process Technology Development for the sub 7nm Era
Integrated Process Technology Development for the sub 7nm Era July 12, 2017 Alex Oscilowski President TEL Technology Center, America, LLC. TEL s Global R&D Operations Korea U.S. imec (Belgium) TEL Technology
More informationLecture 4. Oxidation (applies to Si and SiC only) Reading: Chapter 4
Lecture 4 Oxidation (applies to Si and SiC only) Reading: Chapter 4 Introduction discussion: Oxidation: Si (and SiC) Only The ability to grow a high quality thermal oxide has propelled Si into the forefront
More informationElectroless CoWP Boosts Copper Reliability, Device Performance Bill Lee, Blue29, Sunnyvale, Calif. -- 7/1/2004 Semiconductor International
More information
TSV Interposer Process Flow with IME 300mm Facilities
TSV Interposer Process Flow with IME 300mm Facilities Property of Institute of Microelectronics (IME)-Singapore August 17, 2012 Outline 1. TSV interposer (TSI) cross sectional schematic TSI with BEOL,
More informationTSV Formation: Drilling and Filling
3D Architectures for Semiconductor Integration and Packaging (3D ASIP), Burlingame, CA, Dec. 10-12, 2014 Preconference symposium- 3D Integration: 3D Process Technology TSV Formation: Drilling and Filling
More informationSemiconductor Manufacturing Technology. Semiconductor Manufacturing Technology
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 11 Deposition Film Layers for an MSI Era NMOS Transistor Topside Nitride Pre-metal oxide Sidewall
More informationFigure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.
Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed
More informationSemiconductor Manufacturing Technology. IC Fabrication Process Overview
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you
More informationPost CMP Cleaning SPCC2017 March 27, 2017 Jin-Goo Park
Post CMP Cleaning Conference @ SPCC2017 March 27, 2017 Jin-Goo Park Challenges in surface preparation Research trend in cleaning technology Lesson learned from current cleaning technology Challenges in
More informationEE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
More informationMemory Devices. Ki-Nam Kim, President, Institut of Technology Samsung Electronics, 2010 IEDM, San Francisco.
Memory Devices In Korea now, Samsung : 2010, 30nm 2Gb DDRS DRAM/DDR3 SRAM 2011, Invest US $12 bil. for 20nm & SysLSI. Hynix : 2010, 26nm MLC- NAND Flash 2011, 30nm 4Gb DRAM At 2020, the demands of computing
More informationMARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices
Hitachi Review Vol. 57 (2008), No. 3 127 MARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices Tadashi Terasaki Masayuki Tomita Katsuhiko Yamamoto Unryu Ogawa, Dr. Eng. Yoshiki Yonamoto,
More informationEffect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate
Effect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate H. Park, M. Chang, H. Yang, M. S. Rahman, M. Cho, B.H. Lee*, R. Choi*,
More informationLITHOGRAPHY MATERIAL READINESS FOR HVM EUV TECHNOLOGY DANILO DE SIMONE
LITHOGRAPHY MATERIAL READINESS FOR HVM EUV TECHNOLOGY DANILO DE SIMONE EUV HISTORY AT IMEC OVER 10 YEARS OF EUV EXPOSURE TOOLS AT IMEC 2006-2011 2011-2015 2014 - present ASML Alpha-Demo tool 40nm 27nm
More informationTSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development
TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development Outline Why 3D Integration? TSV Process Variations Lithography Process Results Stacking Technology Wafer Bonding
More informationThe Red Brick Wall of Traditional Semiconductor Electronics
The Red Brick Wall of Traditional Semiconductor Electronics H. Jörg Osten Institute for Semiconductor Devices and Electronic Materials University of Hannover 150 Years of Electronics Edison Effect Lilienfeld
More informationFOR SEMICONDUCTORS 2009 EDITION
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION FRONT END PROCESSES THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS
More informationPortland Technology Development, * CR, # QRE, % PTM Intel Corporation
A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom,
More informationLecture 7 CMOS MEMS. CMOS MEMS Processes. CMOS MEMS Processes. Why CMOS-MEMS? Agenda: CMOS MEMS: Fabrication. MEMS structures can be made
EEL6935 Advanced MEMS (Spring 2005) Instructor: Dr. Huikai Xie CMOS MEMS Agenda: Lecture 7 CMOS MEMS: Fabrication Pre-CMOS Intra-CMOS Post-CMOS Deposition Etching Why CMOS-MEMS? Smart on-chip CMOS circuitry
More informationVertical Group IV Nanowires: Potential Enablers for 3D Integration and BioFET Sensor Arrays
Vertical Group IV Nanowires: Potential Enablers for 3D Integration and BioFET Sensor Arrays Paul C. McIntyre Department of Materials Science & Engineering Geballe Laboratory for Advanced Materials Stanford
More informationUltra High Barrier Coatings by PECVD
Society of Vacuum Coaters 2014 Technical Conference Presentation Ultra High Barrier Coatings by PECVD John Madocks & Phong Ngo, General Plasma Inc., 546 E. 25 th Street, Tucson, Arizona, USA Abstract Silicon
More informationLaser Spike Annealing for sub-20nm Logic Devices
Laser Spike Annealing for sub-20nm Logic Devices Jeff Hebb, Ph.D. July 10, 2014 1 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014 Outline Introduction Pattern Loading Effects LSA Applications
More informationSupplementary Figure S1 Crystal structure of the conducting filaments in sputtered SiO 2
Supplementary Figure S1 Crystal structure of the conducting filaments in sputtered SiO 2 based devices. (a) TEM image of the conducting filament in a SiO 2 based memory device used for SAED analysis. (b)
More information3D technologies for integration of MEMS
3D technologies for integration of MEMS, Fraunhofer Institute for Electronic Nano Systems Folie 1 Outlook Introduction 3D Processes Process integration Characterization Sample Applications Conclusion Folie
More informationPlasma-Enhanced Chemical Vapor Deposition
Plasma-Enhanced Chemical Vapor Deposition Steven Glenn July 8, 2009 Thin Films Lab 4 ABSTRACT The objective of this lab was to explore lab and the Applied Materials P5000 from a different point of view.
More informationHYPRES. Hypres MCM Process Design Rules 04/12/2016
HYPRES Hypres MCM Process Design Rules 04/12/2016 Direct all inquiries, questions, comments and suggestions concerning these design rules and/or HYPRES fabrication to: Daniel T. Yohannes Tel. (914) 592-1190
More informationAdvanced CMOS Process Technology Part 3 Dr. Lynn Fuller
MICROELECTRONIC ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY Part 3 Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee Electrical and Microelectronic Engineering Rochester Institute of Technology 82
More informationAdvanced developer-soluble gap-fill materials and applications
Advanced developer-soluble gap-fill materials and applications Runhui Huang, Dan Sullivan, Anwei Qin, Shannon Brown Brewer Science, Inc., 2401 Brewer Dr., Rolla, MO, USA, 65401 ABSTRACT For the via-first
More informationAlternative Methods of Yttria Deposition For Semiconductor Applications. Rajan Bamola Paul Robinson
Alternative Methods of Yttria Deposition For Semiconductor Applications Rajan Bamola Paul Robinson Origin of Productivity Losses in Etch Process Aggressive corrosive/erosive plasma used for etch Corrosion/erosion
More informationAnnual Meeting. North Carolina State University Dr. Veena Misra. January 17 19, 2017 December
Annual Meeting North Carolina State University Dr. Veena Misra January 17 19, 2017 December 8 2015 1 Misra Group at NCSU Over 9 years experience in wide band gap research on SiC, GaN and Ga2O3. World leaders
More informationAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment
Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment Editors: E. P. Gusev Qualcomm MEMS Technologies San Jose, California, USA D-L. Kwong
More informationMOS Gate Dielectrics. Outline
MOS Gate Dielectrics Outline Scaling issues Technology Reliability of SiO 2 Nitrided SiO 2 High k dielectrics 42 Incorporation of N or F at the Si/SiO 2 Interface Incorporating nitrogen or fluorine instead
More informationSEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy
SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy Jun-Mo Yang, Ph.D. Measurement & Analysis Team National NanoFab Center, Korea Introduction
More informationPrecursors with Metal-Nitrogen Bonds for ALD of Metals, Nitrides and Oxides
Precursors with Metal-Nitrogen Bonds for ALD of Metals, Nitrides and Oxides Abstract Roy Gordon Gordon@chemistry.harvard.edu, Cambridge, MA To achieve ALD s unique characteristics, ALD precursors must
More informationDevice and Process Variability
IEEE SCV-SF Electron Devices Society Seminar Device and Process Variability Tomasz Brozek PDF Solutions Inc.. Santa Clara, 12 June 2017 Outline Why does it matter Impact on parametric yield, speed, leakage
More informationIBM Research Report. Hyungjun Kim IBM Research Division Thomas J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
RC22737 (W0303-012) March 5, 2003 Materials Science IBM Research Report Atomic Layer Deposition of Metal and Nitride Thin films: Current Research Efforts and Applications for Semiconductor Device Processing
More informationMaterials Characterization for Stress Management
Materials Characterization for Stress Management Ehrenfried Zschech, Fraunhofer IZFP Dresden, Germany Workshop on Stress Management for 3D ICs using TSVs San Francisco/CA, July 13, 2010 Outline Stress
More informationA New Liquid Precursor for Pure Ruthenium Depositions. J. Gatineau, C. Dussarrat
1.1149/1.2727414, The Electrochemical Society A New Liquid Precursor for Pure Ruthenium Depositions J. Gatineau, C. Dussarrat Air Liquide Laboratories, Wadai 28, Tsukuba city, Ibaraki Prefecture, 3-4247,
More informationEtching Mask Properties of Diamond-Like Carbon Films
N. New Nawachi Diamond et al. and Frontier Carbon Technology 13 Vol. 15, No. 1 2005 MYU Tokyo NDFCT 470 Etching Mask Properties of Diamond-Like Carbon Films Norio Nawachi *, Akira Yamamoto, Takahiro Tsutsumoto
More informationAmorphous Oxide Transistor Electrokinetic Reflective Display on Flexible Glass
Amorphous Oxide Transistor Electrokinetic Reflective Display on Flexible Glass Devin A. Mourey, Randy L. Hoffman, Sean M. Garner *, Arliena Holm, Brad Benson, Gregg Combs, James E. Abbott, Xinghua Li*,
More informationenabling tomorrow s technologies CVD Production Systems for Industrial Coatings powered by
enabling tomorrow s technologies CVD Production Systems for Industrial Coatings powered by www.cvdequipment.com Equipment Design, Engineering, and Manufacturing Thin film deposition systems for industrial
More informationNew Applications for CMP: Solving the Technical and Business Challenges. Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009
New Applications for CMP: Solving the Technical and Business Challenges Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009 Outline Background and Business Climate for CMP Technical Approach
More informationNeedham Growth Conference. January 2007 NYC
Needham Growth Conference January 2007 NYC 1 Safe Harbor Statement This presentation contains forward-looking statements. These forward-looking statements are just predictions subject to risks and uncertainties
More informationThin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high vacuum ~10-7 torr Removes residual gases eg oxygen from
More informationLecture 22: Integrated circuit fabrication
Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................
More informationBack End Processing (BEP) Needs Statement
Back End Processing (BEP) Needs Statement I. Introduction- The purpose of this document is to define the needs of the SRC member companies in the area of Back End Processes (BEP), and to highlight specific
More information"Plasma CVD passivation; Key to high efficiency silicon solar cells",
"Plasma CVD passivation; Key to high efficiency silicon solar cells", David Tanner Date: May 7, 2015 2012 GTAT Corporation. All rights reserved. Summary: Remarkable efficiency improvements of silicon solar
More informationCMP Solutions for 10nm and Beyond: Breaking trade-offs in the Planarization / Defect Balance
SMC Korea May 18, 2016 CMP Solutions for 10nm and Beyond: Breaking trade-offs in the Planarization / Defect Balance Marty W. DeGroot Global R&D Director, CMP Technologies, The Dow Chemical Company Key
More informationLecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1
Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 LECTURE 030 INTEGRATED CIRCUIT TECHNOLOGY - I (References [7,8]) Objective The objective of this presentation is: 1.) Illustrate integrated
More informationp. 57 p. 89 p. 97 p. 119
Preface Program Committee Members Transistor Physics History John Bardeen and Transistor Physics p. 3 Challenges p. xiii p. xv Technology in the Internet Era p. 33 Metrology Needs and Challenges for the
More informationModeling of Local Oxidation Processes
Introduction Isolation Processes in the VLSI Technology Main Aspects of LOCOS simulation Athena Oxidation Models Several Examples of LOCOS structures Calibration of LOCOS effects using VWF Field Oxide
More informationFlexible functional devices at mass production level with the FLEx R2R sald platform
Flexible functional devices at mass production level with the FLEx R2R sald platform D. Spee, W. Boonen, D. Borsa and E. Clerkx Meyer Burger (Netherlands) B.V. Meyer Burger Introduction to sald Challenges
More informationOverview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA
Overview of CMP for TSV Applications Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA Outline TSV s and the Role of CMP TSV Pattern and Fill TSV Reveal (non-selective)
More informationULSI Devices: Current Status and Future Prospects of Research and Development
Hitachi Review Vol. 56 (2007), No. 3 25 ULSI Devices: Current Status and Future Prospects of Research and Development Dai Hisamoto, Dr. Eng. Nobuyuki Sugii, Dr. Eng. Kazuyoshi Torii, Dr. Eng. Akio Shima
More informationSupporting Information
Supporting Information Fast-Response, Sensitivitive and Low-Powered Chemosensors by Fusing Nanostructured Porous Thin Film and IDEs-Microheater Chip Zhengfei Dai,, Lei Xu,#,, Guotao Duan *,, Tie Li *,,
More informationDevelopment of different copper seed layers with respect to the copper electroplating process
Microelectronic Engineering 50 (2000) 433 440 www.elsevier.nl/ locate/ mee Development of different copper seed layers with respect to the copper electroplating process a, a a b b b K. Weiss *, S. Riedel,
More informationMaterials Characterization
Materials Characterization C. R. Abernathy, B. Gila, K. Jones Cathodoluminescence (CL) system FEI Nova NanoSEM (FEG source) with: EDAX Apollo silicon drift detector (TE cooled) Gatan MonoCL3+ FEI SEM arrived
More informationUltra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes
Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Andrew Strandjord, Thorsten Teutsch, and Jing Li Pac Tech USA Packaging Technologies, Inc. Santa Clara, CA USA 95050 Thomas Oppert, and
More informationMicro-fabrication and High-productivity Etching System for 65-nm Node and Beyond
Hitachi Review Vol. 55 (2006), No. 2 83 Micro-fabrication and High-productivity Etching System for 65-nm Node and Beyond Takashi Tsutsumi Masanori Kadotani Go Saito Masahito Mori OVERVIEW: In regard to
More informationCapital / MRKT CAP \6.14B / \280.6B (as of May 12 th ) Chugeri, Yangji myun, Cheoin gu, Yongin, Kyunggi do, Korea
Company name Established 05 JAN, 2000 Eugene Technology Co., Ltd. CEO Pyung Yong Um Capital / MRKT CAP \6.14B / \280.6B (as of May 12 th ) Address Main Products Home Page 209-3 Chugeri, Yangji myun, Cheoin
More informationEvaluation of Cu Pillar Chemistries
Presented at 2016 IMAPS Device Packaging Evaluation of Cu Pillar Chemistries imaps Device Packaging Conference Spring 2016 Matthew Thorseth, Mark Scalisi, Inho Lee, Sang-Min Park, Yil-Hak Lee, Jonathan
More information1 Thin-film applications to microelectronic technology
1 Thin-film applications to microelectronic technology 1.1 Introduction Layered thin-film structures are used in microelectronic, opto-electronic, flat panel display, and electronic packaging technologies.
More informationFabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical Vapor Deposition
Mat. Res. Soc. Symp. Proc. Vol. 784 2004 Materials Research Society C7.7.1 Fabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical
More informationSchottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers
Schottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers Yoshihisa Ohishi 1, Kohei Noguchi 1, Kuniyuki Kakushima 2, Parhat Ahmet 1, Kazuo Tsutsui 2, Nobuyuki Sugii
More informationEnabling Tool and Process Technologies for Advanced Devices
Enabling Tool and Process Technologies for Advanced Devices June 26 th, 2012 Tokyo Gert Leusink TEL Technology Center America, LLP 1 Outline Emerging Technologies and SPE needs Process and Integration
More informationTechnology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS
INTRODUCTION TO Semiconductor Manufacturing Technology SECOND EDITION Hong Xiao TECHNISCHE INFORMATIONSBiBUOTHEK UNIVERSITATSBIBLIOTHEK HANNOVER SPIE PRESS Bellingham,Washington USA Contents Preface to
More informationSelective Vapor Deposition
Selective Vapor Deposition The Harvard community has made this article openly available. Please share how this access benefits you. Your story matters. Citation Accessed Citable Link Terms of Use Gordon,
More informationA Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon
A Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon April 2009 A Deep Silicon RIE Primer 1.0) Etching: Silicon does not naturally etch anisotropically in fluorine based chemistries. Si
More informationFORMING-FREE NITROGEN-DOPED ALUMINUM OXIDE RESISTIVE RANDOM ACCESS MEMORY GROWN BY ATOMIC LAYER DEPOSITION TECHNIQUE A DISSERTATION
FORMING-FREE NITROGEN-DOPED ALUMINUM OXIDE RESISTIVE RANDOM ACCESS MEMORY GROWN BY ATOMIC LAYER DEPOSITION TECHNIQUE A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE
More informationSurface Preparation and Cleaning Conference April 19-20, 2016, Santa Clara, CA, USA. Nano-Bio Electronic Materials and Processing Lab.
Surface Preparation and Cleaning Conference April 19-20, 2016, Santa Clara, CA, USA Issues on contaminants on EUV mask Particle removal on EUV mask surface Carbon contamination removal on EUV mask surface
More informationA Spacer Patterning Technology for Nanoscale CMOS
436 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002 A Spacer Patterning Technology for Nanoscale CMOS Yang-Kyu Choi, Tsu-Jae King, Member, IEEE, and Chenming Hu, Fellow, IEEE Abstract
More informationReactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge
Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge R. Chanson a, E. Pargon a, M. Darnon a, C. Petit Etienne a, S. David a, M. Fouchier a, B. Glueck b, P. Brianceau
More informationPoint-contacting by Localised Dielectric Breakdown: A new approach for contacting solar cells
Point-contacting by Localised Dielectric Breakdown: A new approach for contacting solar cells SPREE Public Seminar 20 th February 2014 Ned Western Supervisor: Stephen Bremner Co-supervisor: Ivan Perez-Wurfl
More information