Wafer Level Packaging

Transcription

1 1 IEEE CPMT Meeting, San Jose, CA Wafer Level Packaging L. Nguyen National Semiconductor Corp. Santa Clara, CA Acknowledgments: N. Kelkar, V. Patwardhan, C. Quentin, H. Nguyen, A. Negasi, E. Warner Feb-02 1 What is a WLP? Significant confusion in the industry over the term wafer-level packaging Simple definition: All packaging and interconnection must be fabricated on the wafer prior to dicing Bumped chips are WLP? Differentiation: Are the devices packaged further prior to assembly? High I/O µps and ASICs: chips are mounted on chip carriers before surface mount attachment Not WLPs Small die and/or die with low I/O can be mounted directly on the final substrate WLPs Feb-02 2

2 2 Outline CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Feb-02 3 CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Outline Feb-02 4

3 3 Package Forecast 308+ I/O RANGE UNITS (M) Feb-02 Source: Electronic Trend 5 Publications 1999 Flip Chip Packages 1000 Definitions UNITS (M) FCOB FCOO BGA FC CSP FC MCM FC YEAR Direct Attach FCOB - Flip Chip on Board FCOO - Flip Chip on Other In Package BGA FC - FC in BGA CSP FC - FC in CSP (includes WL-CSP) MCM FC - FC in MCM Source: Electronic Trend Feb-02 Publications

4 4 WLP Growth Projections 8-in WAFER EQUIVALENT Source: Electronic Trend Publications High Low Total Packages YEAR Feb-02 7 Source: TechSearch 2001 Form Factor Migration STANDARD < 208 lead TO SOP MSOP SOT SC70 PDIP SOIC TSSOP CSP CSP (Leaded/Laminate) (Wafer) PLCC QFP TQFP CSP > 208 lead PGA BGA BGA FP-BGA (1.27 mm) (1.0 mm) (0.8 mm) POWER TO220 DPAK, D2PAK, TO263 PACKAGE ENHANCEMENTS THERMAL Embedded heat slug Drop-in HS Exposed DAP Shorted leads MQFP ELECTRICAL Aluminum nitride EMC Shorter leads Shorter wire bond Exposed DAP Solder bumps Multiple wires OPTICAL LCC Pre-molded CSP Custom Custom Custom Feb-02 8

5 5 Outline CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Feb-02 9 CSP Migration toward Wafer Level Packaging CSP applications are rapidly expanding with drivers in Flash memory RAMBUS DRAM Analog Evolution of CSP technology toward Wafer Level Packaging due to the following factors: Batch fabrication of ICs in arrays Test and burn-in in strip and array format; strip format has continuously increased in manufacturing for higher throughput Adaptability of some configurations to wafer level processing more than others (e.g., possibility for die shrink) Emergence of 0.5 mm pitch as the standard for CSPs in memory, µps, DSPs, ASICs, and most consumer products Feb-02 10

6 6 CSP for Portable Application 1 Other applications: Game Gear, Play Station, Portable Computers, etc.. Feb CSP for Portable Application 2 Casio Color Wristwatch/Camera (CPU in RealCSP by IEP Technologies) Handspring Visor Edge (Integrated passive devices in Ultra CSP) Feb-02 12

7 7 Benefits of WL-CSP Wafer Level-CSP can provide the following benefits: Batch processing to lower costs Handling and shipping logistics can be streamlined Final test is done at the wafer level. Savings in test and logistics can be equally, or more important, than the manufacturing cost of the package ICs can be packaged in the fab and shipped directly to customers for surface mounting with conventional SMT; shortens TAT; lower assembly capital costs Ability to minimize inventory No need for Known Good Die - tested like other ICs Functionality can be packed into a form factor as small as the die Wider pitch allows for wider UBM, taller bumps, and better joint reliability Feb CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Outline Feb-02 14

8 8 Barriers and Challenges Like any other new technologies, WL-CSP still faces a number of hurdles... Infrastructure is not quite established Wafer bumping is still too costly High cost for poor yield wafers High cost for low wafer bumping yields Who should manufacture the WL-CSP (IC or bumping house) Die shrink strategy Solder joint reliability is more critical (since underfill may not be used in the application) Feb Users of WL-CSPs USA FCD, Unitive, MCNC, Dallas Semi (1wire), Xicor (Shell BGA, Ultra CSP), National Semi (micro SMD), Atmel, CMD (Ultra CSP), Alpine Micro Systems (WALEP), TI (NanoStar) Europe TU Berlin, IMEC, CS2 Taiwan Apack, Unitive Taiwan, ASE, SPIL, Chipbond, ShellCase (Xintec) Korea Amkor, Hyundai Japan IEP/Oki/Casio (Real CSP) Fujitsu/Shinko (Super CSP) Hitachi (WPP2) Feb-02 16

9 9 Outline CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Feb Micro SMD Micro SMD is a Wafer Level-Chip Scale Package No interposer - the die is the package Micro SMD has the following advantages: No need for underfill (although some OEMs use underfills for certain applications such as portable consumer products) Smallest footprint per I/O - savings in PCB estate Leverage standard surface mount assembly technology Cost-effective manufacturing and assembly Matrix interconnect layout designed at 0.5 mm pitch 0.9 mm maximum package height Epoxy backcoating provides conventional black marking surfaces Feb-02 18

10 10 Package Construction MSOP-8 3 mm 5 mm 5 mm 1.5 mm 1.5 mm SMT PACKAGE TYPE Micro SMD: 4, 5, 8, and 14 I/O Comparison between various SMT 0.5 mm pitch; JEDEC Standard MO TSSOP-14 MSOP-8 SOT23-5 SC70-5 microsmd-8 packages and the micro SMD Feb Package Construction Cross-section of an 8 I/O micro SMD bonded to an organic substrate Cross-section of a solder ball Feb-02 20

11 11 Outline CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Feb Process Flow Incoming wafer 2 nd passivation Bumping Back side coating Laser mark Test (Wafer sort) Saw Tape and reel Feb-02 22

12 12 micro SMD Wafer Fab Assembly Flows Conventional Package PQFP & TSSOP Wafer Fab CSP Wafer Fab Solder Bumping Backside Coating Marking Final Test Wafer Sort Saw Die Attach Wire Bond Wafer Sort Saw Die Attach Plasma Clean Saw Tape & Reel 5 process steps 1 test step Mold Lead Plating Trim & Form Final Test Mark Tray / Tape & Reel 7 process steps 2 test steps Wire Bond Laser Mark Final Singulated Test Tape & Reel Feb Mold Saw 7 process steps 2 test steps CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Outline Feb-02 24

13 13 Package Selection WL-CSPs will replace traditional perimeter leaded packages: Initially targets low pin count memory and analog devices; growth highest in wireless portable applications where small form factor and weight are crucial factors Growth relies on the existing assembly infrastructure Criteria for choosing from the many CSP versions? From IC supplier: Reduced TAT, inventory size, cost reduction from transportation and logistics simplification, manufacturability, and scaleability From user: Cost, electrical performance, thermal performance, manufacturability (assembly), and reliability Feb Package Selection Pin Count TSSOPs MSOPs SOTs Laminate CSP L/F based CSP (.5/.65 mm) micro SMD Year Feb-02 26

14 14 Junction Temperature ( o C/W) layer 0.5 W Package Selection 2-layer 0.5 W 1-layer 1.0 W with 50x50 mm Cu enhancement 2-layer 0.7 W MSOP SOT LLP micro SMD (Thermal) Thermal performance comparison of 8-lead MSOP, SOT, LLP, and micro-smd Feb Package Selection (Manufacturability - PCB Layout) Both non-solder mask defined (NSMD) and solder mask defined (SMD) layouts possible Prefer NSMD for (1) tighter control on copper etch process, (2) minimal stress concentration, and (3) ease of trace routing Recommend 0.5 oz (12 to 15 µm) top layer copper thickness Internal reliability data collected with NSMD design, 0.5 oz copper and OSP lead finish For Au finish recommend to limit Au flash thickness < 0.5 µm NSMD Micro SMD 8 bump package footprint Feb All dimensions are in microns Solder Mask Copper Pad Substrate Copper pad PCB Solder mask SMD

15 15 Package Selection (Manufacturability - Solder Paste Printing) Recommend laser cut process followed by electro-polish to ensure tapering aperture walls to facilitate paste release. Recommend aperture mm X mm square on a mm thick laser cut + electro-polished stencil Type 3 or finer solder paste is recommended With recommended stencil parameters a vertical standoff of mm in the final assembly can be achieved Feb Micro SMD 8 bump stencil layout Stencil aperture R 50 All dimensions are in microns Stencil Package Selection (Manufacturability - Pick & Place) Micro SMD can be placed using standard SMT placement m/c Part silhouette or bump recognition can be used to position micro SMD Micro SMD aligns with land pattern by self-aligning of flip chip solder joints Component placement height for the micro SMD should be compensated for its thickness such that minimal force (< 50 gm/bump) is exerted on it when comes in contact with the PCB Micro SMD can be assembled without solder paste (flux only) in case of rework procedure Feb Y-Offset (um) Offset O - Self Aligned X - Not Aligned SMT Process Envelope Flip-Chip Process Envelope X-Offset (um) Platforms used: Fuji CP60, CP3; Amistar PlacePro 5800; ESEC Micron 2; Siemens; Universal GSM

16 16 Package Selection (Manufacturability - Solder Reflow) Micro SMD is assembled using standard reflow process Thermal profile at specific board locations is determined Recommend Nitrogen purge during solder reflow operation The micro SMD is qualified for up to three reflow operations (J- STD-020) Rated max peak temperature = 260 C for < 30 sec Depending on the type of flux used assembly may be cleaned Reflow Furnace: Heller 1700 N 2 Capable Feb Package Selection (Manufacturability - Rework) Rework process similar to a standard BGA or CSP part Rework process duplicates the original reflow profile Automated re-work developed using OK International s BGA Rework System (includes localized convection heating with profiling capability, bottom-side pre-heater, and part placer with image overlay alignment) Manual rework is possible using soft tip high temperature pick-up tool (e.g. tweezers, vacuum wand) and hot vacuum / air gun A Successful Rework Process for Chip-Scale Pack-ages, Paul Wood, OK International, Chip Scale Review, Vol. 2, No. 4, Feb-02 32

17 17 WL-CSP Failure Modes Al Pad Passivation PI UBM High Lead Eutetic Solder Mask Cu Pad Die PCB NPEU PIHL NPHL PIEU Failure Locations Eutectic bump w/o PI showed Al pad peeled off from die and cratering PI showed no significant effect on high lead PIEU with 3 mil stand-off showed 50% cumulative failure rate at 550X High lead deformed much greater than eutectic solder Feb Failure Locations No PI + Eutectic (Al Pad Peel Off) PI + Eutectic (Joint Failed at PCB) No PI + High Lead (Failed at Intermetallic) PI + High Lead (Failed at High Lead) Feb-02 34

18 18 Failure Mechanisms Material Substrate CTE Device Solder mask Effect of Manufacturing Variables Process Bumping Passivation High Pb CTE/E Underfill Adhesion Time Dependent Creep Deformation Temperature Cycle Loading Solder Eutectic Time Independent Plastic Deformation Thermal Shock Encapsulation Wetting Voids Underfill Voids Solder Joint Size Substrate Silicon Thickness Geometry Solder Joint Fatigue Life Height Cap Dia Feb DNP Cause and Effect for Solder Joint Fatigue CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Outline Feb-02 36

19 19 Development of Pb-Free Solders (Ternary Systems) SYSTEM KNOWN COMPOSITIONS T m ( o C) Sn-Ag-Bi 91.8Sn/3.4Ag/4.8Bi (E) Sn/3.3Ag/4.7Bi Sn1Ag/56Bi (E) Sn/2.5Ag/14Bi Sn/2Ag/4Bi Sn/1.5Ag/6Bi SYSTEM KNOWN COMPOSITIONS T m ( o C) Sn-Ag-Zn 95.5Sn/3.5Ag/1Zn 217 Sn-Bi-In 70Sn/20Bi/10In Sn/10Bi/10In Sn-Ag-In Sn-Ag-Cu 88.0Sn/3.2Ag/8.8In Sn/4.1Ag/12In Sn/2.8Ag/20In Sn/4.7Ag/1.7Cu (E) Sn/1.25Ag/2Cu Sn/0.5Ag/3Cu Sn/0.35Ag/4Cu Sn/1.25 Ag/4Cu Sn-Bi-Sb 75Sn/19Bi/6Sb Sn-Bi-Zn 78Sn/16Bi/6Zn Sn/57Bi/1.3In 127 Sn-Cu-In 75Sn/ Cu/0.01-6In/addition Feb Consortia Recommendations NCMS: 96.5Sn/3.5Ag; 91.7Sn/3.5Ag/4.8Bi; 42Sn/58Bi NEMI: Sn/Ag/Cu without Bi is best in reliability ( o C) Brite Euram: 95.5Sn/3.8Ag/0.7Cu (for general purpose soldering); 99.3Sn/0.7Cu; 96.5Sn/3.5Ag; Sn/Ag/Bi Germany: 96.5Sn/3.5Ag; 99Sn/1Cu UK (Department of Trade & Industry): options depend on the applications: automotive/military Sn/Ag/Cu(Sb) industrial/telecoms Sn/Ag/Cu, Sn/Ag consumer Sn/Ag/Cu(Sb), Sn/Ag, Sn/Cu, Sn/Ag/Bi Japan Electronics Industry Development Association: Sn/Ag/Cu (before Pb-free components available) Sn/Ag/Bi (after Pb-free components available) Feb-02 38

20 20 Micro SMD Adoption Path B: Sn/Ag/Cu P: Sn/Pb B: Sn/Ag/Cu P: Sn/Ag/Cu B: Sn/Pb P: Sn/Ag/Cu Sn/Ag/Cu Sn/Pb Bump Paste Sn/Pb Sn/Ag/Cu 220 o C 260 o C 260 o C 220 o C 260 o C 220 o C B: Sn/Ag/Cu P: Sn/Pb B: Sn/Pb P: Sn/Ag/Cu B: Sn/Pb P: Sn/Pb Best solder joint performance results with homogeneous combination of lead-free solder. Standard Sn/Pb packages can be mounted with lead-free paste. Worst solder joint performance results with lead-free packages with Sn/Pb paste and Sn/Pb reflow. Feb CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Outline Feb-02 40

21 21 Wafer Level Underfill Bottom View - Micro SMD 8 I/O with Wafer Level Underfill Top View - Micro SMD 8 I/O with Wafer Level Underfill is assembled on PCB Side View - Micro SMD 8 I/O Over View - Micro SMD 8 I/O with with Wafer Level Underfill Wafer Level Underfill Feb DEVICE Wafer Level Underfill State of the Art - Conventional Underfill Process Align and Place SUBSTRATE Solder Bump Reflow Underfill Dispense Process Flow 1. Align bumped device with substrate pads 2. Reflow assembly to create solder joint 3. Dispense underfill and flow under device 4. Cure underfill Underfill Cure Feb-02 42

22 22 Wafer Level Underfill State of the Art - Conventional Underfill Process Process Disadvantages 1. Slow minutes (for 6 mm die w/ 3mil gap) 2. Performed at device level - can be bottleneck 3. Lengthy cure (1-4 hours) - separate process 4. Sensitive to air entrapment (voids) Material Disadvantages 1. Thermoset materials - not reworkable 2. Material properties - often at odds w/ process requirements a. High filler loading - slows flow under die b. Low filler loading - susceptible to popcorning 3. Cure sensitive properties - short floor life 4. Solvent use can cause voiding or bubbling Feb Wafer Level Underfill State of the Art - Fast Flow Underfill Process Process Disadvantages Sensitive to material/device wetting characteristics Underfill of Test Chip Q with full array (13 mm die, 25 µm gap, 250 µm pitch) Material - Dexter FP4511 Underfill of Test Chip Q with mixed array (13 mm die, 25 µm gap, 200 µm & 400 µm pitches) Material - Dexter FP4511 Feb-02 44

23 23 Wafer Level Underfill State of the Art - Fast Flow Underfill Process Process Disadvantages Sensitive to air entrapment Small void formed during underfill of Test Chip Q (perimeter array) with Namics U8433 Large void formed during underfill of Test Chip Q (full array) with Dexter FP4511 Feb Wafer Level Underfill State of the Art - No Flow Underfill Process Process 1. Dispense underfill over entire bond area 2. Align and place die 3. Cure underfill DEVICE SUBSTRATE Underfill Dispense SUBSTRATE Align and Place Underfill Cure Feb-02 46

24 24 State of the Art - No Flow Underfill Process Process Disadvantages 1. Alignment difficult - bond pads covered 2. Underfill can be retained between solder ball and pad causing mechanical or electrical joint failure 3. Process still performed at package level 4. Susceptible to voiding 5. Potential to float die w/o accurate dispensing Material Disadvantages 1. High reliability materials still in R&D 2. Extremely high CTE (up to 80 ppm/k) 3. Potential for moisture absorption 4. Non-reworkable Wafer Level Underfill Feb Processing Issues Current Process Flow Proposed Process Flow a) Saw Wafer into Die a) Bumped and Coated wafer Underfill Screen Printing b) Assemble Die and Substrate Die c) Reflow Solder Apply heat d) Apply Underfill e) Cure Underfill Wafer Substrate Die Substrate Dispensing Needle Die flow Underfill Substrate Apply heat Die Wafer b) Gel Underfill Apply heat Wafer c) Saw Wafer into Die Wafer d) Assemble Die and Substrate Die Substrate e) Simultaneously Reflow Solder and Cure Underfill Apply heat Die High viscosity - material does not flow through the screen ahead of the squeegee and ruin the print resolution Pseudoplastic - material flows through the screen under high pressures exerted by the squeegee High solids - more efficient material transfer; thicker films; reduced waste Substrate Substrate Feb-02 48

25 25 a)no stress at gel temperature Coating - Large CTE Processing Issues Wafer Die Wafer - Small CTE b)shrinkage at ambient temperature Coating Large Shrinkage Coating Wafer Stress on Wafer Small Shrinkage c)stress at ambient temperature No contact between solder ball and pad Stress-Induced Warpage Wafer curvature - planarity is critical to the dicing process. Caused by CTE mismatch between soft cured underfill and the silicon wafer. Primary factors: wafer thickness, film thickness, modulus of wafer, modulus of film, type of coating (e.g., blanket vs. patterned). Substrate Feb Processing Issues Wafer Warpage - Wafer: 200 mm (8 ) - Nominal thickness: 0.77 mm - Underfill coating: 0.11 mm (4 mils) - Two underfills: 1 and 10 GPa Curvature can reach 0.2x (E=1 GPa) to 2.6X (E=10 GPa) of a 200 mm wafer nominal thickness NORMALIZED CURVATURE COATING PATTERN Feb-02 50

26 26 Processing Issues Underfill Wafer Tape Hub Blade Kerf Negligible impact die edges Irregular kerf width/blade loading Reflow of material into kerf Film delamination Dicing-Induced Damage Potential problems encountered during krpm Chipping: minimal on coated side; potentially high on back side. Blade loading: accelerated blade wear / life; irregular cut widths; heat generated caused melting of the material into the kerf. Film delamination: poor adhesion accentuated by the shearing of the wafer. Feb Initial State At Temperature T Final State Processing Issues Silicon die Underfill Substrate Solder Wetting Under Constrained Conditions Wetting of solder pad - potentially poor / incomplete pad wetting due to the presence of the underfill surrounding the solder balls. Primary factors: surface tension of underfill / solder, weight of die, external force, coating thickness. Feb-02 52

27 27 Outline CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Feb Conclusions WL-CSP is driven by imperatives such as: Packaging cost Production, handling, and testing logistics Functionality, performance, size, and weight Integration and interconnect density WL-CSP such as the micro SMD is highly suitable for low pin count analog applications (cellular phones, cameras, flash minicards, portable products, etc.) Criteria for selection of a particular form factor and pin count will depend on both IC suppliers and end customers readiness Next advances in lead-free and wafer level underfill Feb-02 54

28 28 Outline CSP packaging trends CSP migration toward wafer level processing WL-CSP barriers and challenges micro SMD package construction Process / assembly flows Package selection criteria Future developments Lead-free Wafer level underfill Conclusions References Feb References General WLP books/articles: TechSearch CSP/BGA Update Service Prismark (market research, trends) Electronic Trend Publications (market research, trends) IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, May 2000 issue. Wafer Level Packaging Has Arrived, P. Garrou, Semiconductor International, pp , October Chip Scale Packaging, J. Lau and S. W. R. Lee, Eds., McGraw Hill (1999). Wafer Pre-Applied Encapsulant Materials and Processes, Q. Tong, S-H Hong, L. Nguyen, H. Nguyen, and A. Negasi, 52 nd Electron. Comp. & Tech. Conf., May 28-31, San Diego, CA (2002). Lead-free WL-CSP: Assembly and Reliability, V. Patwardhan, N. Kelkar, and L. Nguyen, 52 nd Electron. Comp. & Tech. Conf., May 28-31, San Diego, CA (2002). TC-18: Wafer Level Packaging Feb-02 56