High Density Packaging User Group International

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1 High Density Packaging User Group International BGA Reliability Characterization Project Temperature Cycling Tests Final Report David Love and David Towne Project Leaden Sun Microsystems Palo Alto, California. USA January 1999

2 BGA Reliability Characterization Project Temperature Cycling Tests Final Report ABSTRACT This paper describes the investigation into the effects of temperature cycling of solder joint connections on the board level for a variety of ball grid array packages (BGA). Variables studied were package construction, package location on the circuit board, solder joint location on the package, and virgin versus reworked boards. Temperature cycle evaluations were conducted with real-time event monitoring and failed sites were subjected to failure analysis to determine cause of failure. The BGA Reliability Characterization Project Team performed this work, as part of the BGA Reliability Characterization Project of the HDP User Group (High Density Packaging User Group). HDP User Group International, Inc. publishes this document as a convenience to those interested in information about BGA products. HDP User Group International, Inc. has not evaluated all particular products and cannot be responsible for error or omissions HDP User Group International, Inc. does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license or rights. HDP User Group International, Inc. accepts no liability for incidental or consequential damages arising from the use of any products. This disclaimer of warranty is in lieu of all warranties whether expressed, implied or statutory, including implied warranties of merchantability or fitness for a particular purpose. BGA Reliability Characterization Project Temperature Cycling Tests Final Report 2

3 INTRODUCTION The HDP User Group is an organization of semiconductor, materials and systems suppliers that are concerned with availability of semiconductor packages suited to high density applications. One of the first needs addressed by the HDP User Group was the second-level BGA reliability, or package-to-board reliability, with respect to temperature cycle stressing. The HDP User Group authorized a project to evaluate medium to long term second-level reliability of a variety of available BGA packages (both production-ready and in development). The project team was formed from several different companies. Packages of various constructions were obtained from member companies. These devices were mounted on printed circuit boards. Some of the boards were subjected to simulated rework conditions. All boards were then subjected to temperature cycle stressing, with real-time resistance monitoring. After 350 cycles, the boards were removed from temperature cycle testing and some of the devices were selected for failure analysis. PACKAGE CONSTRUCTION Four different packages were tested in this experiment. These constructions are detailed in Table 1, below. BGA1 Flip Chip BGA Table 1: Package Construction BGA3 TBGA, Tape Ball Grid Array 787 pins 352 pins 35 mm body 35 mm body Die size: 11.0 mm square Die size: 15.1 mm square 1.0 mm pitch 1.27 mm pitch Construction: eutectic flip chip balls, organic carrier, metal lid Construction: wire bond, metal/tape body, chip down, plastic encapsulated BGA2 Flex BGA BGA4 Super BGA 381 pins 352 pins 35 mm body 35 mm body Die size: 10.8 mm square 15.2 mm square 1.00 mm pitch 1.27 mm pitch Construction: wire bond, flex substrate, chin up, over molded body Wire bond, metal/organic laminate body, chip down, plastic encapsulated BGA Reliability Characterization Project Temperature Cycling Tests Final Report 3

4 PC BOARD CONSTRUCTION All boards used were FR4, 10 metal layers, with inch thickness. The devices were mounted on a single side. The finish has HASL (Hot Air Solder Leveling). The boards are 8.25 in. by 8.00 in. Eleven BGA components mounted on the board, for a total of 112 daisy chain nets per board. Figure 1 shows a photograph of the PC board, top level (BGA side). Figure 1 The component mounting pads were designed to have 1:1 diameter ratios with the pads on their respective packages. The pads on the PC board were non-solder mask defined (NSMD). ASSEMBLY Motorola Corporation performed assembly in Tempe, Arizona. The authors wish to express their thanks to Motorola who provided all stencils, tools, nozzles, direct labor, materials and testing for this project. The process flow for these devices is shown in Table 2. BGA Reliability Characterization Project Temperature Cycling Tests Final Report 4

5 Table 2 A total of nine boards were assembled. Placement of BGAs was automatic, using a Fuji F4G. Placement of connectors was performed manually. Paste used was No clean. The reflow profile is shown in Appendix 1. The connectors used were high-temp type and reflow compatible. SIMULATED REWORK Two of the nine boards were subjected to simulated rework conditions. All BGA devices on the simulated rework boards were cycled through the temperature profile twice, but were not removed from the boards. The simulated rework profile was four stages, including a preheat stage. There was a 40-second dwell at each stage, approximately 4 minutes per full cycle, including cooling. Maximum junction temperature was 220ºC. Maximum board temperature was 120ºC. TEST METHODOLOGY Prior to temperature cycle testing, the boards were subjected to a 60ºC bake for approximately 6 hours to drive out any moisture that may have accumulated. Following the pre-bake, five preconditioning cycles of -40ºC to +85ºC were completed. These cycle profiles included 15 minute rise and dwell times, for a total of 60 minutes per cycle (this was done to simulate a shipping environment). Following the preconditioning cycle, cable leads were hand-soldered to the board contacts for use in real-time resistance measurements during temperature cycling. Once harnessed the nets were all measured for baseline resistance. Prior to temperature cycle testing, the boards were temperature mapped and the data forwarded to Sun for approval. Temperature mapping was done by instrumenting the samples with thermocouples and placing the samples in the actual temperature cycling chamber. This was done to ensure that all devices received the same input temperature stimulus during the temperature cycle testing. Temperature cycling consisted of subjecting the harnessed and monitored samples to 3,500 cycles of temperature cycling. Each cycle lasted 40 minutes. The rise times and dwell times were each 10 BGA Reliability Characterization Project Temperature Cycling Tests Final Report 5

6 minutes. The temperature was cycled between 0ºC and 100ºC, as measured at the top surface of the packages. During temperature cycling, the nets of the samples were monitored for evidence of intermittent operations. This was done by plugging the harnessed samples into 2x256 channel Analysis Tech event detector. This equipment is capable of sensing increases in resistance of 100 ohms for periods of time greater than 200 nanoseconds. These increases in resistance (or events) were considered failures and flagged with respect to time, cycle number, and temperature. A log of the events was maintained. In addition to this in-situ, continuous event detection continuity monitoring, the nets of the samples were measured for electrical resistance every 500 cycles. The samples were thermally stabilized at the 100ºC temperature condition and electrical resistance measurements of the nets were made using 4-wire test apparatus. Board #78, a rework board, was pulled at 1,500 cycles in order to get some early F/A (Failure Analysis) results. The other ten boards were run for the full 3,500 cycles before being pulled out for final test and F/A. RESULTS A Weibull plot showing failure distribution is shown in Appendix 2. As can be seen, the Flip Chip BGA has a very different distribution from the other three packages tested. As will be discussed below, the Flip Chip BGA also had a different failure mode from the other three package constructions, specifically, failures in the chip-to-package solder joints. Regarding the other three BGA devices, given that the vast majority of each part type has not yet failed, the Weibull plots are nearly identical. The few early device failures do not affect the Weibull curve greatly given the numerous devices that have not yet failed upon testing completion. A second Weibull plot, comparing the results of virgin versus stimulated rework boards is shown in Appendix 3. In this case, the data from the Super BGA, TBGA and Flex BGA were combined in order to get a reasonable sample size. The justification for this approach is that the three devices had very similar failure distributions. The virgin and simulated rework boards have similar failure distributions and it is not clear from the data that there is any significant difference between the two samples. Again, the small number of early failures is dominated by the large number of devices that did not fail by the end of the test. FAILURE ANALYSIS: FLIP CHIP BGA A random sample of the failed devices was subjected to failure analysis (F/A). F/A consisted of the following process flow. Probe with ohmmeter to verify open X-ray photography Cross section failed net SEM examination of cross section BGA Reliability Characterization Project Temperature Cycling Tests Final Report 6

7 The flip chip devices were characterized by failures within the chip-to-substrate connection, rather than the anticipated substrate-to-board connection. 100% of the flip chip BGA nets that failed had this unexpected signature. The Flip Chip BGA devices used in this experiment were pre-production samples and were not fully characterized with respect to assembly processing at the time. In retrospect, it would have been wise to build a first article assembly on packages that were in pre-production status in order to verify the correct assembly conditions. The damage to the chip-substrate solder joints occurred during board assembly processing. This was verified by performing X-ray and cross-section analysis of devices from the same lot that had not been assembled to circuit boards. Refer to Appendix 4 for photographs of some of these failures. HDP User Group members can also view additional photographs on the member s Website, in the reports listed in the References section, below. The failure was characterized by coarsening the solder alloy, heavy formation of intermetallic compounds, and in many cases, melting and smearing of the solder joints. Speculations as to the cause of these failures include delamination of the substrate during assembly (while the balls were molten) and/or warping of the substrate during assembly. In conclusion, F/A results show that the Flip Chip BGA is not going to provide useful data regarding package-board solder joint integrity, and the balance of this paper shall concentrate on the other devices used in the testing. FAILURE ANALYSIS: OTHER BGA S A random sample of failed Tape BGA, Flex BGA and Super BGA devices were subjected to the same F/A testing as described above. In all cases, the failures were found in the package-substrate solder joint. The failure mode is a crack, initiating from a stress concentrator region of the solder ball at the package-solder ball interface, and propagating laterally along the same interface. No heavy intermetallic compound formation was observed in any of the solder joints. As can be seen in Appendix 2, the Weibull plots for these three devices are very close and given the small number of failures at the end of the testing, are statistically indistinguishable. Example SEM photographs of cross sections are shown in Appendix 5. HDP User Group members can also view additional photographs of the other devices at the member s Website listed in the References section, below. DISCUSSION As stated previously, the purpose of the test was to study the effects of package construction, package location on PC board, solder joint location on package, and virgin versus rework boards on the reliability of package-to-board solder joints. The effect of package construction appears to be surprisingly small. As can be seen on the Weibull plot in Appendix 2, the packages performed almost equally. The exception to this rule was the Flip BGA Reliability Characterization Project Temperature Cycling Tests Final Report 7

8 Chip BGA. The Flip Chip BGA exhibited a very different failure mode than the other three packages, as discussed previously. The effect of package location on the PC board was examined. Figure 2 illustrates the board, showing the location of the packages. For purposes of this analysis, the board was divided into three areas: center, edge, and corners. Figure 2 Location of Packages The number of failed nets, by package location on the board is shown in Figure 3. This chart shows the cumulative data from all boards. Note that the Flip Chip BGA was not included in the analysis. Figure 3 The actual failure rate was compared to a simple mathematical probability of failure rate (nets per location). The results are summarized in Table 3 (below). Package Location Probability of Failure Actual Failure rate Center 18% 19% Edge 46% 12% Corner 36% 69% BGA Reliability Characterization Project Temperature Cycling Tests Final Report 8

9 From the above table, centrally located packages failed at a rate consistent with the simple mathematical probability, but the packages located on board edges fared better than expected and packages located on corners did much worse. A standard deviation was calculated in order to determine if the above conclusions are statistically valid. The standard deviation was computed from the variation from board to board. Also helpful in computing the standard deviation was the variation caused by the redundancy of having two Super BGA in corner locations and two TBGA in edge locations. The standard deviations are as follows: Location Center 20% Edge 55% Corner 36% Standard Deviation (failure rate) The Student s T-test was then applied to the data. The null hypothesis selected was that there is a difference between the predicted values and the actual values. The conclusion drawn from the T-test is that there is not a sufficiently large sample size in the experiment to validate the null hypothesis. In other words, the conclusion that solder joint failure rates is dependent on board location is not statistically valid. The second objective was the effect of solder joint location within the package on the reliability of package-to-board solder joints As expected, a strong correlation was observed between solder joint distance from neutral point (DNP) and failure rate. Note that a confidence level of 95% was used for all statistical calculations in this study. In the Tape BGA and Flex BGA, the daisy chain nets that include the tested solder joints can be divided into three categories: those close to the corner of the package, those close to the edge of the package, and those in the center of the package. Figure 4 shows the failure rates for each of these packages. Figure 4 Failed Net Locations, TBGA and Flex BGA Packages BGA Reliability Characterization Project Temperature Cycling Tests Final Report 9

10 Note that no solder joints located in the center nets failed. In the Super BGA, the daisy chain nets that include the tested solder joints can be divided into four concentric rings. Figure 5 shows the failure rates for the BGA. Note that no solder joints located in the central two concentric rings of the Super BGA failed. Figure 5 Failure Rate for Super BGA In all three packages, it is important to note that the solder balls are significantly far from the edge of the silicon chip (over 5 mm). Therefore, the effect of proximity of solder joints to chip edge was not tested in this experiment. The final objective of the experiment was to determine the effect of simulated rework processing on the reliability of the package-to-board solder joints. The Weibull plot comparing these two distributions is shown in Appendix 3. As stated above, the virgin and simulated rework boards have similar failure distributions and it is not clear from the data that there is any significant difference between the two samples. Again, the small number of early failures is dominated by the large number of devices that did not fail by the end of the test. This results in a pair of statistically indistinguishable failure distribution plots. The conclusion that there is no difference between the two distributions might have been more valid if the experiment had been continued to the 50% or higher failure point. That was not, however, economically feasible. CONCLUSIONS The data generated in this experiment leads to fewer conclusions than were hoped for at the start of the experiment. The reason for this is that most of the failures found were caused by manufacturing defects in one of the package types (Flip Chip BGA). If this had been known before the testing ended, the test would have been carried out to a further extent to generate more failures in the packages that had no latent defects. However, the experiment did lead to the conclusions listed below, and was valuable for the direction of future experiments. BGA Reliability Characterization Project Temperature Cycling Tests Final Report 10

11 The most obvious conclusion is the strong correlation between failure rate and DNP. There did not appear to be a correlation between failure rates of packages and their locations on the PC board. There did not appear to be an effect of rework processing on the solder joint reliability. The second phase of the HDP User Group Reliability Characterization Project will compare power cycle testing to the existing temperature cycle testing data, sin the same parts and board construction. However, due to the lack of failures at the end o the temperature cycle test, the comparison will be tenuous. This is because the great majority of the devices in the temperature cycle portion of the test did not fail and therefore the Weibull plots are most likely accurate. For all three w/b packages the cumulative fails at 3,500 cycles is less than 20%, not the 50+% of the curves. This is due to a high failure rate at less than 1,000 cycles, that is not consistent with failure rate over 1,000 cycles. This hints at two failure modes, infant mortality and wear-out affecting the results. There is no failure analysis data to back up this theory, as all parts analyzed were of the early failure category. Possibly the early fails are due to manufacturing or handling defects that further accelerate solder ball fails. In reality it is there early fails that predict system reliability, and it is disheartening that such a high percent of fails occur below 500 cycles. The lesson learned here is to carry the experiment out to an endpoint that yields a statistically useful number of failures, whenever economically feasible. By so doing, an accurate prediction of service life of these components will be possible. The use of more robust packages that have well characterized manufacturing methods would have been helpful. The lack of manufacturing experience with the Flip Chip BGA rendered that portion of the testing invalid. However, the nature of this experiment was to push on leading technologies. Some of the packages used at the start of the testing were not completely developed and it was perhaps fortunate that only one of them had a latent defect that affected the outcome of the test. ACKNOWLEDGMENTS The BGA Reliability Characterization Project is one of several projects within the HDP User Group focused on the reliability of the second level of interconnection namely the integrated circuit package to the multilayer printed circuit board. The HDP User Group has approximately 30 member companies. They consist primarily of OEMs in the Telecommunication/Computer markets and their hardware technology providers. Many HDP User Group members contributed their intellectual support and money to the success of this project. This special acknowledgement is for the major asset providers that made this project possible: David Towne and David Love, Sun Microsystems, provided Project Leadership (Both administrative and technical) Sun Microsystems designed and fabricated the PWBs Chung lam and Yuk Yu, Sun Microsystems, conducted failure analysis Stephen Meeks, Advanced Manufacturing Technology, Motorola Computer Group, Tempe, Arizona, assembled the boards and conducted failure analysis Martin Coleman, Nortel Corp., Advanced Technology, Harlow Laboratories, Harlow, UK, conducted failure analysis BGA Reliability Characterization Project Temperature Cycling Tests Final Report 11

12 Tom Massingill (currently at Fujitsu) and Daniel Lau of VLSI Technology and Matt Doty of Amkor provided packages for testing Trace Laboratories was funded by HDP User Group to perform the temperature cycling David Blanchard of HDP User Group edited and posted documents to the Web Site PROJECT TEAM David Towne David Love Steve Meeks Ramesh Kumar Tom Massingill Martin Coleman Pat Johnson Eugenia Corrales Carlos Avila Jeff Reibling REFERENCES The Failure Analysis Reports are available (with a password) on the HDP user Group Member Website on the Internet at: The following reports are available with pictures of the failure analysis: Motorola Computer Group Failure Analysis Test results Nortel Failure Analysis Test results Sun Microsystems Failure Analysis Test results BGA Reliability Characterization Project Temperature Cycling Tests Final Report 12

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18 The HDP User Group Mission: HDP User Group International, Inc. is a non-profit organization of users and suppliers of electronic devices, chiefly in the Telecommunications and Computer industries, that works to reduce the time-to-market by improving cooperation between users and suppliers in the packaging design process using member resources supplemented by a small staff. For More Information: International Headquarters Bob Sullivan North Scottsdale Road, Suite B Scottsdale, AZ , USA Phone: (602) FAX: (602) bob@hdpug.org European Office Ruben Bergman Langbrodalsvagen 73 S Alvsjo SWEDEN Phone or FAX: in Sweden ruben.bergman@hdpug.se BGA Reliability Characterization Project Temperature Cycling Tests Final Report 18