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1 Parti BST and DRAM

Chemical Vapor Deposition Technology of (Ba,Si*)TiO 3 Thin Films for Gbit-Scale Dynamic Random Access Memories Tsuyoshi Horikawa, Masayoshi Tarutani, Takaaki Kawahara, Mikio Yamamuka, Noriko Hirano,

3 Chemical Vapor Deposition Technology of (Ba,Si*)TiO 3 Thin Films for Gbit-Scale Dynamic Random Access Memories Tsuyoshi Horikawa, Masayoshi Tarutani, Takaaki Kawahara, Mikio Yamamuka, Noriko Hirano, Takehiko Sato, Shigeru Matsuno, Teruo Shibano, Fusaoki Uchikawa, Kouichi Ono* and Tatsuo Oomori Advanced Technology R&D Center, Mitsubishi Electric Corporation 8--, Tsukaguchi-Honmachi, Amagasaki , Japan * Department of Aeronautics and Astronautics, Graduate School of Engineering, Kyoto University, Yoshida-Honmachi, Sakyo-ku, Kyoto , Japan ABSTRACT The current status of (Ba,Sr)TiO 3 [BST] capacitor technology using a liquid source chemical vapor deposition (CVD) method is reviewed, focusing on the CVD techniques and the physical, electrical and process-integration-related properties of Ru/BST/Ru capacitors. The use of a new titanium metalorganic (MO) source, titanium bis(terf-butoxy) bis(dipivaloylmethanato) [Ti(tert- BuO) 2 (DPM) 2 ] dissolved in tetrahydrofuran (THF) turned out to enable highly conformal deposition of BST films with a coverage ratio of - 70 % for a trench with an aspect ratio of ~ 5. Electrical properties of a 24-nm-thick BST film, deposited on a Pt substrate at a low substrate temperature of 480 C, were also confirmed to be equivalent SiO 2 thickness (t eq ) of ~ 0.5 nm and leakage current of - lxlo" 7 A/cm 2 at V. As for the Ru/BST/Ru capacitors, no deteriorations of Ru electrode and BST/Ru interface were observed after 750 C post-annealing experiment, showing good thermal stability of Ru as a practical electrode material. Although current leak through Ru/BST/Ru capacitors slightly increased after the H 2 annealing, such degradation in the leakage properties was restored by post-annealing in N 2 ambience. Integrated Ru/BST/Ru capacitors with a 30-nm-thick CVD-BST film were fabricated by 0.5 ^m ULSI technology, and low leakage current was confirmed for the stacked capacitors. Regarding the reproducibility of BST deposition by the liquid source CVD method, the deviation ratio of ~ ± 2.3 % in film thickness was obtained for - 00 successive depositions, thickness uniformity across the wafers was -±.%. The above results imply the potential applicability of BST capacitor technology using a liquid source CVD method for Gbit-scale DRAMs. INTRODUCTION Simple stacked cells with high dielectric constant (Ba,Sr)TiO 3 [BST] films have been proposed for the development of Gbit-scale density dynamic random access memories (DRAMs) and beyond [-3]. The minimum feature size in the DRAMs should be less than 0.5 xm. To achieve a cell capacitance of 25 ff in such small dimension, the height of storage nodes required in stacked capacitors is estimated to be more than 300 nm, even though BST films with equivalent SiO 2 thickness (t eq ) of 0.5 nm are used [3]. This indicates that highly conformal deposition of dielectric films is needed on the side wall of the storage node with a high aspect ratio. From this standpoint, chemical vapor deposition methods are expected to be the most promising solution as a deposition technique for the BST films. In the backend processes of the device integration, the BST capacitors suffer some severe processes, for example, high temperature annealing used for planarization, and H 2 annealing for Mat. Res. Soc. Symp. Proc. Vol Materials Research Society 3

the restoration of metal-oxide-semiconductor field effect transistor (MOSFET) performance. Several reports have pointed out the degradation of the capacitors through such backend process conditions.

4 the restoration of metal-oxide-semiconductor field effect transistor (MOSFET) performance. Several reports have pointed out the degradation of the capacitors through such backend process conditions. Therefore, many efforts focusing the process-induced damages on BST capacitors should be done in order to establish BST capacitor process. For the deposition of BST films, the selection and further refinement of the deposition processes and CVD apparatus is needed from the standpoint of mass-productivity, that is the reproducibility for successive depositions. In this paper, we present the current status of BST-CVD technology using a liquid source CVD method for Gbit-scale DRAM. At first, the conformality of BST films deposited by the CVD method is demonstrated, as well as electrical properties of BST capacitors. Then, backend process effects, such as high temperature annealing and H 2 annealing to Ru/BST/Ru capacitors, are reviewed. The properties of CVD-BST films in integrated capacitors are also shown, through the use of integration processes using 0.5 ^m ULSI technology. The reproducibility and uniformity of successive depositions by the CVD method is presented. Finally, we will discuss the applicability of BST films to future DRAM memory cells. LIQUID-SOURCE CVD USING THF SOLUTIONS OF MO SOURCES CVD System Figure shows a schematic of the liquid source CVD system for BST thin films [4, 5]. Metalorganic (MO) compounds, such as barium bis(dipivaloylmethanato) [Ba(DPM) 2 ], strontium bis(dipivaloylmethanato) [Sr(DPM) 2 ], and titanium oxo bis(dipivaloylmethanato) [TiO(DPM) 2 ] were basically used as source materials. BST films were formed as follows. Tetrahydrofuran (THF) solutions of the MO compounds were delivered into a vaporizer in front of a deposition chamber, and therein-vaporized sources were mixed with oxygen and were uniformly distributed onto a substrate in a chamber [4], where the MO sources can decompose into film precursors, and BST films were formed. The vaporizer and chamber walls were heated at more than the vaporizing point temperature of these sources. Substrate temperatures of C were used for film deposition, because BST films deposited at such low substrate temperatures have a high coverage ratio [5]. To prevent morphology roughening due to protrusion formation in the lowtemperature deposition, we have developed a two-step deposition technique, featured by the insertion of a thin crystallized buffer BST layer [5]. Inert Gas To Pump Substrate Heater Fig. Schematic of liquid-source CVD for BST films.

The advantages of the liquid source CVD method using THF solutions are summarized as follows: () Deposition rate more than 5 nm/min even at low substrate temperature; a large amount of MO sources can

5 The advantages of the liquid source CVD method using THF solutions are summarized as follows: () Deposition rate more than 5 nm/min even at low substrate temperature; a large amount of MO sources can be constantly delivered and easily vaporized, as compared with conventional solid-source CVD method. (2) Less denaturation of MO sources; solvation by THF stabilizes MO sources and prevents their denaturation. (3) Compact and clog-free source delivery system; in solid-source CVD, the temperature of whole delivery system should be precisely controlled to prevent clogging, on the other hand, in liquid source CVD, the delivery system does not need heating, so the system becomes very compact and substantially clogging free. BST DEPOSITION USING AN ADVANCED MO SOURCE In our previous studies [4-7], it was demonstrated that the sticking probability of Ti precursors affects the conformality of BST film much more than those of Ba and Sr precursors. The best coverage ratio of 50 % for an aspect ratio of 3.3 has been obtained using TiO(DPM) 2 [7J. However, it is not sufficient for Gbit-scale DRAMs. Therefore, we examined a new titanium source, titanium bis(/e/*/-butoxy) bis(dipivaloylmethanato) [Ti(/er/-BuO) 2 (DPM) 2 ] which has a very low sticking probability [ref. 8, see molecular structure in Fig. 2]. Figure 3 shows a cross-sectional SEM image for the BST film on a high-aspect trench, deposited at 480 C using Ti(tert-BuO) 2 (DPM) 2 [7]. The BST on the trench side wall does not have an over-hanged area, but is almost conformal. The thickness of side wall BST is about 70 % of that on top face for a trench with an aspect ratio of around 5. It is noted that such a high conformality of BST, which will satisfy the requirement of the application to Gbit-scale DRAMs. As for the electrical properties of 24-nm-thick BST films using this precursor, the dielectric constant of 207 (t^ of 0.44 nm) and leakage current less than lxlo' 7 A/cm 2 at V were obtained, in the case of Pt/BST/Pt flat capacitors with electrode area of. mm 2. It is noted that these (Me) r cj H^c, /C-<Me) 3 \ Q Fig. 2 Molecular structure of titanium Fig. 3 Cross-sectional SEM image of BST film bis#<?r/-butoxy) bis(divibaloylmethanato), deposited on a trench with an aspect ratio of ~~ 5. Ti(fcf*-BuO) 2 {DPM) 2. The BST film was deposited by liquid-source CVD using Ti(ter*-BuO) 2 (DPM) 2

6 properties of BST films almost satisfy the basic device requirements [3]. BST THIN FILMS DEPOSITED ON Ru ELECTRODE Thermal Stability of Ru/BST/Ru Capacitors Structural and electrical stability were examined for high temperature annealing at 750 C for 30 min in N 2 ambience. The tested sample consisted of the layered structure: BST/Ru/TiN/Ti/Si. A 30-nm-thick BST film was deposited using Ba(DPM) 2, Sr(DPM) 2, and TiO(DPM) 2, by the twostep deposition method [5]. To avoid oxidation of Ru electrode by residual oxygen during annealing, an SiO 2 passivation film was deposited on the structure. After annealing, the SiO 2 film was removed by dry etching method for analytical and electrical measurements. Figure 4 shows the SIMS-depth profiles of Si, Ti, and Ru through an annealed capacitor. It is noted that no interdiffusion of Si into Ru layer was observed, showing that the TiN layer acted as a barrier to Si diffusion. In the XRD pattern [Fig. 5], there is not any marked peak ascribed to oxide and/or silicide of Ru. Hence, it is confirmed that the BST/Ru interface has good thermal stability. It is also added, that electrical measurements showed the leakage current was kept at a low level even after the 750 C annealing, though these data are not cited here [3]. * < BST c/) 2 0 j 0' - I I Ru Ru / TiN/Ti Y Ti ' Sputtering Time (s) Si Si e CO ic.2 a (200 o5 fl? z P Peak Position TRuSi VRuO 2 8 E s. /. on Si W ^ ^? CN ill 3 3 C (degree) Fig. 4 SIMS depth profiles for BST/Ru/TiN/Ti/ Fig. 5 X-ray diffraction pattern from BST/Ru/ Si structure after annealing at 750 C for 30 min TiN/Ti/Si structure after annealing at 750 C in N 2 ambience. for 30 min in N 2 ambience. Effect of Hydrogen Anneal Figure 6 shows the current-voltage characteristics of Ru/BST/Ru capacitors before/after H 2 annealing at 400 C for 30 min. Although severe leakage degradation by annealing in hydrogencontaining ambience has been reported for BST capacitors with Pt electrodes [9], it was found that only a small decrease of the turn-on voltage is caused by H 2 annealing for the Ru/BST/Ru

-2 0 I 0-h 0"' Iff 0' -9 After H 2 Annealing and post N 2 Annealing After H 2 Annealing Before H2 Annealing ^ ^ f.... -2-0 Applied Voltage (V) jf f r Fig.

7 -2 0 I 0-h 0"' Iff 0' -9 After H 2 Annealing and post N 2 Annealing After H 2 Annealing Before H2 Annealing ^ ^ f Applied Voltage (V) jf f r Fig. 5 Current-voltage characteristics of Ru/BST/Ru capacitors, before H 2 annealing (solid), after H 2 annealing at 400 C for 30 min (dashed), and after N 2 annealing at 400 C for 30 min following to the H 2 annealing (chain). The equivalent SiO 2 thickness for these capacitors is 0.50 nm. capacitors. Further, it is noted that the degradation of leakage properties was mostly recovered by post annealing in N 2 at 400 C for 30 min. It is clear that two process requirements of thermal and H 2 anneal resistivity can be met in Ru/BST/Ru capacitors with the BST films by liquid source CVD. INTEGRATION OF Ru/BST/Ru CAPACITORS Fabrication of Capacitors BST stacked capacitors were fabricated using the 0.5 \xm ULSI technology. Figure 6 shows the fabrication flow of the integrated capacitors. The storage nodes of Ru/ TiN/Ti structure were electrically connected to the Si substrate via poly- Si plugs. The Ru electrodes were etched by oxygen-containing plasma using SiO 2 -hard mask. A 30-nm-thick BST film was deposited on patterned storage nodes using the two-step method. Finally, Ru was deposited thereon by sputtering, followed by patterned etching to form top electrodes. SiO 2 Ru TiN/Ti / / Poly-Si Plug Formation Barrier Metal (TiN/Ti) Deposition Ru Deposition Si6 2 Deposition I Lithography Si6 2 Etching r Ruand Barrier Metal Etching Si6 2 Removal I BST Deposition (Low Ts, Two-Step CVD) st Deposition (Buffer Layer) st Annealing 2nd Deposition (Main Layer) 2nd Annealing Ru Deposition Fig. 6 Fabrication flow of integrated Ru/BST/Ru capacitors.

8 (b) BST film on the top surface of SN (c) BST film on the side wall of SN (a) Whole view of a BST capacitor Fig. 7 Transmission electron micrograph image, (a) for the whole view of an integrated BST capacitor, (b) for BST film on the top surface of a Ru storage node, and (c) for BST film on the side wall of the Ru storage node Voltage (V) Fig. 8 Current-voltage characteristics for arrays of 9 M Ru/BST/Ru capacitors integrated in 0.5 (im rule, where a Ru storage node in each capacitor is 0.2 ^m high, has \im x im area. The value of t^ for BST films on the 3-D structure was estimated to be about 0.8 nm.

9 BST Films on Patterned Electrodes Figure 7a shows a cross-sectional transmission electron microscopy image of the integrated capacitor. It is shown that BST, Ru, and TiN layers are composed of columnar crystallized grains, respectively. It is noted that the BST film covers the bottom electrode with a high conformality, Enlarged images of the BST on the top of storage node [Fig. 7b] and on the side wall [Fig. 7c] shows that the BST film are wholly well-crystallized, while the side BST film is slightly thinner than the top one. Electrical Properties of Integrated Capacitors Figure 8 shows current-voltage characteristics for the integrated capacitors as shown in Fig. 7. Each characteristic was measured for 32 arrays of 9M capacitors within a 6-inch wafer. Ru storage nodes in integrated capacitors are ~ 0.2 \im high, and have a projection area of ^lm x (im. The average value of t^ for BST films on the 3-D structure was estimated to be about 0.8 nm. REPRODUCIBILITY OF BST DEPOSITION BY LIQUID SOURCE CVD The reproducibility of BST deposition using the liquid source CVD method should be affected by many parameters, such as purity of MO sources, precise flow control of liquid source, temperature control of a vaporizer and chamber walls, and uniformity of gas flow through vaporizer to chamber. Recently, we have optimized entire flow control in liquid and gas flow in our CVD apparatus, and investigated the reproducibility for successive deposition. Figure 9 shows the run-to-run reproducibility of film thickness and refractive index, each for 00 successive depositions. The standard deviations from each mean value are ±2.3 %. The uniformity of film thickness and refractive index across a wafer was also measured. The standard deviations from average values are ±. % in film thickness, and ± 0.7 %, ±.2%, and Run Number Fig. 9 Repeatability of film thickness, refractive indices, and incorporation ratio of metal components for 00 sequential depositions of BST on 6-inch wafers.

10 ±0.7 %, in Ba, Sr, and Ti incorporation ratios, respectively. From the above results, it was concluded that the liquid source CVD method using THF solutions is suitable for uniform and reproducible deposition of BST films, though there are remaining items to be solved. CONCLUSIONS We have shown the current status of BST technology using liquid source CVD method. It was confirmed that our CVD-BST technology satisfies the requirements for Gbit-scale DRAM application, summarized as follows: () The high conformality of BST films on fine 3-D storage node structure of stacked capacitors as well as high dielectric constant and low leakage current. (2) No severe deterioration of electrode during BST deposition. (3) The stability of BST capacitors toward backend processes. Extensive research to further optimize the integration process for BST capacitors using CVD technique is now underway. ACKNOWLEDGMENTS The authors express would like to thank to Dr. S. Satoh for his encouragement throughout the studies reviewed in this paper. They also thank to Dr. N. Mikami for helpful discussions about the dielectric properties of BST capacitors, and to Messrs. T. Kuroiwa, K. Nakamura, Y. Yoneda, T. Takenaga, and Dr. Y. Kitazawa for their support in the fabrication of the integrated capacitors. REFERENCES. A. Yuuki, M. Yamamuka, T. Makita, T. Horikawa, T. Shibano, N. Hirano, H. Maeda, N. Mikami, K. Ono, H. Ogata, and H. Abe, Tech. Dig. IEDM995, S. Yamamichi, P-Y. Lesaicherre, H. Yamaguchi, K. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, and H. Ono, Tech. Dig. IEDM 995, K. Ono, T. Horikawa, T. Shibano, N. Mikami, T. Kuroiwa, T. Kawahara, S. Matsuno, F. Uchikawa, S. Satoh, and H. Abe, Tech. Dig. IEDM 998, T. Kawahara, M. Yamamuka, T. Makita, J. Naka, A. Yuuki, N. Mikami and K. Ono, Jpn. J. Appl. Phys., 33, (995). 5. T. Kawahara, M. Yamamuka, A. Yuuki and K. Ono, Jpn. J. Appl. Phys., 34, (995). 6. M. Yamamuka, T. Kawahara, M. Tarutani, T. Horikawa and K. Ono, 9th Symp. Dry Process 997, T. Kawahara, S. Matsuno, M. Yamamuka, M. Tarutani T. Sato, T. Horikawa, F. Uchikawa, and K. Ono, Ext. Abstr. SSDM 998, K. Ogi and A. Itsuki, Proc. 5th Symp. Semiconductors and Integrated Circuits Tech., (996) [in Japanese]. 9. R. Khamankar, B. Jiang, R. Tsu, W.-Y Hsu, J. Nulman, S. Summerfelt, J. M. Anthony, and J. C. Lee, Symp. VLSI Tech. Tech. Dig. 995,

Fabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical Vapor Deposition

Mat. Res. Soc. Symp. Proc. Vol. 784 2004 Materials Research Society C7.7.1 Fabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical