THE rapid development of microelectronic systems, such

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1 938 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015 Modeling, Fabrication, and Reliability of Through Vias in Polycrystalline Silicon Panels Qiao Chen, Hao Lu, Venky Sundaram, and Rao R. Tummala, Fellow, IEEE Abstract Silicon interposers with through-silicon vias (TSVs) have been developed in single-crystalline silicon wafer to address the high I/O density requirements between high performance logic, memory, graphic, and other devices. However, singlecrystalline silicon interposers suffer from many shortcomings such as high cost, low electrical performance, and reliability. To overcome these shortcomings of traditional silicon interposers, an entirely different approach using polycrystalline silicon panels with polymer liners and through-package-vias (TPVs) is proposed by Georgia Tech Packaging Research Center. This paper, for the first time, focuses on the reliability of TPVs in polycrystalline silicon interposers fabricated from panels. Mechanical simulations were carried out that show lower stresses in TPVs in polycrystalline silicon lined with thick polymer liners, compared with TSVs in traditional single-crystalline silicon with thin SiO 2 layers. TPVs were fabricated for thermal cycling tests, resistance monitoring, and scanning electron microscope imaging. The reliability characterization results showed good mechanical reliability of TPVs in polycrystalline silicon panels. Index Terms Fracture strength, polycrystalline silicon panel, reliability characterization, silicon interposer. I. INTRODUCTION THE rapid development of microelectronic systems, such as smartphones and tablets, has fueled a growing interest in advancing packaging technologies to smaller pitch and lower cost [1]. One of these advanced packaging technologies is the development of interposers for interconnecting 3-D IC stacks with through-silicon vias (TSVs) [2]. Traditional silicon interposers, based on TSV techniques, however, suffer from high production cost because of expensive CMOS tools and processes and small wafer sizes. They also suffer from high electrical loss in spite of thin SiO 2 layers [3], [4]. In addition, the thin SiO 2 layers can also lead to reliability problems. Liu et al. [5], [7] [9] and Chen et al. [6] have extensively reported the finite-element modeling (FEM) and Manuscript received March 26, 2015; revised June 15, 2015; accepted June 15, Date of current version July 15, This work was supported by the Silicon and Glass Interposer through the Consortium of Georgia Tech Packaging Research Center. Recommended for publication by Associate Editor A. Chandra upon evaluation of reviewers comments. Q. Chen, H. Lu, and V. Sundaram are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA ( qiaochen198411@gatech.edu; hlv6@gatech.edu; vsunda@ece.gatech.edu). R. R. Tummala is with the School of Electrical and Computer Engineering, School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA USA ( rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT simulations of the stress distribution in TSVs. These models showed that the stresses at the Cu/SiO 2 interface and in the SiO 2 layer lead to potential failure mechanisms in TSVs, such as liner delamination and cracking, both of which are confirmed by the characterization of fabricated TSVs after thermal cycling. Cassidy et al. [10] reported similar results by identifying the localized stresses around the TSV sidewalls. It was also pointed out that the thin oxide liner was susceptible to problems such as leakage and dielectric breakdown. Georgia Tech Packaging Research Center proposed an alternative to silicon interposer with through-package vias (TPVs) to interconnect logic memory for high bandwidth in the short term and entire systems in the long run with the system-on-package concept technology [11]. This interposer technology is a panel-based polycrystalline silicon with TPVs lined with thick polymers, aimed at lowering the total cost of fabricating the interposer with high performance and high reliability [12] [14]. Due to its lower purity level, polycrystalline silicon material presents a much lower resistivity ( 0.5 cm) than the traditional wafer. Hence, addressing this higher loss and yet achieve higher performance is one of the major challenges. This issue can be addressed with the introduction of low loss and thick polymer liners for insulating the lossy silicon. The electrical simulation results in [14] confirmed that TPVs with polymer liners present superior electrical performance, such as lower insertion loss, than the TSVs with thin SiO 2 layers. This paper focuses on the reliability of these TPVs. To address the reliability challenges due to the coefficient of thermal expansion (CTE) mismatch between Cu and silicon, thick, and low cost polymer liners with low modulus are proposed to act as stress buffer, replacing SiO 2 and barrier layer in TSVs. This paper starts with the introduction of polycrystalline silicon panels followed by a study of handling such thin panels during processing (Section II). Following Section II, Section III presents the mechanical modeling results, showing the stress comparisons between TPVs in polycrystalline silicon interposers and TSVs in traditional silicon interposers. Parametric studies were also performed with in-via liner thicknesses. Section IV summaries the fabrication of TPVs. Reliability characterization of TPVs is presented in Section V with thermal cycling tests, resistance monitoring, and scanning electron microscope (SEM) imaging. II. POLYCRYSTALLINE SILICON PANELS The top view of the 200-μm thick polycrystalline silicon panel used in this paper is shown in Fig IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information

2 CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 939 Fig. 1. Polycrystalline silicon panel used in this paper. Fig. 2. Four-point bend test to evaluate fracture strength. Polycrystalline silicon panels have been widely used in photovoltaic industry as the substrate material for solar-cell applications [15] [18], but not as substrates for interposer demonstrations. Polycrystalline silicon panel is cheaper to fabricate than the single-crystalline wafer, and can be scaled to large sizes. More importantly, the larger size substrates yield more numbers of interposers, thus promising to lower the cost of single-unit interposers. However, polycrystalline silicon is a brittle material, and therefore, one of the fundamental challenges is the high fracture rate caused by handling during the TPV liner formation and metallization process steps. These challenges get exacerbated when moving to thinner and larger panel sizes. To overcome these panel breakage challenges, surface polymer liners on both sides of the panel were introduced. The surface liner not only minimizes the damage, improves the strength, and enables handling of the thin silicon panels, but also functions as an electrical insulator to isolate signals from leaking into the lossy silicon. The surface liner was deposited by vacuum lamination of thin dry film polymer dielectrics during TPV liner fabrication process [14]. The fracture strength of any brittle material, such as polysilicon, is controlled by the existence of critical defects, which act as the origins of the final failure. Unlike single-crystalline silicon, defects are distributed randomly in the polycrystalline silicon panels, due to different crystal orientations and grain boundaries. Different grain orientations can be clearly observed in the top view detail of the as-cut polycrystalline silicon panel made by directional solidification, shown in Fig. 1. Therefore, it is inaccurate to evaluate the fracture strength of the sample by carrying out the experiment on an entire large panel. Hence, to quantify the fracture strength of the stack consisting of the silicon panel with polymer liners, three types of samples were prepared, including raw silicon panels, silicon panels laminated with 22.5-μm thick polymer liners on both sides, and silicon panels laminated with 40-μm thick polymer liners on both sides. Each test sample was diced into 24 rectangular pieces, each having a length of 37.5 mm and a width of 25 mm, and mechanically tested by four-point bending tests (Fig. 2). The schematic of testing fixture, with the sample mounted, is shown in Fig. 3. The stress was calculated Fig. 3. Schematic of fixture setup for four-point bending test. using the following [19]: σ = 3P(L L i) 2bd 2 (1) where σ is the stress due to applied load, P is the applied load, L outer span, L i is the inner span, b is the sample width, and d is the sample thickness. Consistent with the hypothesis about the randomness of the defects, strength data were generated with a large amount of scatter, due to many variables such as defect locations, grain sizes, and orientations. Therefore, statistical treatment of the strength data was necessary with Weibull plots. Weibull theory of brittle fracture is based on the fact that failure of the whole body depends on a combination of survival probabilities of the individual volume elements. For a given test, the Weibull equation can be written as [20] [ ( ) σ m ] P f = 1 exp (2) where P f is the probability of failure due to applied stress σ, σ θ is the characteristic strength when 62.5% of the sample fails, and m is the Weibull modulus. In general, the Weibull plots can be obtained by assigning P f to each strength point. The two important factors σ θ (usually used as a reference for the fracture strength of the sample) and m (Weibull modulus describing the variation of the data) are achieved by plotting ln(1/ln(1 P f )) versus ln(σ ) followed by a linear regression analysis. σ θ

3 940 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015 Fig. 5. Schematic cross-sectional drawing of TPV for mechanical modeling. Fig. 4. Weibull plots of fracture strength for silicon panels with and without polymer liners. TABLE I PARAMETER VALUES FOR FRACTURE STRENGTH AFTER LINEAR REGRESSION The Weibull plots for three types of test samples are compared in Fig. 4 with critical factors obtained from linear regression summarized in Table I. It can be concluded from Fig. 4 and Table I that surface polymer liners significantly improve the fracture strength and thus the handling of the thin polycrystalline panels. The thicker polymer led to even higher fracture strength. The comparison between Weibull modulus from different sets of data suggests that the variations were small enough and were similar in each data set, confirming the validity of the tests. These results proved the hypothesis that surface liners on both sides of the panel help improve the handling of the substrate and thus mitigate the panel breakage problem. III. MECHANICAL MODELING OF TPVs In this section, FEM was performed using Ansoft Ansys to simulate the proposed TPV structure with polymer liners, in comparison with TSVs with thin SiO 2 liners. A 2-D axisymmetric model was built to generate and analyze both the interfacial shear and first principal stresses due to thermal loading. Parametric studies were also performed with sidewall liner thickness. The schematic cross section (one-fourth via) is presented in Fig. 5 with geometry values. The Cu via size was 30 μm with a height of 200 μm. The diameter of the pad was 50 μm and the thickness was 10 μm. Fig. 6 compares the schematic cross section and meshed models for TPVs and TSVs. In this paper, TPVs were simulated with 3-μm-thick polymer liner on the top and Fig. 6. Schematic cross-sectional drawings and meshed models for (a) TPV and (b) TSV. TABLE II MATERIAL PROPERTIES USED IN MECHANICAL MODELING bottom surfaces and 3-μm-thick via sidewall liner, compared with 1-μm-thick SiO 2 liner on the top and bottom surfaces of silicon and 1-μm-thick via sidewall liner for TSVs. The effect of the very thin diffusion barrier was neglected in TSV modeling. The material properties used in the simulations are given in Table II. The polymer presents moderate CTE and much lower modulus than SiO 2. The nonlinear model of

4 CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 941 TABLE IV STRESS COMPARISONS FOR TPV WITH DIFFERENT SIDEWALL LINER THICKNESSES Fig. 7. Thermal loading curve for mechanical modeling. Fig. 8. stress. Contour plots for the (a) first principal stress in Si and (b) shear TABLE III STRESS COMPARISONS IN TSV WITH SiO 2 LINER AND TPV WITH POLYMER LINER Cu was used based on [5]. A standard thermal load cycle of 55 C 125 C (Fig. 7) was used in the analysis with a dwelling time of 15 min at both extreme temperatures. The contour plots of the first principal stress in Si and shear stress are shown in Fig. 8. Stress localizations occur at the interfaces of different materials due to CTE mismatch. Table III summaries the maximum first principal stress in Si substrate and the maximum shear stress for TPVs and TSVs at 125 C. It can be observed that the maximum first principal stress in silicon is significantly reduced in TPV (164 MPa) compared with TSV (259 MPa). This is due to the low modulus and cushion effect [22] of the polymer material. The much smaller stress in TPV can mitigate the possibility of silicon crack and thus result in better reliability. Similarly, TSV shows larger (137 MPa) maximum shear stress than the TPV (85 MPa). The relatively higher interfacial shear stress localizations in TSV structures can be attributed to the higher CTE mismatch of SiO 2 with Cu vias. This makes it more susceptible to delamination failures compared with TPV structures. Based on the above discussions, thick polymer liners in TPVs act as buffer layers, absorbing stresses, and can reduce the risk of failures in both substrate cracking and interface delamination. On the other hand, TSVs show higher stress in spite of the thinner layer of SiO 2. Furthermore, due to higher stiffness of SiO 2, the TSV structures are more prone to cohesive cracks in liners compared with TPV structures. It is also expected that TSV structures would experience additional stresses during the backgrinding processes required for fabricating these structures. Parametric studies are also performed with varying sidewall liner thickness, since this analysis can provide important guidelines for the reliability of TPVs. Three different cases, 5-, 10-, and 15-μm in-via liners, were studied and compared. The substrate thickness in each case was 200 μm andthe diameter of the via (Cu filled) was 30 μm. The surface liner was 15-μm-thick. As presented in Table IV, when the in-via liner becomes thicker (5, 10, and 15 μm), the maximum first principal stress at 125 C gradually decreases (111, 52, and 21 MPa). Hence, at elevated temperature, larger polymer liner thicknesses absorb the stresses more effectively and lead to less first principal stresses in silicon and thus less risk of cohesive cracking in the substrate. It can also be summarized from Table IV that the maximum shear stresses for TPVs are 82, 80, and 79 MPa for TPVs with 5-, 10-, and 15-μm liners, respectively. As expected, the shear stresses localize at material interfaces and larger liner thicknesses also help to reduce the shear stresses, thus leading to a smaller possibility of delamination failures. IV. FABRICATION OF TPVs Following the simulation results from Section III, this section discusses the fabrication of test vehicles to evaluate the thermomechanical reliability of TPVs in polycrystalline silicon panels. These test vehicles consisted of two metal wiring layers and TPV transitions with daisy chain structures.

5 942 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015 Fig. 10. Top view of the fabricated test structures. Fig. 9. layers. Fabrication process flow for test vehicle with TPVs and two metal In addition, four-point probe pads (kelvin structures) were included in the design, which are able to exclude any errors from probe contact resistances and wire resistances. The fabrication process used is presented in Fig. 9. The process started with the cleaning of the 150-mm as-cut polycrystalline silicon panel with acetone, methanol, isopropanol, and deionized water. Then, TPVs were drilled by 355-nm UV laser ablation with via entrance diameters of 80 μm. UV lasers were used for the best combination of via size reduction, cost, and throughput. The panels then underwent a plasma cleaning step to remove impurities, followed by a surface treatment with silane solutions (3-aminopropyltrimethoxy silane). This silane treatment was meant to form covalent bonds at the interfaces between silicon and the applied polymer films to improve adhesion [23]. 40-μm-thick polymer dry films were laminated on both sides to insulate the surface and fill the via. This step was achieved using a vacuum laminator at 95 C. This vacuum-assisted process removed the air inside the via, leading to a faster and void-free filling process for the TPVs. In addition, such a double-side process can help to mitigate any potential warpage of the thin silicon panel generated by the heating and cooling cycles in the lamination process. A short hot press cycle was performed at 120 C with 1-ton force for better planarity by eliminating any dimples resulting from the filling process, followed by a thermal curing to complete the polymerization reactions. Then, a second UV laser ablation process step was applied to form 50-μm diameter through holes in the polymer, leading to 15-μm TPV sidewall liners. Precise alignment of the laser beam to the TPV locations was necessary to ensure that the ablation process happened in the center of the vias in silicon and to maintain sufficient polymer liner thickness on the side walls. The TPV metallization and redistribution layer fabrication required an electroless copper seed layer, in contrast to sputtered seed for TSVs. Prior to such a process, a chemical desmear process was performed to roughen the polymer liner surface to improve Cu-to-polymer adhesion. The panel was then patterned by a double-sided lithography process. This process consisted of several steps, starting with dry-film photoresist lamination using a hot roll laminator, followed by an UV exposure, and photoresist development by dilute sodium carbonate solution in a spray tool. Subsequently, electrolytic copper plating using a semiadditive process method was carried out, varying both the current density as well as the plating time to control the final Cu thickness. The photoresist was then stripped by potassium hydroxide and the Cu seed layer was etched by dilute CuCl 2 solution. The top view of the fabricated test structures is shown in Fig. 10. V. RELIABILITY CHARACTERIZATION OF TPVs The test vehicles were first subjected to a 24-h bake at 125 C, followed by accelerated moisture sensitivity level 3 preconditioning (60 C and 60% RH for 40 h), followed by three times reflow at a peak temperature of 260 C, to simulate the lead-free solder board assembly processes. The test vehicles were then subjected to thermal cycles between 55 C and 125 C with a dwelling time of 15 min at each temperature extreme, as described in JEDEC JESD22-A104 condition B test standard. The samples were taken out at 100, 200, 500 cycles, and every 500 cycles thereafter, and the daisy chain resistances were measured to detect

6 CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 943 Fig. 11. Resistance measurement of reliability samples. Fig. 13. SEM image of Si/polymer liner interface. low modulus and moderate CTE that effectively absorbed the stresses from CTE mismatch between copper and silicon. VI. CONCLUSION This paper presents, for the first time, the modeling, fabrication, and reliability of TPVs in polycrystalline silicon panels. The reliability test vehicles with metalized TPVs and daisy chain structures were successfully demonstrated. Both mechanical modeling and reliability characterization results indicate that TPVs in polycrystalline silicon panels can achieve high reliability due to the thick sidewall polymer liners with low modulus and moderate CTE. Fig. 12. SEM image of Cu/polymer liner interface. TPV failures, as shown in Fig. 11. No significant resistance changes were observed during the tests. All the TPV daisy chains survived 4000 thermal shock cycles with a stable resistance value of 0.13, confirming the thermomechanical reliability of TPVs in polycrystalline silicon panels. To characterize the samples after thermal cycling tests, SEM imaging was carried out after microsectioning and fine polishing. To protect the sample and to avoid any artificial cracking during sample handling and cross sectioning, TPV samples were first molded in epoxy resins. Then, the molded samples were fine polished to expose the TPVs. No Cu cracking was found, which may explain why there were no resistance changes. In addition, no silicon cracking was observed, which can be attributed to the cushion effect of polymer liners to mitigate the first principal stresses in silicon, as discussed in Section III. Magnified images at TPV corners were also observed to analyze the interfaces between different materials, where shear stress localizations occur, as predicted by the FEM and simulations. The Cu/polymer liner and Si/polymer liner interfaces are shown in Figs. 12 and 13, respectively. It can be concluded that no delamination failures occurred at either of these interfaces. This is due to the thick polymer liners with ACKNOWLEDGMENT The authors would like to thank the Silicon and Glass Interposer Consortium of Georgia Tech Packaging Research Center for their support. The authors would also like to thank Y. Suzuki from Zeon Corporation for polymer process guidance, and Micron Laser for their support. REFERENCES [1] R.R.Tummala,Fundamentals of Microsystems Packaging. NewYork, NY, USA: McGraw-Hill, [2] R.R.Tummalaet al., Trend from ICs to 3D ICs to 3D systems, in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, USA, Sep. 2009, pp [3] Z. Xu and J.-Q. Lu, High-speed design and broadband modeling of through-strata-vias (TSVs) in 3D integration, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 2, pp , Feb [4] Z. Xu, A. Beece, K. Rose, T. Zhang, and J.-Q. Lu, Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration, in Proc. IEEE Int. Conf. 3D Syst. Integr. (3DIC), Sep. 2009, pp [5] X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. R. Tummala, and S. K. Sitaraman, Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV), in Proc. 59th Electron. Compon. Technol. Conf. (ECTC), May 2009, pp [6] Q. Chen, X. Liu, V. Sundaram, S. K. Sitaraman, and R. R. Tummala, Double-side process and reliability of through-silicon vias for passive interposer applications, IEEE Trans. Device Mater. Rel., vol. 14, no. 4, pp , Dec [7] X. Liu et al., Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps, in Proc. IEEE 61st Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2011, pp

7 944 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015 [8] X. Liu et al., Reliability assessment of through-silicon vias in multi-die stack packages, IEEE Trans. Device Mater. Rel., vol. 12, no. 2, pp , Jun [9] X. Liu, Q. Chen, V. Sundaram, R. R. Tummala, and S. K. Sitaraman, Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test, Microelectron. Rel., vol. 53, no. 1, pp , Jan [10] C. Cassidy et al., Through silicon via reliability, IEEE Trans. Device Mater. Rel., vol. 12, no. 2, pp , Jun [11] R. R. Tummala, Introduction to System-on-Package (SOP) Miniaturization of the Entire System. New York, NY, USA: McGraw-Hill, [12] Q. Chen et al., Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs), in Proc. IEEE 61st Electron. Compon. Technol. Conf. (ECTC), Lake Buena Vista, FL, USA, May/Jun. 2011, pp [13] V. Sundaram, Q. Chen, Y. Suzuki, G. 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Appl. Phys., vol. 114, no. 6, p , [23] K. L. Mittal, Silanes and Other Coupling Agents, vol. 4. Boca Raton, FL, USA: CRC Press, Qiao Chen received the B.S. and M.S. degrees in materials science and engineering from Tsinghua University, Beijing, China, in 2006 and 2008, respectively, and the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in His current research interests include the modeling, design, demonstration, and characterization of through-silicon-via and silicon interposers for 3-D integration. Hao Lu received the B.S. and M.S. degrees in Mechanical Engineering from the Huazhong University of Science and Technology, Wuhan, China. He is currently pursuing the Ph.D. degree in the School of Electrical and Computer Engineering, Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA. He is a Graduate Research Assistant with the 3D Systems Packaging Research Center, Georgia Tech. His main research interests include the multilayer redistribution layer design, fabrication, and signal integrity analysis for cost driven panel-based glass interposer. Venky Sundaram received the B.S. degree from IIT Mumbai, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA. He is currently the Director of Research and Industry Relations with the 3-D Systems Packaging Research Center, Georgia Tech. He is the Program Director of the Low-Cost Interposer and Packages Industry Consortium with over 25 active global industry members. He is a globally recognized expert in packaging technology, and the Co-Founder of Jacket Micro Devices, Livonia, MI, USA, and a RF/wireless startup acquired by AVX Corporation, Fountain Inn, SC, USA. He has authored over 100 publications and holds 15 patents. His current research interests include system-on-package technology, 3-D packaging and integration, ultrahigh-density interposers, embedded components, and systems integration research. Dr. Sundaram is the Co-Chairman of the IEEE Components, Packaging and Manufacturing Technology Technical Committee on High Density Substrates and the Director of Education Programs with the Executive Council of the International Microelectronics and Packaging Society. He has received several best paper awards. Rao R. Tummala (F 93) received the B.S. degree from the Indian Institute of Science (IIS), Bangalore, India, and the Ph.D. degree from the University of Illinois at Urbana Champaign, Champaign, IL, USA. He was an IBM Fellow, pioneering the first plasma display and multichip electronics for mainframes and servers. He is currently a Distinguished and Endowed Chair Professor and the Founding Director of the National Science Foundation s Engineering Research Center with the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA, pioneering Moore s Law for system integration. He has authored over 500 technical papers, the first modern book entitled Microelectronics Packaging Handbook, the first undergrad textbook entitled Fundamentals of Microsystems Packaging, and the first book introducing the system-on-package technology, and holds 74 patents and inventions. Prof. Tummala is a member of the National Academy of Engineering. He has received many industry, academic, and professional society awards, including the Industry Week s Award for improving the U.S. competitiveness, the IEEE David Sarnoff and Dan Hughes Awards from the International Microelectronics and Packaging Society, the Engineering Materials Award from ASM, and the Total Excellence in Manufacturing Award from the Society of Manufacturing Engineers. He was a recipient of the Distinguished Alumni Awards from the University of Illinois, IIS, and Georgia Tech, and the Technovisionary Award from the Indian Semiconductor Association and the IEEE Field Award for his contributions in electronics systems integration and cross-disciplinary education in He was the President of the IEEE Components, Packaging and Manufacturing Technology and the International Microelectronics and Packaging Society.