Frank Wei Disco Corporation Ota-ku, Tokyo, Japan

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1 Advances in panel scalable planarization and high throughput differential seed layer etching processes for multilayer RDL at 20 micron I/O pitch for 2.5D glass interposers Hao Lu, Fuhan Liu, Venky Sundaram, Rao Tummala 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta, GA, USA Frank Wei Disco Corporation Ota-ku, Tokyo, Japan Ryuta Furuya Ushio Inc. Yokohama city, Kanagawa Prefecture, Japan Atsushi Kubo Tokyo Ohka Kogyo Co., Ltd (TOK) Kawasaki, Kanagawa Prefecture, Japan Abstract This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate µm lines and spaces with 4-5 µm diameter photo-vias for multiple redistribution layers (RDL) at 20 µm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth need with lowest power consumption has enabled the application of 2.5D interposers for high density chip-to-chip interconnections. Silicon interposers with through-silicon-vias (TSVs) are capable of ultra-high density wiring between logic and memory chips, but use back end of line (BEOL) dual damascene processes, requiring chemical mechanical polishing (CMP), leading to high process cost, which limits their expansion into lower cost and higher volume applications. On the other hand, organic substrates processed on large panels have large capture pads for via landing due to their poor dimensional stability, limiting the bump pitch scaling at chip level. Glass interposers have been proposed to address the limitations of both silicon interposers and organic substrates in recent years. This paper reports on research to extend low cost and large panel semi-additive processes (SAP) to below 5um lines and vias. To achieve this, high resolution lithography processes combined with photosensitive dry film polymer dielectrics were optimized to form fine patterns and ultra-small micro-vias. A major challenge for multilayer RDL is the non co-planarity of copper electroplating, and a new cost-effective copper surface planarization process was proposed and evaluated for surface coplanarity improvement, leading to better yields for multi-layer RDL fabrication. Keywords RDL; SAP; 2.5D interposer; Planarization; Lithography I. INTRODUCTION High performance computing applications demand ultra-high bandwidth and low latency interconnections between logic and memory. The simplest approach to scaling bump pitch and integrating multiple devices on one substrate involves extending the wiring capacity of current organic substrates. Although significant advances have been made in developing such organic interposers, they are ultimately limited in scaling due to the poor dimensional and thermal stability, as well as the non-planar surface of organic laminate cores. The leading edge organic interposers by Kyocera have achieved 6µm lines and spaces (L/S) wiring and 50 µm bump pitch on low coefficient of thermal expansion (CTE) organic substrates [1]. To further increase the wiring density, wafer-based silicon interposers were developed. Xilinx used 65nm node back end of line (BEOL) processes to demonstrate 2.5D silicon interposers with 45µm interconnection bump pitch [2]. AMD s Fiji GPU was packaged on a 2.5D silicon interposer with four high bandwidth memory (HBM) stacks [3]. Each memory stack consisted of four memory chips and one controller chip, with a total of 1000 I/Os connecting to the GPU. The next generation HBM will stack 8 memory chips and result in more I/Os per stack. The silicon interposers used for GPUs with HBM utilized wafer level processes on 300 mm diameter wafers, and ultra-dense copper traces and microvias were formed by dual-damascene processes. Shinko demonstrated a thin film copper-polymer RDL process as an alternative to BEOL processes for silicon interposers [4]. This process used liquid spin-on dielectrics, sputtered metal seed layers, and chemical-mechanical polish (CMP) processes to achieve 1.6 µm pitch fine copper wiring on silicon interposers. The fabricated copper traces were typically narrower than the spaces, due to sidewall etch of copper traces during seed layer removal. Additionally, the CMP steps add significant cost to the multilayer RDL process. Although the 2.5D silicon interposers satisfy the I/O density requirements for current applications where organic substrates struggle, their relative high process cost limits their applicability to high end products only. Glass is similar to silicon in its dimensional and thermal stabilities as well as in its surface smoothness to facilitate ultra small wiring trace formation, but glass is superior in electrical performance due to its ultra-low loss and its high resistivity. Furthermore, glass is available in large panel form factors, reducing the cost by increasing the number of unit interposers per panel. Design, modeling, and fabrication of ultra-thin glass interposers with fine pitch through-package-vias (TPV) have been successfully demonstrated by Georgia Tech Packaging Research Center (PRC) [5, 6]. The insertion losses of TPVs in glass are lower than in traditional silicon interposers.

2 This paper presents the demonstration of µm multilayer re-distribution layers (RDL) wiring structures on glass interposer capable for 20 µm I/O pitch. The semi-additive process (SAP) for fabricating the demonstrator was advanced with high resolution dry film photoresist for smaller pitch wiring. The photosensitive dielectric with photo-vias is applied as an alternative solution for ultra-small micro-vias connecting multi-layer RDL. To improve the copper RDL thickness uniformity, a low-cost surface planarization process was introduced. A new differential seed layer etching chemistry was applied to improve the yield of the SAP method by minimizing copper side wall etch. As a result of the multiple process improvements listed above, the limit of low-cost SAP processes has been extended to below 5 µm in this research. II. PANEL-BASED HIGH RESOLUTION LITHOGRAPHY The photolithography process is a vital step for all semiconductor applications, for it dominates the critical dimension of both chip transistor size and its package minimum line and space. The resolution of the lithography for wafer level process has been developed to achieve less than 10 nm feature size for next generation microprocessors. However, the package substrate technology is another story. Most of the lithography machine designed for package substrate processes utilize I-line UV lamp for large field size exposure instead of 193 nm ArF excimer laser used for wafer level process. The state-of-the-art dry film resist (DFR) for panel-based lithography is struggling to achieve sub-micron resolution. Unlike high resolution liquid photoresist which thickness is tunable according to the spin speed while coating on the substrate, the DFR has limited choice of thickness. The typical thickness of high resolution DFRs are 7 µm, 10 µm, and 15 µm. For example, if 2 µm critical dimension is required, then with 7 µm DFR, the aspect ratio will be 3.5. Such high aspect ratio may lead to DFR collapse or bend even if the adhesion of DFR to the substrate is strong, affecting the yield of the whole panel, as shown in Figure 1. TABLE 1. UX PROJECTION LITHOGRAPHY TOOL SPECIFICATIONS [7] Resolution < 2µm L/S Effective exposure field 70mm x 70mm Wavelength 365nm (i-line) Depth of Focus (DOF) +/- 10µm Alignment accuracy <1µm Figure 2 shows the lithography result of liquid photoresist from TOK. The maximum resolution (1.5 µm) was achieved with proper optimization. However, the minimum feature size of 7 µm thick DFR was still 2 µm, same as showed in previous paper [7]. The advantage of DFR is its low cost compared to liquid photoresist, and capable of scaling to large panels. It can be imagined that if the thickness of the DFR further reduced in the future, better resolution can be achieved, greatly increasing DFR s potential for panel based advanced SAP. At current status, the only method to fabricate 1.5 µm critical dimension RDL is utilizing liquid photoresist. (a) Figure 1. Challenge of ultra-fine lithography for DFR The projection lithography tools are capable for high throughput step-and-repeat exposure for high-volume panel sized interposer manufacturing in the near future. In this study, a newly developed 7 µm thick DFR was tested with a projection aligner UX from Ushio Japan. This projection aligner was set up in Georgia Tech Package Research Center, with less than 2 µm resolution and 70 mm by 70 mm exposure area. The allowed depth of focus is +/- 10 µm for maximum resolution, which is critical accommodation for high resolution lithography on panels that do not have perfect co-planarity, especially for multi-layer panels. Table 1 shows the key specifications of UX in GT PRC [7]. (b) Figure 2. SEM image of liquid photoresist after development: (a) 1.5 µm to 3.5 µm line and space trench structure, (b) 1.5 µm line and space traces III. MICRO-VIA FORMATION WITH PHOTOSENSITIVE DIELECTRIC The common method of micro-via formation in organic package substrates utilizes CO 2 laser to drill µm diameter micro-via in polymer dielectric layers [8]. The CO 2 layer was widely used for this application for its low cost, high throughput, and various material compatibility. However, further decreasing via size was proved to be difficult due to the long wavelength of CO 2 laser (10.2 and 10.6 µm), and large focused laser beam size (60 µm). To form

3 smaller micro-via, the short wavelength solid state lasers and excimer lasers were being researched instead of CO 2 laser. The characteristic wavelength of Nd-YAG laser is 1064nm, and the third and fourth harmonic wavelengths are 335 nm and 266 nm, respectively. These ultraviolet (UV) lasers are capable to form smaller micro-vias than CO 2 laser due to the shorter wavelength and the small size of the focused beam. 20 µm diameter micro-via drilled by Nd-YAG laser [9] and less than 10 µm diameter micro-vias in thin polymer dielectric films ablated by excimer laser [10] have been reported. However, these small micro-via formation method require expensive tools for processing, leading to high product cost. Photo-vias are an alternative for micro-vias under 10 µm diameter connecting multi-layer RDL. The photo-via formation is similar to photolithography process, including UV exposure and development. The photosensitive polymer is the key for this approach, which is used as the dielectric layer. Since all photo-vias can be formed with as few as one shot, the throughput of this process is much higher than laser drilling. However, due to limited availability of high resolution dry film photosensitive materials and higher electrical loss than traditional dry film polymer, the photovias have not been widely applied for mass production, but limited in the research area. Even though the photo-vias have such disadvantages, the demand of small diameter micro-vias with ultra-fine pitch for interposers in the near future attracted the interest in developing advanced photosensitive materials. Shinko have demonstrated 10 µm diameter photo-vias for organic interposers using liquid photosensitive materials by single sided spin coating [11]. In this paper, the advanced dry film photosensitive polymers, IF4605, from TOK, Japan, were identified and the process optimized. The material properties are listed in Table 2. TABLE 2. PROPERTY OF DIELECTRIC MATERIAL IF4605 Tg 250 C Coefficient of thermal 45 ppm/ C expansion Young s modulus 1.64 GPa Dielectric constant 3.5 Thickness 5 µm Figure 3. 3-layer structure of dry film type photosensitive dielectric IF4610 The photosensitive dielectric IF4605 is similar to the DFR, which is a 3-layer structure shown in Figure 3, and the patterning is also similar to the photolithography process. It is also available in 10 µm thickness named IF4610. To fabricate the micro-via below 5 µm, The IF4605 was applied to reduce the aspect ratio of the via. The exposure tool was the same one used for photolithography process. The IF4605 was first laminated on the substrate and bake dried, then exposed in the project aligner with the designed via mask. After that, the substrate was post-exposure baked and developed in propylene glycol monomethyl ether acetate (PGMEA). The dielectric with formed photo-vias was then cured in the nitrogen oven at 200 C for an hour. The formed 5 µm photovia array before metallization is shown in Figure 4. This photosensitive dielectric series from TOK are compatible with our advanced SAP method using PVD copper seed layer. After copper metallization, the top view and cross-sectional view of 4 µm via arrays are shown in Figure 5. Figure 4. SEM image of 5 µm photo-via array before metallization Figure 5. Top view (left) and cross-sectional view (right) of metallized 4 µm photo-via array IV. COPPER RDL PLANARIZATION During the electrolytic plating step in our advanced SAP method, the plated copper thickness was related to the electrical current density, which was not constant across the whole panel due to variety of RDL design. The current density on large patterns was usually lower than on fine patterns, resulting in thinner thickness. However, when the pattern size was below 2 µm, the chemicals could be trapped in the narrow trench of photoresist. This lower fluidity could result in thinner copper structure than wide patterns, as shown in Figure 6. The build-up polymer layer on this uneven copper RDL followed up the thickness non-uniformity, leading to poor co-planarity of the substrate and negatively affecting the yield of lithography process for next layer fabrication. Figure 6. Uneven copper thickness after electrolytic plating The CMP process is utilized for polishing and planarizing the copper surface during wafer level processing, but too expensive for the low cost 2.5D glass interposers. In this paper, a cost-effective thinning and planarization method for

4 ductile materials using a diamond cutter on a spindle was investigated. This method can be applied to metals such as Au, Cu, and solders, polymer like photoresists, underfill materials, and passivation such as BCB and polyimide. The kinematics of the planarization tool is shown in Figure 7 [12]. A single bit of diamond was mounted on a spindle which rotates at high speeds during the process. This spindle s height was fixed, while the chuck table where the sample was held was slowly fed under the diamond cutter. The parallelism between the chuck table surface and diamond cutter rotating plane was precisely controlled to ensure 1 µm co-planarity. The unevenness of the sample would be shaved by the rotating diamond cutter. Such planarization process by diamond cutter is capable to planarize the free standing structure. The organic substrate with CCL was patterned and electrolytic plated for the preliminary test. The DFR was stripped, leaving the free standing copper structure to be planarized. The cross-sectional schematic of the samples is shown in Figure 8. The targeted copper pattern thickness was 5 µm. The top view and cross-sectional image of the comb structure after planarization is shown in Figure 9. The fine copper traces were deformed after planarization process, due to the shear force of the diamond bit during cutting. The larger traces (10 µm) showed less sign of deformation. Therefore, for planarization of fine line RDL, the support layer was required to prevent copper deformation. The second planarization test sample was fabricated on a 300 µm thick glass panel using our advanced SAP method. The process flow of improved planarization process is shown in Figure 10. The DFR thickness was 7 µm and the copper was over-plated, as shown in Figure 11. The DFR was functioning as the support layer for fine copper patterns. After planarization, the DFR was stripped and the copper seed layer was etched by spray etching machine using Atotech differential etchant called EcoFlash [13]. The cross-sectional images of the sample right after planarization and after seed layer etch are shown in Figure 12. No deformation of copper traces was observed. Figure 7. Kinematics of ductile materials surface planarization with Au metal bumps as an example [12] Figure 8. Schematic of copper planarization test sample Figure 10. Improved copper surface planarization process flow (a) Figure 11. Over plated copper escape routing structure at 3 µm line and 4 µm space, ready for surface planarization (b) Figure 9. Copper comb structure after surface planarization: top view of 5 µm and 6 µm line and space (a) and cross-sectional view of 5 µm line and space (b) and 10 µm line and space (c) (c) Figure 12. Cross-sectional view of 5 µm line and space copper traces after planarizaion with DFR and seed layer (left) and after DFR strip and seed layer etch (right)

5 Another improvement of this planarization process is that the copper surface roughness is greatly reduced after shaven by the diamond bit. During seed layer etch process, smooth copper surface will result in less copper trace etching due to the smaller surface area, which further improves the SAP method yield in addition to the differential seed layer etching. V. MULTI-LAYER RDL FABRICATION BY SAP The detailed processes described in the previous 3 sections were the improvement over traditional SAP method. The integrated advanced SAP flow for the second metal layer fabrication is shown in Figure 13. The second layer fabrication is somewhat similar to the first layer fabrication, except for the dielectric material and photo-via formation. The first metal layer fabrication was discussed in our previous paper [14] (Step 1). The dielectric layer with photo-vias were formed on the first metal layer by the processes described in Chapter III. The photosensitive dielectric IF 4610 was laminated on the glass substrate containing first metal layer (Step 2), and subjected to the UV exposure in the projection aligner UX mentioned above with the designed microvia mask. The post-exposure bake was required before development. After the development in PGMEA, the photovias were formed, exposing the copper capture pad in the first metal layer. Then the photosensitive polymer was thermal cured, followed by copper seed layer sputtering which covers both dielectric surface and via wall (Step 3). The next step was the high resolution lithography process discussed in Chapter II. The high resolution photoresist or DFR was coated or laminated on the substrate (Step 4), and exposed in the mask aligner with precise alignment followed by the development (Step 5). Once this is done, the second metal layer along with photo-vias was metallized by electrolytic Cu plating in a specialized chemistry from Atotech, and planarized by the surface planer described in the Chapter IV (Step 6). The photoresist was then stripped and the copper seed layer was etched by the differential etchant from Atotech [13]. Figure 14. The SEM image of via daisy chain structure at Step 5 in Figure 13. Via diameter is 5 µm with 20 µm pitch Figure 15. The metallized via daisy chain structure top view (left) and SEM cross-sectional view (right) Figure 14 shows the top view of the via daisy chain structure at Step 5 in the SEM using TOK liquid photoresist. The photoresist was fully open even in the vias after development. The via pitch is 20 µm and the diameter is 5 µm. The top view and cross-sectional view of metallized via and copper traces at Step 7 is shown in Figure 15. This demonstrator shows the capability of our advanced SAP for 20 µm via pitch multi-layer RDL fabrication on 2.5D glass interposers. VI. CONCLUSIONS In summary, this paper reports the improvement of panel based photolithography process, ultra-thin photosensitive dielectric polymer, and cost-effective surface planarization process, leading to advanced SAP capable of 20 µm bump pitch chip-level interconnections for 2.5D glass interposers. The resolution of 1.5 µm for liquid photoresist from TOK, 2 µm for DFR from Hitachi was achieved by Ushio projection aligner. The photosensitive dielectric from TOK was optimized to achieve 4 µm photo-via. The surface planer with diamond bit was utilized for substrate co-planarity improvement after electrolytic copper plating. The two metal layer daisy chain structure with photo-vias at 20 µm pitch was demonstrated. The approaches described in this paper are expected to increase the applicability of high density low cost 2.5D glass interposers. Figure 13. The SAP flow of second metal layer fabrication with photo-vias REFERENCES [1] Mitsuya Ishida, APX (Advanced Package X) Advanced Organic Technology for 2.5D Interposer, 2014 CPMT Seminar, Latest Advances in Organic Interposers, Lake Buena, Vista, Florida, USA, May 27-30, 2014 [2] Kirk Saban, Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity,

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