THE TREND to high I/O densities, performance, and

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1 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER Direct SMT Interconnections of Large Low-CTE Interposers to Printed Wiring Board Using Copper Microwire Arrays Xian Qin, Pulugurtha Markondeya Raj, Vanessa Smet, and Rao Tummala Abstract This paper reports compliant microwire copper arrays, in thin polymer carriers, as an innovative approach for direct surface mount technology (SMT) attach of large silicon, glass, and low coefficient of thermal expansion organic interposers to printed wiring boards (PWBs). The microwire arrays (MWAs) are prefabricated as free-standing ultrathin carriers using standard, low-cost manufacturing processes such as laser vias and copper electroplating. Such wire array carriers are then assembled in between the interposer and the PWB as a stress-relief interlayer. The MWA interconnections show low interconnection stress and strains even without the underfills. The approach is extensible to larger interposer sizes (20 mm 20 mm) and finer pitch (400 µm), making it suitable for smart mobile systems. The parallel wire arrays that form each joint result in low resistance and inductance, and therefore, do not degrade the electrical performance. The scalability of these structures allows extendibility to finer pitch and larger interposer sizes for high-performance applications. The finite-element method was used to design the MWAs to meet the thermomechanical reliability requirements. Computational models were built in 2.5-D geometries to study the reliability of 400-µm-pitch interconnections with a 100-µm-thick, 20 mm 20 mm silicon interposer that was SMT-assembled onto an organic PWB. The warpage, equivalent plastic strain, and projected fatigue life of the MWA interconnections are compared with those of the ball grid array interconnections. A unique set of materials and processes was used to demonstrate the low-cost fabrication of the MWAs. Copper microwires with 15 µm diameter and 50 µm height were fabricated on both sides of a 50-µm-thick thermoplastic polymer carrier using dry-film-based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB with SMT-compatible processes. Thermomechanical reliability of the interconnections was characterized by thermal cycling test from 40 C to 125 C. The initial fatigue failure in the interconnections was identified at 700 cycles, consistent with the models. Index Terms Connectors, electronics packaging, surfacemount technology. Manuscript received May 18, 2015; revised August 26, 2015; accepted September 21, Date of publication October 15, 2015; date of current version November 6, This work was supported in part by the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA USA, and in part by Qualcomm. Recommended for publication by Associate Editor C. J. Bailey upon evaluation of reviewers comments. (Corresponding author: Xian Qin.) The authors are with the Microsystems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA USA ( qinqqxian@gmail.com; raj.pulugurtha@ece.gatech.edu; vanessa.smet@prc.gatech.edu; rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT I. INTRODUCTION THE TREND to high I/O densities, performance, and miniaturization at low cost is driving the industry toward shrinking interposer design rules, similar to back end of line, requiring a new set of packaging technologies. Interposers of high-density wiring with 2 4 μm lithographic dimensions at μm off-chip interconnection pitches are projected for future generation of high-performance, smart mobile, and consumer systems. These applications require reduced thickness, short interconnection length, low cost, and direct-assembly onto system boards without any intermediate packages in-between. Most of today s packages are made of organic materials. They are widely available, readily processable, and cost efficient, but they are low-temperature materials with low Tg, resulting in poor dimensional stability at chip and board assembly temperatures around 260 C. The dimensional instability leads to layer-to-layer via-registration challenges, and thus to low I/O densities. In addition, they have poor thermal conductivity, resulting in poor heat dissipation. Their chip-to-package coefficient of thermal expansion (CTE) mismatch also limits scalability of the interconnection pitch. To address these limitations of standard organic substrates, low-cte organic, silicon, and glass interposers or packages are being explored by the industry and Georgia Tech (GT)-Packaging research center. Silicon and glass interposers are high-temperature materials and thus have excellent dimensional stability and matched CTE with ICs, thus allowing the formation of ultrahigh I/O density interposers [1]. Organic substrate manufacturers are also addressing this problem of CTE mismatch and dimensional stability with novel low-cte polymer composites that also have higher glass-transition temperatures (T g )[2]. These advances in low-cte interposers, however, pose interconnection reliability challenges when they are assembled directly on a printed wiring board (PWB) using solder joints, because of the now large mismatch in CTE between interposers (2.7 8 ppm/ C) and PWB (12 18 ppm/ C). Due to the environmental hazards and the associated restrictions (RoHS, WEEE, J-MOSS, etc.) with the use of lead-based solders, lead-free solders have been widely adopted worldwide in the semiconductor industry. Most of these lead-free solders, however, are known to be less ductile and more prone to fatigue. When the lead-free interconnections between the low-cte packages and boards are subjected to power IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 1710 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015 Fig. 1. (a) Copper MWA in a polymer carrier. (b) MWA as an SMTcompatible solution for reliable board-level interconnections. or thermal cycling, cyclic shear stresses are created in the solders, subsequently leading to fatigue failures. This problem is further aggravated with large-body-size interposers, required for multichip integration in memory-intensive high-bandwidth applications. CTE-mismatch-related reliability issues have been solved in the past at the IC-package level with silicon IC-to-organic package interconnections by a variety of methods such as by the use of organic underfills. However, underfilling is not an acceptable option for package-to-board interconnections, where reworkability after assembly is required. Current highdensity Si interposers use an intermediate organic ball grid array (BGA) package to address the board-level reliability challenge. This approach creates an additional package level and additional process steps, increases cost and thickness, and degrades the electrical performance. Therefore, there is an urgent need to investigate novel methods to address reliability challenges in direct surface mount technology (SMT) attach of low-cte packages to system boards. Large low-cte pin grid array and land grid array packages have been used by IBM [3] and others to connect very large low-cte, glass-ceramic Low temperature cofired ceramic modules of the same CTE as silicon to the system board. The reliability in this example was accomplished by compliant pins, but not by standard SMT. In research and development, multiple approaches have been reported in the literature, including the use of compliant metal springs or leads. Wide area vertical expansion structures by DiStefano et al. [4] utilize a flexible copper lead, surrounded by a compliant polymer, to interconnect the die and the substrate, thereby allowing relative movement between IC and package. The G-Helix compliant interconnect structure has been reported by GT, where a copper arch was used to achieve large compliance [5]. Flexible MoCr cantilevers, which can be released from the substrate by intrinsic stresses, are explored as compliant interconnections in-between chip and substrate [6]. Other than metal springs or leads, copper pillars are also widely investigated to replace solders for reliable interconnections at finer pitches [7], [8]. Another approach to address the CTE mismatch is to utilize stress-buffer structures such as polymer layers or air gaps. Reliable interconnections between low-cte glass interposers and PWB by compliant polymer stress-buffer layers Fig. 2. Top view of the 20 mm 20 mm interposer. was reported by the Packaging Research Center at GT [9], where thin polymer layers were used to decouple the stress in BGAs. GT has also reported the sea-of-leads technology, which utilizes compliant leads on a polymer layer with embedded air gaps to achieve flexible chip-to-substrate interconnections [10]. Double-solder ball chip-scale wafer-level packaging technology has been reported by IZM [11], where a second array of solder balls are stencil-printed or placed on top of an array of original solder balls, thus increasing their compliance. The bottom solder balls are embedded in the stress compensation layer, laminated onto the die. The ELAStec wafer-level packaging technology has been reported by Infineon and IZM, which uses printed silicone bumps as contacts [12]. In this paper, copper microwire arrays (MWAs) are proposed and demonstrated as a low-cost and SMT-compatible approach for direct SMT attach of large low-cte interposer, as shown in Fig. 1. A two-step process was developed to assemble the silicon interposers onto FR-4 PWBs through the MWAs. The joints on both the interposer side and the board side were simultaneously formed during reflow. The reliability of the interconnections was characterized by thermal cycling tests from 40 C to 125 C. II. FINITE-ELEMENT MODELING A20mm 20 mm silicon interposer, designed for mobile applications, and directly assembled onto an FR-4 PWB through MWA interconnections at 400-μm pitch, was modeled with ANSYS. A 2.5-D finite-element method (FEM) model was built and used to study the detailed structure of the assembly, and to achieve high calculation efficiency. Due to the half-symmetric nature of the geometry, a 400 μm 10 mm strip located in the geometrical center was modeled, as shown in Fig. 2. The strip considers 25 unit interconnections, each with a dimension of 400 μm 400 μm. The detailed structure of each unit for the initial setup is shown in Figs. 3 and 4. The silicon interposer thickness was assumed to be 100 μm, as commonly used for 2.5-D and 3-D architectures. The copper wires are held together by a 25-μm-thick polymer carrier, as shown in Fig. 4. On each side of the carrier, the wires are

3 QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1711 TABLE I MATERIAL PROPERTIES USED FOR FEM MODELING Fig. 3. Cross-sectional view of a single unit. Fig. 5. Bilinear isotropic hardening model for copper. Fig. 4. Detailed structure of the copper MWA interconnections. 50-μm long, and connected by a 230-μm diameter pad at the top, before they are soldered onto the interposer and PWB. Compared with directly soldering the wires, the additional pads provide more contact area and bonding strength, and also help prevent solder wetting onto the copper wires. The pads can be formed by mushroom plating during wires fabrication, without adding additional lithography steps. The wires are 10 μm in diameter, and are fully populated at 20 μm pitch in the 230-μm diameter pad area. Symmetric boundary conditions were applied at the right boundary of the strip. The assembly was subjected to a temperature drop from a stress-free temperature of 230 C to 25 C, emulating the SMT process, followed by three thermal cycles, each from 125 C to 40 C. The Von-Mises stress and the equivalent plastic strain range in each thermal cycle was calculated to assess the reliability of interconnections. Unified Anand s model was used to describe the viscoplastic behavior of SAC305 solder [13]. The material properties used for silicon and the FR-4 board are summarized in Table I. Bilinear isotropic hardening model was used for copper (as illustrated in Fig. 5), where the modulus is 121 GPa and the yield stress is Mpa. Based on the fabrication constraints from packaging processes, the aspect ratio of the wires was limited to 5 in the modeling, with 10 μm diameter and 50 μm height on both sides. Higher aspect ratio of the wires offers greater compliance, though they increase the complexity of fabrication. By fabricating the copper wires with aspect ratio of 5 on both sides of the carrier, a total aspect ratio of 10 is achieved for the MWA interconnections. III. FINITE-ELEMENT MODELING THE EFFECT OF POLYMER CARRIER The polymer carrier not only acts as a mechanical holder of the copper wire arrays, but also introduces an anchor point and affects the strain distribution along the wires. The effect of the polymer carrier s CTE and modulus on the reliability of MWA interconnections was studied by finite-element modeling. Fig. 6 shows how the CTE and modulus of the carrier affect the maximum nodal strain in both the copper wires and the solders. The solid lines show the strain in solders, while the dashed lines show the strain in copper wires. In this paper, the dimension of the copper wires and the material properties of other materials were kept constant. The CTE values studied were 20, 40, and 60 ppm/ C, and the modulus values were 1, 2, and 3.5 GPa. It can be observed that the strain in the copper wires reduces with the decrease in the CTE of the carrier, and the higher the modulus of the carrier, the higher the reduction rate. Therefore, a stiffer carrier with low-cte corresponds to low strain in the copper wires.

4 1712 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015 Fig. 8. Volume averaged strain over the elements sharing the node with largest nodal strain for fatigue life prediction. Fig. 6. Effect of the mechanical properties of the polymer carrier on the strain in solder joints. TABLE II EQUIVALENT PLASTIC STRAIN RANGE AND PROJECTED FATIGUE LIFE FOR MWA&BGAINTERCONNECTIONS Fig. 7. Geometry of the BGA model. As shown by the solid lines, when the modulus of the carrier increases from 1 to 3.5 GPa, the strain in the solder joints also increase. The CTE of the carrier has a less significant effect on the strain values in the solder, compared with that in the copper wires. The polymer properties that correspond to lower strain in copper wires also lead to higher strain in the solder joints. Interconnection failure is defined by either failure of copper wires or that of solder joints, whichever comes first. Therefore, an optimized design is achieved when the fatigue life of copper wires and solder joints are close to each other, and both exceeds 1000 cycles. The solution was found when the modulus of the polymer carrier is 7.5 GPa and the CTE is 20 ppm/ C. The fatigue performance of the interconnections with the selected polymer properties is discussed in detail in Section IV. IV. FINITE-ELEMENT MODELING RESULTS AND ANALYSIS The reliability performance of the copper MWA was compared with standard BGA interconnections, using response parameters such as warpage of the silicon interposers, equivalent plastic strain in the interconnections and the projected fatigue life. The same dimensions for the silicon interposer and board were applied in the BGA model, as shown in Fig. 7. Standard SAC305 solder balls of 250-μm diameter were used for BGA interconnections at 400-μm pitch. The same boundary conditions and loading profiles were applied for both baseline BGA and MWA models. At the end of the thermal cycles, the silicon interposers showed a concave down warpage for both types of interconnections, since the FR-4 PWB shrank more than the silicon, as the assembly cooled from reflow temperature to room temperature. At 20-mm interposer size, the warpage was 0.16 mm with microwire interconnections, and 0.19 mm with BGA interconnections. Larger warpage negatively affects the integrity of the vias and redistribution layers in the interposer, as well as of the reliability of the chip-to-interposer interconnections. Coffin Manson models were applied for both copper and solder to estimate the fatigue performance of the interconnections. Several damage metrics have been previously reported for fatigue life prediction, such as accumulated plastic strain per cycle, plastic strain range per cycle, accumulated creep strain per cycle, strain energy density per cycle, creep strain energy per cycle among others [14] [16]. In this paper, the elemental averaged equivalent plastic strain range in each thermal cycle was chosen as the damage metric. The elemental strain is the volume average of the strain in the elements that share the same node in which the maximum nodal strain occurs, as illustrated in Fig. 8. Equations (1) and (2) describe the low-cycle fatigue of both SAC305 and copper [17], [18], in which ɛ f is a material-related constant, with the value of

5 QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1713 Fig. 9. Strain contours in (a) copper microwire interconnections and (b) BGA interconnections and for solder and copper, respectively. Fig. 9 shows the strain contour of both interconnections: in the MWA interconnection, the deformation is distributed between the copper wires and the solders, while in the BGA interconnection, the deformation is solely accommodated by the solder joints. Table II shows the strain range and projected fatigue life for both interconnections. In the MWA interconnections, the first failure is predicted to be in the solder joint on the interposer side, with a fatigue life of 1158 cycles, and the copper wires are predicted to survive more than 1450 cycles. The geometry parameters of the interconnection structure can be further optimized to balance the strain distribution between copper wires and solder joints to achieve lower strain in solders at the cost of higher strain in copper. The fatigue life of BGAs is predicted to be 719 cycles, which is much lower than that of the MWA interconnections ( 2ɛ f N f solder = 0.5 γ p ( ɛ 0.75 f N f copper = γ p ) (1) ) (2) V. TEST VEHICLE DESIGN AND FABRICATION Silicon interposers (600 μm thick), FR-4 PWBs (800 μm thick), and copper MWAs in polymer carriers were designed and fabricated for assembly and reliability tests. The silicon interposers have 1 layer of copper traces (10 12-μm thick) built with semiadditive process, and silicon nitride as passivation layer. Solder mask defined design was used for the silicon interposer, where the diameter of copper pad is 344 μm and that of passivation is 225 μm. Electroless nickel and immersion gold was used as surface finish. The board has 1 layer of copper traces patterned by an etch-back method, while solder mask was used for the passivation, and Organic solderability preservative as the surface finish. Nonsolder mask defined pads design was used for the board, where the pad diameter is 231 μm, and the passivation opening is 344 μm. The boards and interposers have matched daisy chain designs to test the integrity of the interconnections. The daisy chain is designed with 90 rotational symmetry, 5 daisy chains in each quarter, and 20 daisy chains in each test vehicle. The key attribute of this innovative SMT technology is the use of a prefabricated MWA stress-relief insert, illustrated in Fig. 1(a). Syron 7000 films were chosen as the carrier material based on the modeling results. It is a thermoplastic substrate material, with a modulus of 8.6 GPa and CTE of 18 and 23 ppm/ C in the two in-plane directions, which are close to the guidelines recommended by modeling. To fabricate copper wires of high aspect ratio with low-cost packagingcompatible processes, multiple photoresist candidates were evaluated. A 25-μm-thick dry-film photoresist from Hitachi Chemical was shown to have the best performance for highaspect-ratio features. Two layers of photoresist are applied on both sides of the carrier to achieve 50-μm stand-off height of the electroplated wires. The diameter of the wires is designed to be 15 μm for the initial proof-of-concept samples. The fabrication process flow is shown in Fig. 10. Copperfilled vias were formed in the Syron carrier as the current path in between the wires on both sides. Continuous copper posts, other than the individual wires as shown in the modeling, were used in the carrier, for ease of via formation and alignment of wires onto the posts. CO 2 laser was used to process the vias with 225 μm diameter in the Syron film. The vias were metallized by bottom-up electrolytic plating. Lithography of microwire pattern was performed on both sides of the carrier, followed by electrolytic plating to build the copper wires. Copper pads were formed on the top of the wires by overplating, which help prevent solder wetting along the wires during reflow. Eutectic 96.5Sn3.5Ag alloy was coplated on the top of the copper pads for assembly. SAC305 solder was used in the modeling, since it is widely used for the board-level interconnections, but SAC305 cannot be coplated. The cross section of the MWA interconnections is shown in Fig. 11. The process is compatible with standard high-volume SMT assembly, making it a manufacturable and cost-effective approach for reliable board-level interconnections of silicon, glass, and low-cte organic interposers. VI. ASSEMBLY AND RELIABILITY CHARACTERIZATION The assembly was carried out with a semiautomated flip-chip bonder (Finetech Matrix Fineplacer), with a placement accuracy of ±3 μm. A two-step process was developed

6 1714 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015 Fig. 10. Process flow for fabrication of copper MWA interconnections. Fig. 11. Cross section of the interconnections before assembly. to assemble the silicon package to the PWB through MWA interconnections, as shown in Fig. 12. The first step is to place the MWAs onto the board [Fig. 12(a)] using a vacuum-locked 20 mm 20 mm gimbal tool. The Syron carriers with copper wires and solder bumps plated on both sides had significant warppage. Tacky flux (ALPHA NCX-FD) was applied onto the board to hold down the carrier. ALPHA NCX-FD flux is a no-clean flux that does not leave residues, and is compatible with leadfree applications that require higher reflow temperatures. The amount of flux has to be carefully controlled to avoid heavy degassing, which may cause voiding in the solder joints. An external force was also applied to offset the warpage of the carrier and the noncoplanarities of the solders. The applied force was limited to below 5 N to avoid damaging the soft solder caps. The silicon package was then picked up with a10mm 10 mm flat tool head, aligned onto the MWA interconnections, and pressed on top with a 5 N placement force. The same flux was also applied on the silicon interposer to remove oxide and promote bonding between the solder and the pads on the interposer. The joints on both sides were simultaneously formed during reflow of the solder, with the peak temperature at 260 C. The cross section of the assembly is shown in Fig. 13. Warpage of the Syron carrier and noncoplanarity of the solder bumps were identified as major challenges for assembly yield. The warpage of the Syron carrier is caused by the following.

7 QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1715 Fig. 12. Two-step assembly process. (a) Placement of the MWA interconnections onto the PWB. (b) Placement of the silicon package, and reflow. Fig. 13. Cross section of silicon package-mwa-pwb assembly. 1) The low thickness and modulus of the polymer material, which made the stand-alone film prone to deformation during the fabrication process. The deformation induced in the polymer film further affected the contact between the polymer and the mask during lithography, and caused non-ideal development and resist residues in certain areas. The adhesion of the plated wires in these areas was weak, which resulted in wires falling off during resist stripping and therefore missing interconnections, as shown in Fig ) The asymmetry in the structure on both sides of the polymer film, which is induced by both the missing bumps and unbalanced copper and solder plating. Noncoplanarities are primarily caused by the nonuniform current distribution in both copper and solder plating processes. The difference in copper plating rates generated mushroom pads of different diameters and thicknesses, which later on affected the plating rates of solder on these copper pads. The plating nonuniformity of the solder itself further exaggerated the issue. The process control to achieve symmetric structures on both sides of the polymer carrier is the key to mitigate warpage and to improve the yield of the assembly, which further eliminates premature failures caused by imperfect bonding during the thermal cycling test. Missing solder bumps is another cause of package distortion and misalignment during assembly. Regardless of the defects described above, the daisy chains yielded well in locations where the polymer carrier was comparatively flat with uniformly plated solder caps. Thermal cycling test was used to characterize the reliability performance of the MWA interconnections by tracking the Fig. 14. Missing interconnections caused by process defects. resistance of the yielded daisy chains. The temperature range was 40 C 125 C, with 15-min dwell time at each temperature extreme, at a rate of 1 cycle/h, as per JEDEC standard (JESD22-A104D, type G). The resistance of each daisy chain was measured every 50 cycles. The daisy chain resistance readings are shown in Fig. 15(a). A dramatic increase in the resistance was detected between 700 and 800 cycles. The locations of the failed daisy chains are shown in Fig. 15(b). The earliest failure was identified in one of the corner daisy chains (#7), while dc #13 and #14 are longer chains which are located more toward the inner area. The interconnections at the corners have larger distance to the

8 1716 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015 Fig. 15. (a) Resistance of the daisy chains during thermal cycling test. (b) Location of the failed daisy chains. Fig. 16. Cross section of failed MWA interconnections. neutral point compared with the inner ones, and experience larger strains during thermal cycling, and are consequently expected to experience earlier failures. The sample was cross-sectioned for failure analysis, as shown in Fig. 16. The solder joints in Fig. 16 are the edge joints located in dc #13 [Fig. 15(b)]. The solder on the interposer side showed fatigue cracks, which propagated along the diagonal direction. Two reasons may have contributed to the way the cracks propagate. The first one is the warpage of the carrier itself, which pulled the solder joints in the vertical direction. The second reason is the imperfect alignment between the solder and the capture pads on the interposer (shown in Fig. 16), which caused necking in the joints and accelerated crack initiation. The imperfect alignment is mainly

9 QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1717 Fig. 17. Comparison of the refined model and the original model. driven by the warpage of the carrier, which made it difficult to focus and align during assembly. The fatigue failure initiated from the solder joints on the interposer side, which agrees with the larger strains on the interposer side compared with that on the board side, as suggested by modeling. VII. ANALYSIS AND DISCUSSION OF MODEL-TO-EXPERIMENT CORRELATIONS The geometry and material parameters typically deviate from the design because of processing compromises and material availability. This section analyzes the critical parameters in the fabricated samples that are different from the original design, and discusses the effect of these parameters on the reliability of interconnections. A. Change in Geometry Parameters 1) Change in Silicon Thickness: In the original design, the thickness of the silicon interposer is 100 μm, representing the typical thickness for 2.5-D and 3-D architectures. In the fabricated samples, however, the packages are not thinned and have a thickness of 600 μm. This larger silicon thickness increases the rigidity of the interposer, and results in larger strains in the interconnections. In the refined model, the interposer thickness was changed to 600 μm. 2) Change in Carrier Thickness: The polymer carrier is 25 μm thick in the original design, while the commercially available Syron material has a thickness of 50 μm. The larger carrier thickness helped handling of the polymer during processing and the control of warpage and deformation, but restricted the deformation of the wire arrays and increased the strain in the solder joints. 3) Change in Wire Diameter: The wires were initially designed to have a 10 μm diameter. However, a mask with 15-μm openings was used for lithography to help improve the yield of the wires. The average wire diameter after seed layer removal was found to be around 12 μm. Larger wire diameters reduced the aspect ratio of wire array and decreased the compliance. Diameter of 12 μm was used in the refined model and the same element size was applied for both models. B. Change of Solder Material The solder material used in the original models was SAC305, as it is one of the most popular lead-free solders for reliable board-level interconnections. However, SnAg eutectic solder (96.5Sn3.5Ag) was used in the samples for processing convenience. The two solder materials have different viscoplastic behaviors and fatigue performance. The Anand model for 96.5Sn3.5Ag reported by Wang et al. [19] was used in the updated model. The low-cycle fatigue performance of 96.5Sn3.5Ag was studied by Kanchanomai et al. [20] in detail. Their ductilitymodified Coffin Manson relationship was used for fatigue life prediction of the solder joints, as shown in the following equation. D is the fracture ductility, which equals to 1.6 for 96.5Sn3.5Ag solder. α and θ are material constants, which are 1.07 and 13, respectively. The snapshot of the refined model and how it compares to the original model is shown in Fig. 17 ( ) εp N α f = θ. (3) 2D The same boundary conditions and loading profiles were applied in the refined model. The maximum elemental plastic strain range per cycle was calculated for fatigue life estimation. The calculated strain and fatigue life for both solder joints and copper is shown in Table III. Due to the combination of thicker silicon packages and larger wire diameter, the strains in the interconnections are larger than that shown in the initial design. With the refined model, the estimated fatigue life is 801 cycles, defined by the failure in the solders. As discussed previously, fatigue failures were detected in one of the corner daisy chains at 700 cycles. The model was able to describe the performance of the interconnections well, in spite of other parameters such as misalignment, intermetallic compounds, and solder voids that were not considered in the models but are expected to degrade the fatigue life. The models are therefore validated by the experiment. The major factor that led to the decrease in fatigue life is the thick silicon. With thinner packages, such as the ones used in today s 2.5-D and 3-D architectures, the MWA interconnections are expected to survive more than 1000 cycles in accelerated test for package sizes up to 20 mm 20 mm. VIII. CONCLUSION The trend toward high I/O density, ultraminiaturization and high performance has heralded a new era of low-cte silicon, glass and organic interposers. However, the CTE mismatch between these interposers and PWBs creates new major reliability concerns at board-level interconnections. A new set of interconnection technologies that are SMT-compatible and manufacturable are, therefore, required. In this paper, an innovative compliant copper MWA concept was explored to meet this need. The FEM was used to analyze the reliability performance of the copper microwire interconnections to provide guidelines for design of the MWA structure. The warpage, equivalent plastic strain, and projected fatigue life were compared with standard BGA interconnections. At the same interposer size and interconnection pitch, the copper MWAs showed lower

10 1718 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 11, NOVEMBER 2015 TABLE III MWA FATIGUE LIFE CALCULATION WITH THE REFINED MODEL warpage, lower plastic strain, as well as longer fatigue life than standard BGA interconnections. A low-cost approach was used to fabricate the copper microwire interconnections using standard photolithography and plating processes. A two-step assembly process was developedto assemble 20 mm 20 mm silicon interposers onto FR-4 PWBs with MWA interconnections. The reliability performance was assessed by thermal cycling tests from 40 C to 125 C. Initial fatigue failures were identified at one of the corner daisy chains at 700 cycles. The finite-element models were further refined based on the geometry and material parameters used in the fabricated samples. Good correlation between modeling and experimental data was achieved with the refined models. The models were therefore validated by reliability characterization. With thin low-cte interposers or packages, the compliant MWA interconnections are expected to survive more than 1000 cycles, as predicted by the models. The MWA concept is thus demonstrated as a highly reliable and SMT-compatible interconnection solution for direct attach of large low-cte interposers. ACKNOWLEDGMENT The authors would like to thank the industry mentors Dr. U. Ray and Dr. J. Lee from Qualcomm for their active guidance, suggestions, and support of this work. They would also like to thank Rogers Corporation for providing polyimide materials and Atotech Germany for their support with solder alloy plating. REFERENCES [1] R.R.Tummalaet al., Trend from ICs to 3D ICs to 3D systems, in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2009, pp [2] M. Miyatake et al., Newly developed ultra low CTE materials for thin core PKG, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [3] J. U. Knickerbocker et al., An advanced multichip module (MCM) for high-performance UNIX servers, IBM J. Res. Develop., vol. 46, no. 6, pp , Nov [4] T. H. DiStefano, J. W. Smith, Z. Kovac, and K. Karavakis, Compliant microelectronic mounting device, U.S. Patent , Jan. 6, [5] Q. Zhu, L. Ma, and S. K. Sitaraman, Compliant off-chip interconnects, U.S. Patent , Aug. 31, [6] I. Shubin et al., A package demonstration with solder free compliant flexible interconnects, in Proc. 60th Electron. Compon. Technol. Conf. (ECTC), Jun. 2010, pp [7] T. Wang, F. Tung, L. Foo, and V. Dutta, Studies on a novel flip-chip interconnect structure Pillar bump, in Proc. 51st Electron. Compon. Technol. Conf., May/Jun. 2001, pp [8] V. S. Rao, A. A. O. Tay, V. Kripesh, C. T. Lim, and S. W. Yoon, Bed of nails 100 microns pitch wafer level interconnections process, in Proc. 6th Electron. Packag. Technol. Conf. (EPTC), Dec. 2004, pp [9] X. Qin, N. Kumbhat, V. Sundaram, and R. Tummala, Highly-reliable silicon and glass interposers-to-printed wiring board SMT interconnections: Modeling, design, fabrication and reliability, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [10] M. S. Bakir, H. A. Reed, P. A. Kohl,K.P.Martin,andJ.D.Meindl, Sea of leads ultra high-density compliant wafer-level packaging technology, in Proc. 52nd Electron. Compon. Technol. Conf., 2002, pp [11] M. Topper et al., Wafer level package using double balls, in Proc. Int. Symp. Adv. Packag. Mater., Process., Properties Interf., Mar. 2000, pp [12] R. Dudek et al., Thermomechanical design for reliability of WLPs with compliant interconnects, in Proc. 7th Electron. Packag. Technol. Conf. (EPTC), vol. 1. Dec. 2005, pp [13] M. Motalab et al., Determination of Anand constants for SAC solders using stressstrain or creep data, in Proc. 13th IEEE Intersoc. Conf. IEEE Thermal Thermomech. Phenomena Electron. Syst. (ITherm), [14] J. Pang, B. S. Xiong, and T. H. Low, Comprehensive mechanics characterization of leadfree 95.5 Sn 3.8 Ag 0.7 Cu solder, Micromater. Nanomater., vol. 3, pp , [15] A. Schubert, R. Dudek, E. Auerswald, A. Gollbardt, B. Michel, and H. Reichl, Fatigue life models for SnAgCu and SnPb solder joints evaluated by experiments and simulation, in Proc. 53rd Electron. Compon. Technol. Conf., May 2003, pp [16] J. H. Lau, D. Shangguan, D. C. Y. Lau, T. T. W. Kung, and S. W. R. Lee, Thermal-fatigue life prediction equation for wafer-level chip scale package (WLCSP) lead-free solder joints on lead-free printed circuit board (PCB), in Proc. 54th Electron. Compon. Technol. Conf., vol. 2. Jun. 2004, pp [17] D. Shangguan, Lead Free Solder Interconnect Reliability. Materials Park, OH, USA: ASM International, [18] R. Iannuzzelli, Predicting plated-through-hole reliability in high temperature manufacturing processes, in Proc. 41st Electron. Compon. Technol. Conf., May 1991, pp [19] G. Z. Wang, Z. N. Cheng, K. Becker, and J. Wilde, Applying Anand model to represent the viscoplastic deformation behavior of solder alloys, J. Electron. Packag., vol. 123, no. 3, pp , [20] C. Kanchanomai, Y. Miyashita, and Y. Mutoh, Low-cycle fatigue behavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi lead-free solders, J. Electron. Mater., vol. 31, no. 5, pp , May 2002.

11 QIN et al.: DIRECT SMT INTERCONNECTIONS OF LARGE LOW-CTE INTERPOSERS TO PWB 1719 Xian Qin received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, and the Ph.D. degree in materials science and engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in She focused primarily on reliability of board-level interconnections with the 3-D Systems Packaging Research Center, Georgia Institute of Technology, during her thesis research. She is involved in modeling, design, fabrication, and reliability characterization of compliant interconnections. Pulugurtha Markondeya Raj received the B.S. degree from IIT Kanpur, Kanpur, India, in 1993, the M.S. degree from the Indian Institute of Science, Bangalore, India, in 1995, and the Ph.D. degree in ceramic engineering from Rutgers University, New Brunswick, NJ, USA, in He co-developed several technologies, which include low-cost capacitor and inductor integration, advanced thin film precision analog and RF components with nanomagnetic and nanocomposite dielectrics, and their package integration as functional modules. He is currently a Research Professor and Program Manager for the Power and RF Functional Components and Modules Program with the 3-D Systems Packaging Research Center (PRC), Georgia Institute of Technology, Atlanta, GA, USA. At PRC, he provides leadership in the areas of power-supply component integration on silicon, glass, and organic substrates for power conversion and integrity, RF and precision components (antennas, diplexers, matching networks, and nonlinear devices), and finepitch interconnections. He has co-authored 215 publications, eight books, and eight patents with others pending. Dr. Raj received 15 best paper awards for his conference and journal publications that include the Distinguished Scholar Award from the Microbeam Analysis Society, the IEEE TRANSACTIONS ON ADVANCED PACKAGING Commendable Paper Award, the IEEE Outstanding Technical Paper Award, the IEEE ECTC Best-Poster Award, and the Philips Best Paper Award. He is the Co-Chair of the IEEE CPMT Nanopackaging Technical Committee, and the Track Chair of Nanopackaging at the IEEE NANO Conference. He is also the Co-Chair and served as the Session Chair of the High- Speed, Wireless and Components thrust in the Components, Packaging and Manufacturing Technology Conference and the Electronics and Component Technology Conference. Vanessa Smet received the B.S. degree in applied physics from the École Normale Supérieure de Cachan, Cachan, France, the M.S. degree in applied physics from the University of Paris XI, Orsay, France, and the Ph.D. degree in electrical engineering with a minor in reliability assessment of power modules from the University of Montpellier 2, Montpellier, France. She was a Post-Doctoral Researcher with the Tyndall National Institute, Cork, Ireland, where she was involved in novel high-temperature high-power die-attachment solutions for power chips and µbga assembly. She is currently a Research Scientist and Program Manager for the Interconnections and Assembly Program with the 3-D Systems Packaging Research Center, where she focuses on ultrafine pitch first-level interconnections and microelectromechanical systems (MEMS) packaging. Her current research interests include power electronics, thermomechanical modeling, 3-D integration, interconnections, assembly processes (flip-chip, thermocompression, and SLID), and MEMS packaging. Rao Tummala was the Director of Packaging with IBM, Armonk, NY, USA. He is currently the Joseph M. Pettit Chair Professor and Director of the 3-D Systems Research Center with the School of Electrical and Computer Engineering and Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA, USA. He is also the Founding Director of the first National Science Foundation Engineering Research Center in the U.S. He is a World Renowned Packaging Expert and has developed several major technologies from concept to manufacturing, including the industry s first 100-chip ceramic modules, first plasma display, and thin film magnetic storage devices for which contributions he was named an IBM Fellow.