Comparison of Missing Metal Defect Formation on He In-Situ and Furnace Annealed Electroplated

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1 Comparison of Missing Metal Defect Formation on He In-Situ and Furnace Annealed Electroplated Copper Films Yasmin Abdul Wahab 1, Anuar Fadzil Ahmad 2 and Zaiki Awang 1 1 Microwave Technology Centre, Faculty of Electrical Engineering, Universiti Teknologi MARA, Shah Alam, Selangor, Malaysia 2 Silterra Malaysia Sdn. Bhd., Kulim, Kedah, Malaysia Abstract- Copper electrochemical plating (ECP) has contributed to a significant rise in both systematic and random defects. A missing metal defect is a critical problem for the 0.13 μm node and normally will only be detected after chemical-mechanical polishing (CMP). Meanwhile, this defect is also strongly dependent on post-electrochemical plating. In addition, Cu films characteristics depend critically on anneal, plating conditions and bath chemistry. This paper presents a comparison of missing metal defect formation on samples annealed using furnace versus He in-situ anneal. All copper deposition and He in-situ anneal processing was performed on the Applied Materials SlimCell TM ECP system. A post-ecp He in-situ anneal processing was carried out over a 60º C to 180º C temperature range, with anneal duration times ranging from 6 s to 2 hours. In the He in-situ anneal process, the wafers began to be ramped at over 100 º C with less than a minute soak time. For the furnace anneal, the wafers were loaded for almost an hour with less than 200 o C soak temperature. After the annealing process, Cu CMP partial polish was applied as a final step before analyzing the wafers with scanning electron microscope (SEM). Our conclusion is that the missing metal defect levels for furnace and He in-situ anneal are found to be comparable and have no correlation with reflectivity or stress. In this paper we compare the capabilities and performance of different types of annealing processes and their impact on missing metal defect (MMD), an in-line technique developed to reduce total defect count. We will also present correlations of these defects to plating and anneal process parameters. Keywords: Copper electrochemical plating, missing metal defect, He in-situ anneal, furnace anneal, chemical-mechanical polishing. I. INTRODUCTION With the rapid adoption of Cu metallization as the metal interconnect in nanotechnology and high-speed/radio frequency integrated circuits, Cu dual damascene technology is gaining momentum because of the higher electrical conductivity and electromigration resistance of Cu. During some stages of wafer processing, defects arise gradually depending on the level and process step implemented in the back end of line (BEOL). A missing metal defect has been a major problem in Cu dual damascene (CuDD) technology and is normally seen after /06/$ IEEE 53 CMP. This problem, as well as electromigration (EM) and stress migration (SM) reliability strongly depends on postelectrochemical plating (ECP) Cu film grain size, orientation, and intrinsic stress in patterned structures [1]. In fact, missing metal (or commonly known as a Cu void) has been indirectly affecting yield enhancement process. In many cases it has been observed that void defects of Cu thin films mainly yield killers and seriously degrade the reliability of interconnects [2]. This paper investigates the formation of missing metal defect for He in-situ and furnace annealed electroplated Cu films. The objective is to identify critical defects buried in the Cu film after applying different types of annealing process. II. EXPERIMENTAL DETAILS Blanket 200 mm Si wafers were used for the inspection of missing metal defect and other post-plating defects. TaN x /Ta barrier layers of Cu seed were deposited using a 200 mm Barrier Seed Endura physical vapor deposition (PVD) system that utilizes a hollow cathode magnetron. Pre-stress of seed layer was studied before the plating step. A set of wafers was annealed in separated lots using furnace, and the other set was put through the He insitu anneal located at the plating system tool. The post-stress and reflectivity of the plated Cu layer were then recorded. As a final stage of missing metal qualification, a Cu CMP partial polish was employed before both sets of wafers underwent particle scan check prior to plating defect monitoring. Detailed review and classification of all defects on each processed wafers was carried out using a scanning electron microscope (SEM), to build up a defect pareto chart for each wafer. On top of that, SEM images of missing metals were captured and selected defects were examined by SEM images of cross sections created by focused ion-beam (FIB). As a part of the defect inspection and classification system, the classification codes and SEM images for every individual defects were automatically downloaded into a defect database system after the wafers were reviewed. In addition, the number and distributions of the defects at the end of polishing step would be available for post-defect review analysis.

III. RESULTS and DISCUSSION A. Process Parameter Comparison The results of the process parameter comparison between furnace and He in situ anneal are presented in Fig. 1.

2 III. RESULTS and DISCUSSION A. Process Parameter Comparison The results of the process parameter comparison between furnace and He in situ anneal are presented in Fig. 1. Analysis of stress and reflectivity shows a significant difference in both process parameters between the two annealing conditions. To further improve the results in terms of significance difference a value, a T-test has been implemented in one-way analysis by anneals. The results shown in Fig. 1 seem to indicate that high stress in the He in-situ anneal occurred because of the faster ramp rate. In integrated circuits, the difference in thermal expansion between the metal film or line and the neighboring materials gives rise to high stress during the fabrication process, resulting in stress-induced damage, such as voids or grooves [3]. Meanwhile, the high reflectivity observed in furnace-annealed samples is probably due to different grain size and Cu oxidation. The grain size in as-deposited Cu films is small but starts to grow after deposition and this increased further in samples annealed at higher temperatures. Atoms are loosely packed in the grain boundaries, so the grain growth densifies the film and introduces tensile stress. Numerous decreases in the grain boundary energy can compete with the increase in the strain energy and directly influence the growth of the grains against stress [4]. In other words, high densities of grain boundaries and immediate re-crystallization after electrochemical plating lead to unstable grain structures. In post Cu electroplating, annealing plays a key role in the process, as it impacts layer properties such as grain size, re-crystallization, texture and internal stress. The furnace and He in-situ anneal temperature profile are displayed in Fig. 2. The temperature profile for the furnace shows that the wafers were loaded onto zone 1 with less than 5 º C per min ramp up and for the He in-situ, the wafers were ramped about 30 º C per minute. The temperature reached a maximum point and then was ramped down at the end of the pre-cool step. The wafers cooled down at the end of cool recipe. 200 (a) Figure 1: Box and Whisker Plot comparison between furnace and He in situ anneal for the formation of missing metal defects (a) Analyses of stress by anneal Analyses of 480 nm by anneal. MMD Qual lot loaded to zone 1. Helium ON ( a) Helium ON T=0 T=1 T=2 min /06/$ IEEE 54 T2 T3 T4 T8 T9 T10 T14 T15 T16 Figure 2: (a) Furnace temperature profile He in situ temperature profile

The temperature ramp rates of a furnace are limited by the onset of plastic deformation of silicon wafers.

The comparison of the defect counts per wafer in furnace versus He in-situ anneal is shown in Fig. 3.

3 The temperature ramp rates of a furnace are limited by the onset of plastic deformation of silicon wafers. During a transient wafer heating or cooling process, a non-uniform temperature distribution on a wafer surface produces thermal stresses and dislocations will be induced if the yield strength of silicon is exceeded [5]. B. Defect Comparison of Furnace versus He in-situ Samples Missing metal defect is related to electroplating process, and is one of the most commonly seen defects in electro-plated Cu films. The comparison of the defect counts per wafer in furnace versus He in-situ anneal is shown in Fig. 3. It indicates the highest count of missing metal was found in the furnace anneal process step in one related wafer. On the other hand, the overall count of this defect level in both anneal processes are comparable and not significantly different. The median defect count per wafer for the furnace and He in situ anneal were equal we can therefore conclude there was no significant difference in missing metal defect counts between the two annealing processes. B1. Missing Metal Defect A compluss scan and top-view SEM image observed from an electroplated Cu film with missing metal defects are shown in Figs. 4 (a) and, respectively. This defect generation was found only after the CMP partial polish step and was not transformed from previous defect. We feel that the possible cause of missing metal defect was attributed to the missing seed Cu from the wafer at the beginning of electroplating or preferentially etched during plating, therefore no Cu is plated in that area. Cu plating is normally followed with an anneal step to encourage film stabilization and grain growth, but this situation will lead to additional defects if the anneal temperature is too high. In fact, such defects are typically observed at post-cmp, where Cu migrated through stress away from the damascene features, leaving voids in its place, giving rise to metal defects. Fig. 5: Missing metal defect counts versus ECP to furnace queue time Fig.3: Box plot of missing metal defect counts for Cu films annealed in furnace and He in-situ (a) /06/$ IEEE 55 Fig. 4: Images of missing metal defect: (a) compluss scan image topview of SEM image Fig. 5 shows the counts of missing metal defect versus electroplating to furnace queue time observed in this study. The results show there is weak correlation between anneal queue time and defect count. The slight increase in this defect with longer queue time may be caused the seed aging. There are several factors that contribute or influence the occurrence of this flaw. The first factor is copper seed age or oxidation state. It is clear that this is not only a function of the time between seed deposition and plating, but also the specific anneal duration. As the above result shows, longer queue time from copper plating to anneal influenced the occurrence of missing metal defect. Further investigation has to be implemented to study the possibility of imposing a time window between seed deposition and plating as well as plating to anneal duration in order to get consistent results. The second factor is mostly dependent on plating chemistry. A couple of organic additives (accelerator and suppressor) used in plating bath are essential to provide

bottom-up fill in small via and trench features, however they tend to act as good surfactants, thus causing metal defects.

Missing metal defect counts versus run sequences in ECP cells is presented in Fig. 6. From the results shown, we can deduce that there is a weak correlation between run sequences and defect level.

Possible causes of such defects could range from an ECP step that might shield a region from the previous processes.

Meanwhile, embedded particles are most easily identified using SEM - normally the size of this defect is 1 to 100 microns range.

In-situ energy dispersive X-ray (EDX) analysis was applied on the embedded particles during SEM review.

Indirectly, this information will lead to identification of the root cause of the defect.

Defect type Gouge TABLE 1: POST-PLATING DEFECT TYPES. Compluss image SEM image Description Caused mainly by CMP process step.

Other Post-plating Defects Post-CMP defect review and classification can reveal previously undetected defects that are unrelated to the CMP process step.

4 bottom-up fill in small via and trench features, however they tend to act as good surfactants, thus causing metal defects. Besides, a third organic additive (leveler) has been introduced to reduce Cu over-deposition (mounding) in dense area of small features. Missing metal defect counts versus run sequences in ECP cells is presented in Fig. 6. From the results shown, we can deduce that there is a weak correlation between run sequences and defect level. But there is a strong correlation to first wafer in He in situ anneals between run sequences for pits, void and crater defects. Possible causes of such defects could range from an ECP step that might shield a region from the previous processes. cause an electrical short between metal lines or other structures, leading to yield loss and reliability problems [6]. Meanwhile, embedded particles are most easily identified using SEM - normally the size of this defect is 1 to 100 microns range. It is important to identify the chemical compositions of these particles to track down the source of these embedded particles. In-situ energy dispersive X-ray (EDX) analysis was applied on the embedded particles during SEM review. As a result, the chemical spectrum will clearly indicate the presence of related chemical in the embedded particle. Indirectly, this information will lead to identification of the root cause of the defect. There are several possibilities for the root cause of embedded particle such as core defect prior to the ECP is already embedded in the barrier or seed layer and then coated by plating. Defect type Gouge TABLE 1: POST-PLATING DEFECT TYPES. Compluss image SEM image Description Caused mainly by CMP process step. Embedded Due to surface particle at CuBS layer, transformed at ECP layer Figure 6: Missing metal defect counts versus run sequences in ECP C. Other Post-plating Defects Post-CMP defect review and classification can reveal previously undetected defects that are unrelated to the CMP process step. Defect detection and classification of other types of post-plating defects were performed in detail in this work. For missing metal faults, the major types of post-plating defects are gouges, embedded particle, Cu void and corrosion. Listed in the table below are the main defects of interest within the barrier seed, copper plating and partial CMP polishing module. Gouge or mostly known as triangle scratches have characteristic triangular profiles as shown in Table 1 and they could be as deep as 2000 Å in angular shape. It is also found some suspected alumina slurry trapped in the gouge at post CMP. Furthermore, EDX analyses shows peaks of C, Si, O, Al and Cu. The gouge is commonly seen on large copper pads in random and is normally detected at Cu CMP process. This flaw can originate from defects in ECP, barrier seed or etch which transformed into gouge after CMP. As a result, scratches or gouges are formed on the wafer surface due to the ploughing action of the abrasive particles as they come into contact with the wafer. Deep scratches can result in the formation of metal residues or puddles on subsequent metal layers, which can then /06/$ IEEE 56 Cu Void Corrosion Round/circular shapes. Derived from previous layer (ECP step)- crater Due to CMP. Large area. Other than that, Cu voids, normally in round shape, is another example of post-plating flaw. The possible cause of Cu voids is still not clear in terms of defect characterization. However, we suspect that the root cause could be at the copper-electroplating step, which is due to surface contamination that prevents plating from happening locally. An aging bath or higher plating current densities resulted in an increase in film impurities, and this can lead to more void formation. One other possibility is decrease in chemical resistance of Cu films by impurity incorporation. It is generally believed that good Cu film quality can hinder void formation. In the metallization process sequence, defects arising from the plating process can be attributed to

5 poor initial wetting of the seed layer at the onset of deposition, sporadic accelerated growth due to the plating chemistry, embedded particles and incomplete rinsing after plating. Another class of post CMP defects is corrosion. The wafers are exposed to corrosive conditions by the chemical component actions of the process, since the Cu CMP utilizes a chemical and mechanical step to remove the material. The occurrence of corrosion is completely random and normally will be detected in a large area. The role of electroplated film quality cannot be ignored in the study corrosion although CMP slurry chemistry is frequently related to this defect. VI. CONCLUSION A preliminary study of the quality of furnace and He in-situ annealed Cu films were evaluated in this work by comparing the missing metal defect level. The impact of annealing conditions on the films was investigated. This paper discussed the major defect types seen in dual damascene copper CMP technology, with an emphasis on major defects that affect yield. As a conclusion, missing metal defect levels for both anneals was found to be comparable for the data points collected. Besides, there is a significant difference in reflectivity and stress between He in-situ and furnace annealed films. A further investigation is currently underway to quantify the difference in copper grain size. IV. ACKNOWLEDGMENTS The authors are grateful to the Thin Film Metal Group from Silterra Malaysia Sdn. Bhd. for their contributions. VII. REFERENCES [1] R. Mostovoy, V. Svidenko, L. Levin, L. Karsenti, A. Rosenfeld, K.Ta, Post-plating Morphological Cu Grain Boundary Analysis, in Proc International Semiconductor Technology Conf., Santa Clara, USA, pp. 1-10, [2] H. P. Feng, M. Y. Cheng, Y. L. Wang, S. C. Chang, Y. Y. Wang, C. C. Wan, Mechanism for Cu Void Defect on Various Electroplated Film Conditions, Thin Solid Films, pp , [3] Hyun Park, Soo-Jung Hwang and Young-Chang Joo, Stress-induced Surface Damage and Grain Boundary Characteristics of Sputtered and Electroplated Copper Thin Films, Journal of Acta Materialia, vol. 52, pp , [4] A. Uedono, T. Suzuki and T. Nakamura, Vacancy-type Defects in Electroplated Cu Films Probed by using a Monoenergetic Positron Beam, J. App. Phys., vol. 95, pp , February [5] Yong-Hui Fan and Taiqing Qiu, Analyses of Thermal Stresses and Control Schemes for Fast Temperature Ramps of Batch Furnaces, in IEEE Trans. on Semiconductor Manufacturing, vol. 10, No. 4, pp , Nov [6] T.Y. Teo and W. L. Goh, Characterization of Scratches Generated by a Multiplaten Copper Chemical-Mechanical Polishing Process, J. Vacuum Sc. Technology, vol. 22, pp , January [7] P. H. Haumesser, T. Mourier, S. Maitrejean, M. Cordeau, T. Morel, X. Avale, O. Pollet, J.Klocke, Copper Post-Electroplating Anneal: Evaluation of In-line vs. Furnace Anneal on Layer Properties, Microelectronic Engineering, vol. 70, pp , /06/$ IEEE 57

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