The ABC s of CMP for DWB and SOI. Robert L. Rhoades, Ph.D. CAMP Conference Presentation August 9, 2010

Transcription

1 The ABC s of CMP for DWB and SOI Robert L. Rhoades, Ph.D. CAMP Conference Presentation August 9, 2010

2 Outline Introduction Direct Wafer Bonding (DWB) Background CMP for DWB Silicon-On-Insulator (SOI) Background CMP for SOI Summary 2

3 DWB Background DWB requires surfaces that are Flat or negative topography (no bumps or mesas) Very smooth Extremely clean CMP is a logical choice for surface preparation Good starting points in CMOS (ILD, STI, Cu, etc.) Many materials can be polished as long as the slurry/pad/process are properly optimized 3

4 Direct Wafer Bonding CMP / Clean Activation RT Bond Anneal Direct Wafer Bonding (DWB) Surface prep is key CMP adapted to the materials being bonded Cleaning steps are critical to ultimate DWB success Anneal is usually necessary to strengthen bonds 4

5 Guideposts for DWB Surface Roughness (Ra) < 0.5 nm nm > 2.0 nm Good Usually ok.. Poor Flatness or topography No bumps sticking up from surface Indents or cavities ok (preferably sharp corners) Surface cleanliness Must be very clean and particle free NO hydrocarbons allowed on surface Materials Strongest bond is generally same-same material Most common are oxide-oxide and Si-Si 5

6 Types of Si DWB Source: Kim and Najafi, University of Michigan,

7 DWB Example #1 Included 3 types of substrates Silicon wafers with grown thermal oxide layers Silicon wafers with deposited oxide films Borofloat 33 glass (clear) Initial work performed on bare substrates and blanket film wafers to understand materials independent of pattern effects 7

8 Thermal Oxide Removed (Ang) CMP Thermal Oxide Removed (low pressure) Removed (med pressure) Test Inputs Thermal oxide films IPEC 472 polisher Klebosol silica slurry IC1000 on Suba IV pad stack Diamond pad conditioner OnTrak DSS with PVA brushes NH4OH(2%) cleaning chemistry Polish Time (seconds) Outcome Two pressures screened Linear function of polish time Surface roughness excellent at all settings (Ra <1 nm) 8

9 Borofloat 33 Removed (Ang) CMP Borofloat 33 Glass Test Inputs Removed (low pressure) Removed (med pressure) Substrates of Borofloat 33 IPEC 472 polisher Klebosol silica slurry IC1000 on Suba IV pad stack Diamond pad conditioner OnTrak DSS with PVA brushes NH4OH(2%) cleaning chemistry 2000 Outcome Same two pressures screened Removal rate ~50% faster than same process on thermal oxide Polish Time (seconds) Multiple wafers per data point shows excellent repeatability 9

10 Removal Rate (Ang/min) CMP on Cavity Wafers Test Inputs Cavities patterned in Si wafers then coated with oxide IPEC 472 polisher Klebosol silica slurry IC1000 on Suba IV pad stack Diamond pad conditioner OnTrak DSS with PVA brushes NH4OH(2%) cleaning chemistry CMP Index (Pressure * Table Speed) Outcome Range of processes studied for impact on cavity edges Relatively linear response across range of CMP index (confirms Prestonian behavior) High pressure settings showed more edge rounding 10

11 Sealed Cavity Excellent bond no evidence of separation along interface Cavities were fabricated using optimized CMP processes on both surfaces 11

12 DWB Example #2 Devices fabricated on primary wafer (200 mm) then encased in thick TEOS layer CMP used to planarize TEOS layer Prime Si wafer used as bonding pair Extreme thinning performed after DWB anneal 12

13 DWB Example #2 Image taken by Surface Acoustic Microscope White spots = small voids Scribe lines barely visible due to density variation in bottom wafer Initial bond made at room temp Bond is stronger after annealing > Kept below 400 deg C to avoid damage to underlying metals 13

14 3D Packaging Apps Source: Yole Development

15 SOI Background SOI = Silicon On Insulator Benefits of SOI vs bulk Si wafers Better Performance (esp. below 90nm device nodes) Reduced junction capacitance Faster speeds Higher signal to noise ratio for RF &analog Lower Power Reduced Vdd Better Yield & Reliability Enhanced isolation between transistors Reduced sensitivity to EM interference Much less sensitive to ionizing radiation (aka rad hardened ) 15

16 SIMOX SOI flow Separation by Implantation of Oxygen Single wafer sequence Three key steps Oxygen implantation High temperature anneal Optional Kiss polish Thickness and depth of buried oxide (BOX) layer are linked Top layer residual damage more of a problem than with Smart-Cut process Source: 16

17 Smart-Cut SOI flow Developed at CEA-Leti Six key steps Thermal oxidation Hydrogen implantation Direct wafer bonding Splitting Annealing Touch or Kiss polishing Very flexible for thickness of buried oxide & top Si layers H+ damage easier to anneal Source: SOI Technology by Vishwas Jaju,

18 SOI Surface Finish Top Si surface finish requirement can vary Fabrication technique Technology for intended device (power, 45nm, etc.) Thickness of active Si layer and BOX layer are both factors in the spread of the implant depth of the ions Generally not possible to achieve best SOI results with standard Si prime wafer final polishing processes Removal rate is too high for accurate thickness control Very low removal amounts do not achieve lowest Ra Optimized CMP polish is preferred 18

19 Polishing Comparison Comparison Substrate Polishing CMP Focus of the Process Improve TTV, flatness, Ra Planarize, reduce defects Mounting Style Rigid Compressible or flexible Impact on TTV Reduction Almost none Typical Amount Removed µm to 10's of µm 0.1 µm to a few µm Removal Rate >1 µm/min (stock) wide range Uniformity outgoing TTV is primary <10% of thin film removed Surface Finish (Ra) nm Ra wide range, typical <1 nm Defect Level Required Low and being reduced Low and being reduced 19

20 Prime Si Polisher Standard Single-Sided Silicon Wafer Polisher Uneven pressure across wafer face Differential material removal from thick areas Designed to improve TTV Rotating carrier shaft Rigid backing plate No gimbal Slurry Wafer Polishing Pad Rigid platen 20

21 CMP Polisher Standard CMP Polisher Uniform pressure across wafer face Designed for uniform film removal Very little impact on TTV Rotating carrier shaft Baseplate Compressible film or membrane Gimbal mount Slurry Wafer Polishing Pad Rigid platen 21

22 Typical Consumables Typical Consumable Substrate Polishing CMP Primary Pad Double-impregnated felt Structured polyurethane Pad Conditioning Stock Slurry Slurry usage details Diamond or other styles Used after multiple runs High ph, silica abrasive Low solids (<2%) High dilution (1:20 or 1:40) Recirculation possible Diamond conditioning disk Continuous or every wafer ph and abrasive vary by mtrl High solids (>10%) Much smaller dilution (if any) Single pass usage preferred Finishing Pad Coated porous felt Wide variation by material Final Slurry Mildly alkaline, silica abrasive Low solids (<2%) Often not required Post-Polish Cleaner Megasonic cleaning line Double-sided scrubber Cleaning Chemistry Typical SC1/SC2 with some proprietary refinements Custom by material 22

23 SOI Examples Parameter Typical Range Example #1 Example #2 Incoming Ra Ang 26 Ang 41 Ang Si Removal 500 Ang 2.0 µm 550 Ang 0.85 µm Final Ra Ang 3.29 Ang 1.93 Ang Ultrathin layer. Target was extremely low removal. More typical values. 23

24 SOI Example Before CMP Ra = 3.88 nm (38.8 Ang) After CMP (removed <600A) Ra = 0.33 nm (3.29 Ang) 24

25 SOI CMP Optimized Before CMP Ra = 3.71 nm (37.1 Ang) After CMP Si removed = 704 Ang Ra = 0.12 nm (1.20 Ang) 25

26 Ra (Ang) SOI CMP Repeatability Optimized CMP process for SOI top Si layer after splitting and annealing 3.0 SOI Post Polish Roughness by AFM Avg Ra = 1.48 Ang Avg Si removal = 871 Ang 1.5 Avg defects < 100 / wafer 1.0 Device ready surface finish comparable to prime Si Wafer Slot 26

27 Summary Direct wafer bonding Bond strength is improved when both surfaces are polished and properly cleaned. Roughness is key with Ra <1nm preferred Surfaces with etched cavities can be bonded for niche apps SOI CMP Final surface must be similar to prime Si for Ra and defects Substrate polishing methods are generally too aggressive Key differences in pads, slurries, and equipment design Optimized CMP can achieve results with <800Ang removal 27

28 Acknowledgements Many thanks to the following: Terry Pfau, Paul Lenkersdorfer, Donna Grannis of Entrepix Customers who gave permission to use images and data For additional information, please contact: Robert L. Rhoades Entrepix, Inc. Chief Technology Officer