Radiation-induced depassivation of latent plasma damage

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1 Microelectronic Engineering 60 (2002) locate/ mee Radiation-induced depassivation of latent plasma damage * a, a b,1 c d. Cellere, A. Paccagnella, L. Pantisano, M.. Valentini, O. Flament, d e a O. Mousseau, P.. Fuochi Dipartimento di Elettronica ed Informatica, Universita` di Padova, Padova, Italy b Dipartimento di Elettronica ed Informatica, Universita` di Padova, Padova, Italy c ST Microelecronics, via C. Olivetti 2, Agrate Brianza, Milan, Italy d CEA-DAM, Bruyeres-le-chatel, ˆ France e CNR-FRAE, Bologna, Italy Received 3 May 2001 Abstract Plasma treatments are widely used in microelectronic industry but they may leave some residual passivated damage in the gate oxides at the end of the processing. The plasma-induced damage can be amplified by metal interconnects (antenna) attached to the gate during the plasma treatments. Ionising radiation reactivates this latent damage, which produces enhanced oxide charge and Si/ SiO2 interface state density. Two CMOS technologies have been investigated, with 5 and 7 nm gate oxides. Threshold voltage shifts, transconductance decrease, and interface traps build-up are always larger for plasma damaged devices than for reference devices Elsevier Science B.V. All rights reserved. Keywords: CMOS; Plasma damage; Radiation; ate oxide 1. Introduction Plasma treatments are widely used in fabrication processes of ULSI integrated circuits, being well suited to comply with the continuing CMOS dimensional scaling, lowering of the thermal budget, and increasing of interconnects levels. Chlorine-based plasma processes are used to attack the metal (etching), oxygen-based plasmas to remove the photoresist (ashing), and various recipes are used to deposit the intermetal dielectric. The gate oxide damage caused by charging during plasma processing *Corresponding author. addresses: cellere@dei.unipd.it (. Cellere), paccag@di.unipd.it (A. Paccagnella), luigi.pantisano@imec.be (L. Pantisano), grazia.valentini@st.com (M.. Valentini), flamento@bruyeres.cea.fr (O. Flament). 1 Present address: IMEC, Leuven B-3001, Belgium / 02/ $ see front matter 2002 Elsevier Science B.V. All rights reserved. PII: S (01)

2 440. Cellere et al. / Microelectronic Engineering 60 (2002) has been widely investigated, as it produces shifts of key device parameters, excess low-field leakage, and early breakdown [1 16]. Plasma damage strongly depends on gate interconnect topographies, device position on wafer, plasma characteristics, and processing equipment. To simulate the very different interconnect topographies, an antenna in polysilicon or metal is usually connected to the gate (see Fig. 1). This antenna enhances the charge collected by the gate during plasma processes, which may result in high fields inducing a tunnelling current to flow through the gate oxide. This current can generate oxide defects such as interface states [2], oxide traps [4,5], and border traps [6]. Charge collection (and the subsequent damage to gate oxide) can happen because of various mechanism: (i) non-uniformities in plasma density and potential, which can lead to large electric fields across the gate oxide [3]; (ii) the electron shading effect [8 11]: in dense lines, the photoresist charges during plasma etching because of the different mass and temperature of electrons and of ions; (iii) the damage due to the O2 plasma used to ash the photoresist [13,14]; this damage mechanism can be enhanced by large area antennas; (iv) the damage due to interlevel dielectric deposition, due to non-conformal oxide growth [15] or to Vacuum Ultra Violet (VUV) rays [16], which generate electron hole pairs in thick oxides, being of great concern in recent studies. The gate oxide plasma damage is partially annealed during subsequent thermal processing, such as the post-metallization heating in forming gas. Nevertheless, part of the oxide defects are just passivated (likely by H atoms) and they can reappear during the device operating life. Passivation effects can be particularly insidious because they mask damage which later may affect long term Fig. 1. Planar geometry of antennas connected to the gate of the devices used in this work. Dense Fingers (DF) antenna enhances the collected charge.

3 Table 1 Main features of the studied CMOS technologies. Cellere et al. / Microelectronic Engineering 60 (2002) Technology 1 Technology 2 tox 5.2 nm 7 nm W/L 60 mm/1.6 mm 10 mm/0.35 mm Poly-doping Dual Dual Well-type Twin-well Twin-well reliability. Electrical stresses are commonly used to accelerate the depassivation and show up this latent damage [2,4,5]. Typically, ionising radiation studies are performed on MOS capacitors or MOSFETs without significant plasma damage. However, these devices are not fully representative of the devices fabricated in ULSI integrated circuits, which may have suffered largely different plasma damage levels depending on their position on the wafer surface, size and topology of the metal contacts to the gate, gate area, etc. Plasma related effects have seldom received attention in the literature devoted to ionising radiation studies; moreover, previous works on this field were focused on relatively thick oxides [17,18]. In this contribution, we have addressed the problem of plasma damage depassivation by ionising radiation in thin gate oxides typical of contemporary CMOS technologies, investigating also the experimental techniques more suitable to study this subject. 2. Devices and experimental procedure Devices used in this work have been fabricated with two different LDD-CMOS technologies with up to six metal levels by ST Microelectronics, Agrate Brianza (MI); Italy. The main technological parameters are listed in Table 1. Minimum channel length for technology 1 is 0.25 mm; however, used devices have a 1.6 mm long channel. This is only due to the availability of these devices; however, we measured and studied 0.25 mm devices using electrical stresses [19], and no significant difference related to latent plasma damage was found between short-channel and long-channel devices. For each technology, all MOSFETs are nominally identical, with the exception of the gate antenna shown in Fig. 1. The Minimum Size (MS) devices have the minimum antenna area and perimeter. The Dense Fingers (DF) antennas have been designed with the purpose of simulating the effects of dense interconnects layouts [8]. DF MOSFETs with different Antenna Ratios (AR) are present (see Table 2), Table 2 eometrical parameters of the antennas Device name Antenna type AR DF1000 Dense fingers 1000 DF500 Dense fingers 500 MS Minimum size 1.5

4 442. Cellere et al. / Microelectronic Engineering 60 (2002) AR being the ratio between antenna and gate area (AR for MS is 1.5). Used antennas are realized in the first metal layer. Based on the material presented in the previous section, the expected gate oxide damage grows with AR. MS devices are subjected to minimum plasma damage and they will be taken as reference devices. All results shown in this work are taken on different MOSFETs (two or three devices have been tested in each experimental condition) cut from a single wafer for each technology: this is necessary, since plasma-induced damage may strongly depend on small plasma process variations. Moreover, plasma induced damage is strongly dependent on global plasma non-uniformities [3]. In order to limit the impact of site-to-site variation on results repeatability, every time data relative to different devices are shown on the same figure, they are taken from MOSFETs on the same or on adjacent wafer sites. The experimental procedure used to depassivate plasma damage is schematically illustrated in Table 3. After the initial electrical characterization (gate current voltage I2V, drain current gate voltage ID2V, and charge pumping (CP) measurements) devices were irradiated. Irradiation of biased devices was done by using a microprobe test station equipped with 10 KeV X-rays generator with dose rate of 1 Mrad(SiO 2)/ min (CEA-DAM, Bruyeres-le-Chatel, ˆ France). This high dose rate is needed to test a number of devices in a reasonable time. Some unbiased devices were exposed to 8 MeV electrons (LINAC, CNR-FRAE Bologna, Italy). After irradiation, positive and negative V sweeps were repeated, as a fast and reliable way to recombine the positive trapped charge and to inject electrons in the neutral traps. The maximum uv u was chosen to limit the current density below A/cm, in order to minimize the associated electrical stress. After each V sweep, we repeated the ID2V and CP measurements. For CP measurements we grounded bulk, drain, and source while the gate was connected to a pulse generator supplying a trapezoidal waveform with fixed sweep of 4 V, frequency of 800 khz, and rise and fall times of 250 ns. In fixed sweep CP the gate offset voltage is gradually increased during the measurement. The maximum CP bulk current is proportional to the Si/ oxide interface state density [20,21]: I max 2 5 qaf?dw? D cp s it q is the electronic charge, A the gate area, f the frequency, Dws is the surface potential swing driven by the gate voltage, and Dit is the interface state density. The CP technique is very reliable and sensitive. For example Icp,max51 na, which is easily measurable, approximately corresponds in our MOSFETs to Dit 5 8?10 cm /ev in Technology 1, and Dit 5 2?10 cm /ev in Technology 2. These large different values are due to the different gate areas. (1) Table 3 Stress and test methodology Initial characterization (I2V, ID2Vand charge pumping) Radiation step Positive I2V ID2V and charge pumping Negative I2V ID2V and charge pumping Positive I2V I 2V and charge pumping, etc.

5 . Cellere et al. / Microelectronic Engineering 60 (2002) Fig. 2. Threshold voltage of pmos (technology 1) after 1 Mrad(SiO ) X-ray irradiation and subsequent V device terminals were grounded during irradiation. 2 sweeps. All 3. 5-nm Oxides (Technology 1) Figs. 2 4 show some results obtained on pmos and nmos (Technology 1) with gate grounded during irradiation (which is almost the flat-band condition in these devices). The threshold voltage of nmos and pmos before and after 1 Mrad(SiO 2) X-ray irradiation and after the first V sweep is plotted in Fig. 2. For both pmos and nmos, in fresh devices threshold voltages depend on the AR value: V TH(DF 1000).V TH(DF 500).V TH(MS). The latter is also the nominal VTH value for this devices (20.65 V for pmos, 10.6 V for nmos). We believe the differences between MS and DF devices are due to some negative charge trapped in DF devices, deriving from incomplete annealing and passivation of plasma damage. In fact, as will be clearer in the following, the effect of plasma damage is mainly seen as enhanced negative charge trapping. As expected in thin oxides [22,23] the threshold voltage shifts due to irradiation are very small. Irradiation induces a tiny accumulation of Fig. 3. Threshold voltage shift of pmos (technology 1) after 10 Mrad(SiO ) X-ray irradiation and a single V device terminals were grounded during irradiation. 2 sweep. All

6 444. Cellere et al. / Microelectronic Engineering 60 (2002) Fig. 4. Maximum of the charge pumping current measured in nmos devices (technology 1) after 10 Mrad(SiO ) X-ray 2 irradiation, as a function of total dose. All device terminals were grounded during irradiation. positive charge, producing DV TH around 210 mv for both nmos and pmos. The positive charge disappears during the following V sweeps when some excess negative charge is trapped and the threshold values slightly increases over the fresh ones. The positive trapped charge grows with the radiation dose, as illustrated in Fig. 3 for pmos after 10 Mrad(SiO 2) and after the first V sweep (positive voltage). Very similar results were obtained for nmos (not shown for brevity). To better evaluate the differences between DF and MS devices, we have plotted the threshold shifts in this figure. The largest VTH variation occurs for the DF 1000 device and it is more than twice the DV TH observed in the MS device. The positive radiation-induced charge grows with the AR, likely due to the depassivation and positive charging of latent defects generated by the plasma treatments. After the V sweep, the positive charge recombines or is passivated by the injected electrons. The largest trapped negative charge is found in the DF 1000 device. Differences among DF and MS devices are reduced after the V sweep, but a negative threshold shift is still measured in comparison with fresh samples. This may suggest that the positive charge has not been fully compensated, or instead that the interface states add a positive charge masking the effects of the negative charge trapped in the oxide. To evaluate the contribution of interface states to DV TH and to study their build-up for different antennas, we measured Dit by CP as a function of the cumulative radiation dose (see Fig. 4). The interface state density grows with the dose and with the AR value, but differences between MS and DF devices are evident only after very high radiation doses (that is, 10 Mrad(SiO 2)). Even in this case the device with the largest AR (and expected to be more damaged by plasma treatments) is more 10 prone to develop interface defects under irradiation. After 1 Mrad(SiO 2), Dit is still below cm / ev indicating negligible defect accumulation at the oxide interface nm Oxides (Technology 2) In 7-nm oxides threshold voltage shifts induced by irradiation are larger than on 5-nm devices and the features observed in the previous figures are well reproduced. In Fig. 5, we show the threshold

7 . Cellere et al. / Microelectronic Engineering 60 (2002) Fig. 5. Threshold voltage shifts for technology 2 pmos devices after 1 Mrad X-ray irradiation. ate voltage was kept to ground during stress; DV TH after positive V sweeps only are shown. voltage shift (around 2100 mv) of pmos after 1 Mrad(SiO 2); all device terminals were grounded during irradiation. Again, the uvthu shift and the trapped positive charge grow with the AR. After the positive V sweep, the threshold voltage becomes more positive than in fresh devices, owing to the positive charge recombination and negative charge trapping, being larger (again) in DF components. When the V sweeps are repeated VTH tends to a saturation value, indicating that no oxide damage is produced by these V swings. Similar results are found in pmos devices subjected to 50 Mrad(SiO ), with gate kept at V V during irradiation (see Fig. 6). In this case, the threshold voltage shifts by almost 1 V in the DF 1000 device. The threshold shift is still negative even after several V sweeps, possibly due to the positive charge contribution from interface states. The effect of the bias applied during irradiation is illustrated in Fig. 7, showing the threshold voltage shifts for pmos with V 50 VorV 521 V during irradiation at 1, 10, and 50 Mrad(SiO ). 2 Fig. 6. Threshold voltage shifts for technology 2 pmos devices after 50 Mrad (SiO ) X-ray irradiation. ate voltage was 2 kept to V 521 V during stress; DV after positive V sweeps only are shown. TH

8 446. Cellere et al. / Microelectronic Engineering 60 (2002) Fig. 7. Threshold voltage shifts immediately after irradiation for technology 2 pmos devices as a function of total dose (10 KeV X-rays), at different gate bias. DF devices are always more damaged than MS, confirming that larger latent plasma damage is present in high AR devices. Devices under negative gate bias show larger DV TH than under zero or even positive gate voltage. This does not correspond to the worst case commonly used for radiation tests of thick oxides, (i.e. the positive bias), but it is in agreement with previous results found on thin oxides [24]. In fact, a positive bias should drift the oxide positive charge toward the Si/ SiO interface, where 2 its effect on threshold voltage is maximum. However, the positive trapped charge is compensated by electrons tunnelling from both interfaces. Under a positive gate voltage, the barrier seen by electrons tunnelling into the oxide from the substrate is much smaller than that seen by electrons tunnelling from the gate. Therefore, the distribution of holes surviving the recombination process will be shifted toward the gate interface. In case of negative bias it will be shifted to the Si, producing the high V TH shift observed in Fig. 7. Very similar results have been found on nmos devices with the same geometry, which are not shown for brevity. On the other hand, if the device is under a positive bias during irradiation, positive charge is driven toward the silicon/ oxide interface. Through recombination processes, the positive charge may create interface defects, resulting in a reduction of the surface mobility. In agreement with this expectation, the peak value of the nmos transconductance decreases more for irradiation done under positive than negative oxide fields (Fig. 8). Again, the DF degradation is larger than in MS nmos. To investigate the behaviour of devices subjected to different types of ionising radiation we also performed irradiation with 8 MeV electrons. No microprobe station could be used in this case to bias the device under irradiation. Moreover, any metal micro-bonding could damage our devices through electrostatic discharges, due to the small MOS size (i.e. small input capacitance). For these reasons these irradiation were done on unbiased devices. In Fig. 9 we show the threshold voltage shift of nmos after 10 Mrad(SiO 2) and after consecutive sweeps. The voltage shifts are similar to those found after X-rays biased irradiation. However, in V this case when more V swings are repeated the oxide negative charge gradually increases, without reaching a saturation value as previously observed, at least in DF devices. In Fig. 10 Icp,max appears for the same devices. These results confirm the previous findings after X-rays irradiation, but even in

9 . Cellere et al. / Microelectronic Engineering 60 (2002) Fig. 8. Transconductance shifts for technology 2 nmos devices subjected to 10 Mrad(SiO ) with different gate bias (10 2 KeV X-rays), at different gate bias. this case successive V sweeps enhance the interface state density. Some electrical stress of the oxide is produced by the V swings (as for the non-irradiated MS device shown in the same figure) and some further depassivation of interface states and negative charge trapping is achieved in large AR samples. 5. Discussion No basic aspect related to the defect reactivation has been considered in this work, which was intended as an exploratory effort to investigate possible reliability problems related to plasma damage and radiation effects. In this sense, if plasma damage effects are limited to the extent observed in our Fig. 9. Threshold voltage shifts for nmos devices (technology 2) subjected to 10 Mrad(SiO 2) with 8 MeV electrons, as a function of V sweeps. Devices were left floating during irradiation.

10 448. Cellere et al. / Microelectronic Engineering 60 (2002) Fig. 10. Maximum of charge pumping current for nmos devices (technology 2) subjected to 10 Mrad(SiO 2) with 8 MeV electrons, as a function of V sweeps. Devices were left floating during irradiation. devices, in general no concern should appear for space applications where radiation doses are quite low ( Krad(SiO 2)) in comparison with those used in this work. Moreover, CMOS circuits produced by using the most recent scaled technologies should be even less sensitive to radiationinduced depassivation of plasma damage. On the other side, some points give rise to serious concern: (i) in high energy physics experiments radiation doses as high as 10 Mrad(SiO ) are expected on the 2 front-end electronics. If these components will be fabricated by using CMOS commercial processes, depassivation of related plasma damage may have some impact on the performance of MOSFETs. The same consideration holds true for long space missions, where the same high total doses are achieved. (ii) Older generation, thicker-oxide devices degradation may be underestimated if latent plasmainduced damage is not taken into account. Radiation-induced degradation is usually measured using large area capacitor, which have a very small AR (due to the short interconnection), and so exhibit no plasma-induced damage. This way, performance degradation of real devices (which do have a latent plasma-induced damage, since they need large interconnections) is underestimated. (iii) Even state-of-the-art devices, with very short channels and ultra-thin oxides, usually need some thicker oxide device, which is intended to work at higher voltages: for example, charge pump circuits in flash memories. These devices are more prone to degradation because of their thicker oxides; in fact, they often are the first to fail in Total Irradiation Dose experiments [25]. 6. Conclusions We have proposed a stress-and-test method to study the effect of ionising radiation on the latent plasma damage in recent CMOS technologies. We studied devices from two commercial technologies, and used different ionising sources, namely X-rays and 8 MeV electrons. As in case of electrical

11 . Cellere et al. / Microelectronic Engineering 60 (2002) stresses, ionising radiation reactivates passivated defects in the oxide and at the Si/ SiO2 interface. Consequently, excess oxide charge and interface states are observed in MOSFETs with large antenna ratio. In general high doses are needed to produce noticeable depassivation of latent damage, and the radiation effects are larger on thicker oxides. The importance of these results for device reliability in different operating conditions is discussed. In particular, we demonstrated that device shifts after irradiation can be largely underestimated. Acknowledgements The authors would like to acknowledge C. Marcandella for the technical support during tests with the X-rays microprobe station, and E. Minicuci for valuable help in data analysis. This work was supported in part by CNR, Progetto Finalizzato Materiali e Dispositivi per l Elettronica a Stato Solido 2, and INFM (Istituto Nazionale di Fisica della Materia). References [1] J.P. McVittie, Process charging in ULSI: mechanisms, impact and solutions, IEDM 1997 Tech. Digest, pp [2] L. Pantisano, A. Paccagnella,. Cellere, P. Colombo, M.. Valentini, Interface State Creation Due to Low-Field Latent Damage Depassivation, 5th Symp. Plasma Process-Induced damage, pp [3] K.P. Cheung, C.P. Chang, Plasma-charging damage: a physical model, J. Appl. Phys. 75 (1994) [4] T. Brozek, Y.D. Chan, C.R.Viswanathan, Enhanced Hole Trapping in MOS Devices Damaged by Plasma-Induced Charging, Proc. ESSDERC, 1996, pp [5] T. Brozek, Y.D. Chan, C.R. Viswanathan, Threshold voltage degradation in plasma-damaged CMOS transistors-role of electron and hole traps related to charging damage, Microelectron. Reliab. 36 (1996) [6] D.M. Fleetwood, N.S. Saks, Oxide, interface and border traps in thermal, N2O, and N2O-nitrided oxides, J. Appl. Phys. 79 (1996) [7] T. Yamada, K. Eriguchi, Y. Kosaka, K. Hatada, Impacts of Antenna Layout Enhanced Charging Damage on MOSFET Reliability and Performance, IEDM Tech. Dig., 1996, pp [8] K. Hashimoto, New phenomena of charge damage in plasma etching: heavy damage only through dense-line antenna, Jpn. J. Appl. Phys. 32 (1993) [9] K. Hashimoto, Charge damage caused by electron shading effect, Jpn. J. Appl. Phys. 33 (1994) [10].H. Hwang, K.P. iapis, On the Link Between Electron Shadowing and Charging Damage, 2nd Symp. On Plasma Process-Induced Damage, 1997, pp [11] X.-Y. Li, T. Brozek, P. Aum, D. Chan, C.R.Viswanathan, Degraded CMOS Hot Carrier Life Time-Role of Plasma Etching Induced Charging Damage and Edge Damage, IEEE Proc. IRPS, 1995, pp [12] S. Ma, J.P. McVittie, K.C. Saraswat, Effects of wafer temperature on plasma charging induced damage to MOS gate oxide, IEEE El. Dev. Lett. 16 (1995) [13] K. You, M. Chang, C. Wu, A new simulation model for plasma ashing process-induced oxide degradation in MOSFET, IEEE Trans. El. Dev. 45 (1998) [14] C.-H. Chien, C.-Y. Chang, H.-C. Lin, T.-F. Chang, S.-. Chiou, L.P. Chen, T.Y. Huang, Resist-related damage on ultrathin gate oxide during plasma ashing, IEEE El. Dev. Lett. 18 (2) (1997) [15].H. Hwang, K.P. iapis, Modeling of charging damage during interlevel oxide deposition in high-density plasmas, J. Appl. Phys. 84 (1998) [16] K.P. Cheung, On the Mechanism of Plasma Enhanced Dielectric Deposition Charging Damage, 5th Symp. Plasma Process-Induced damage, pp

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