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1 Modeling, Design and Demonstration of Low-temperature, Low-pressure and High-throughput Thermocompression Bonding of Copper Interconnections without Solders Ninad Shahane*, Scott McCann, Gustavo Ramos +, Arnd Killian +, Robin Taylor +, Venky Sundaram, Pulugurtha Markondeya Raj, Vanessa Smet, and Rao Tummala 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta, GA, USA + Atotech GmbH, Berlin, Germany ninad.shahane@gatech.edu Abstract High-throughput assembly technologies to form Copper (Cu) interconnections without solders at below 200 o C, and pitch below 40µm has been a major challenge in the semiconductor industry. A unique solution has been demonstrated by Georgia Institute of Technology to overcome this grand challenge. This technology utilizes thermocompression bonding to form copper interconnections with process tolerances to accommodate non-coplanarities of bumps and warpage of the substrate, without solders. The bonding pressure applied for thermocompression was 365MPa, to enable Cu bump collapse by 3µm. As thermocompression bonders are generally force-limited to 400N, such high bonding pressures may hinder scalability of this technology to fine pitches with higher I/O densities. This paper addresses this manufacturability challenge with the novel Electroless Palladium Autocatalytic Gold (EPAG) surface finish instead of the standard Electroless Nickel Immersion Gold (ENIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) finish, previously used to prevent Cu oxidation for bonding load reduction down to 120MPa. Finite element modeling was carried out to understand the bonding mechanism and deformation behavior of Cu bumps and pads. Compensation of non-coplanarities and warpage by collapse of the Cu bumps was found to be the prevalent limiting factor for pressure reduction. New interconnection material and structure innovations were studied for their deformation behavior as a function of the applied pressure in thermocompression. The EPAG surface finish enables a 3X reduction in bonding pressure, by the elimination of Ni, and redistribute plastic deformation more equally between bumps and pads. The proposed innovations thus address both manufacturability and scalability of copper interconnections to 20µm pitch, while maintaining compatibility with current production-level thermocompression tools and processes. 1. Introduction The need for higher speed and bandwidth at lower power consumption for high-performance applications is expected to drive off-chip interconnection pitch to 20µm and below in the coming decade. The recent trend to 2.5D integration, where a single large die may have to be partitioned into two or more smaller devices and reconstructed on the substrate, with highdensity wiring, further reinforces the requirements for ultrafine pitch interconnections in advanced smart mobile and highperformance systems. Ever since IBM s invention of the C4 solder bump flipchip technology [1], numerous advances in interconnection technologies have been made to keep up with increasing I/O densities on one hand, and IC size reduction on the other, thus necessitating pitch scaling. The Cu pillar with solder cap technology developed by APS [2] and more recently by Texas instruments in tandem with Amkor in 2011, was a major breakthrough in fine-pitch interconnections, dominating mobile and high-performance applications at 40µm pitch in production [3] and 30µm in research and development. Further pitch scaling leads to a reduction of the bump standoff height and diameter, which subsequently leads to a reduction in solder volume. This raises severe reliability concerns due to increased stresses at the solder-intermetallic interfaces and poor currenthandling capability of solders. Solid-liquid Interdiffusion (SLID) bonding has been proposed as an all-intermetallic interconnection solution to extend the scalability of solderbased technologies to finer pitches [4]. SLID bonding works on the principle of forming a high melting and stable intermetallic phase after assembly at the expense of low-melting reactants. However, this technology faces its own set of challenges, including low throughput due to extended transition times required to attain fully stable intermetallics [5, 6] and questionable reliability due to Kirkendall voiding and inherent intermetallic brittleness [7]. As a result, interconnections formed by solid-state bonding are gaining importance to address the fine-pitch challenge. Such technologies are extensively used in wafer-level packaging and gaining importance for off-chip interconnections. Solid phases have low interdiffusion rates because of higher activation energies required compared to liquid phases. Consequently, metallurgical bonding in solid state necessitates clean and oxide-free surfaces and the use of an external driving force such as ultrasonic energy or pressure. Hence, oxide-resistant, soft materials such as gold are generally preferred. Gold (Au) is chemically noble and can be deposited using either electroplating, electroless plating or stud bumping at pitches as low as 50µm [8, 9]. Au-Au interconnections (GGI) can be formed by thermosonic [10] or, more recently, thermocompression bonding. Thermocompression bonding conditions are a trade-off between temperature and pressure; higher temperatures resulting in lower yield strength and higher ductility, while higher pressures improve interdiffusion by reducing diffusion lengths. Formation of Au-Au interconnections has been demonstrated by thermocompression bonding at 150 o C-300 o C with typical pressures in the MPa range [11-14]. Despite their excellent processability and electrical, thermal and reliability performances, the use of Au /15/$ IEEE Electronic Components & Technology Conference

2 based interconnections in high-volume manufacturing is inherently limited by the prohibitive cost of Au. Ultimately, all-cu interconnection technologies, without solders are highly sought after by the semiconductor industry as the holy grail for ultra-fine pitch. Cu has outstanding electrical and thermal conductivities, enabling high powerhandling capability and high-speed signal transmission, and is compatible with standard back end of line (BEOL) infrastructure and processes. Existing direct Cu-Cu technologies, typically used in wafer-level 3D IC stacking, often require extensive surface preparation or activation, such as chemical-mechanical polishing (CMP), bonding in vacuum or controlled atmospheres, or at temperatures far exceeding that of traditional solder-based reflows with long annealing times at high temperature for interdiffusion and recrystallization [15-22], thus limiting their applicability to high-volume manufacturing. To date, no cost-effective, manufacturable all- Cu interconnection technology, combining low bonding temperatures and pressures, and short assembly cycle times has been demonstrated. Georgia Tech PRC recently patented a novel technology to form Cu interconnections without solders at temperatures below 200 o C, in air, without any complex surface preparation, and with cycle times comparable to production times [23]. This is achieved with the following attributes: a) prevention of Cu oxidation by application of standard surface finish on Cu micro-bumps and pads; b) reduction in bumping cost by implementing all-cu bonding without solder plating; c) accommodation of bump and pad non-coplanarities by controlled collapse of the bumps during thermocompression; d) ultra-high current handling capability without solders and with stable interfaces; and e) high-throughput, under 5 seconds. Excellent thermomechanical reliability and electromigration resistance of these interconnections at 10 6 A/cm 2 has already been demonstrated at pitches down to 30µm, with low-cte organic and glass substrates [24-26]. Recently, lowtemperature, ultra-fast die-to-panel Cu interconnections were demonstrated by Georgia Tech PRC by thermocompression bonding using pre-applied underfill materials at a 365MPa nominal pressure and a bump temperature of 160 o C [27, 28]. The cycle time was limited by the underfill reaction speed which is, itself, temperature-dependent. A fast curing underfill will decrease the cycle time and will bring about a lowtemperature high-throughput assembly. Reduction of the bonding load with adequate tolerance to non-coplanarities and warpage is, therefore, the last bottleneck in advancing this interconnection technology to the manufacturability level required for ultra-fine pitch assembly. Since thermocompresion bonders are force-limited to 400N, this constrains I/O densities at a given process pressure, thus requiring innovations in both interconnection design and surface finish materials to meet this manufacturability challenge. This paper reports the modeling, design and demonstration of all-cu interconnections and assembly technology with low bonding pressures, down to 120MPa. Finite element modeling was carried out to understand the bonding mechanism and deformation behavior of the interconnection structure, leading to the controlled collapse of the Cu bumps. Different surface finish compositions were evaluated ENIG, used as reference and a novel EPAG finish with respect to the bonding pressure. Daisy-chain test wafers and organic substrates with a minimum pitch of 100µm were fabricated to verify the models prediction. The surface finish was plated by Atotech GmbH on wafers and substrates with controlled variations in thickness of Pd and Au layers for this parametric study. Confocal 3D microscopy was used to characterize the bump collapse for various pressure levels in compression tests. 2. Bonding Mechanism The interconnection structure in this study is shown in Fig. 1. The Cu micro-bumps and Cu pads on wafers and substrates are protected from oxidation by a surface finish layer. The bonding mechanism established in [28] was identified as partial metallurgical bonding with pressureinduced plastic deformation as the driving force. This was assisted by chemical bonding through a pre-applied underfill material. Fig. 1. Schematic of interconnection structure with Cu bumps and pads plated with surface finish (SF), and illustration of bonding mechanism with controlled collapse of the bump under compression. Fig. 2. Deformation contours showing a maximum vertical collapse of 3.20µm at 350MPa (left) with a maximum lateral displacement of 1.06µm (right). The 3D quarter symmetric finite element model of Fig. 2 was built using ANSYS software to better understand the bonding mechanism and deformation behavior of the Cu bump and pads during thermocompression bonding. The modeled geometry consisted of a Cu bump, 10µm in height and 10µm 1860

3 Collapse (μm) in diameter, plated on a 5µm-thick Cu pad on the Si die side; and a Cu landing pad on the substrate, 10µm in thickness. The bump diameter was scaled using the half-pitch design rule, for 20µm pitch. ENIG surface finish was considered on Cu bump and pads with a 3µm-thick Ni(P) and Au layer, respectively. The Ni(P) layer acts as a diffusion barrier to prevent Au diffusion into Cu under thermal loading to form AuCu, AuCu 3 or Au 3Cu intermetallics [29]; while the thin Au layer acts as soft, plastically deformable surface to create intimate contact between the mated interfaces. The model also includes a preapplied underfill material surrounding the bumps. Isotropic elastic-plastic mechanical behavior was assumed for all materials. Plasticity was represented with a bilinear kinematic hardening law, with the parameters reported in Table 1. The load was applied from the die side while the substrate pad side was fixed. The model was uniformly heated and cooled. The model was solved at five different time steps using birth and death, to emulate as accurately as possible the assembly process: 1) heat to bonding temperature of 180 C; 2) force ramped up to the bonding pressure, in the MPa range; 3) release of the pressure; 4) cool to underfill activation temperature of 160 C, which corresponds to its glass transition temperature T g (birth of underfill); 5) cool to room temperature at 25 C. Table 1. Isotropic elastic-plastic material properties for Cu, Ni(P) [30], Pd [31] and Au [32]. Materials Cu Ni(P) Au Pd Elastic (GPa) Poisson s ratio Initial Yield Stress (MPa) Tangent Modulus (MPa) CTE (ppm/k) Applied compressive forces cause plastic strain in the Cu bump, leading to their collapse and bringing the mated interfaces into intimate contact. The deformation contours of Cu bumps and pads are shown in Fig. 2 The deformation gradient in the pads and the bump implies that plastic strain is distributed between bumps and pads. Due to the stiff Ni layer hindering deformation of the Cu bump and substrate pad, significant plastic strain was found in the Cu pad on the die side, raising serious concerns over potential failures of low-k dielectric layers stacked underneath. Additionally, excessive plastic strain is observed in the thin Au layers of the ENIG finish, acting as a driving force for interdiffusion or self-diffusion of Au and subsequent localized metallurgical bonding where atomic contact was achieved under thermocompression. Local Au-Au metallurgical bonding has been demonstrated at 200 o C and 365MPa applied pressure in [28], with outstanding reliability performance [26]. Due to the high plasticity and ductility of Au, it has been shown that Au-Au bonding can be achieved at average pressures of MPa, indicating that the pursuit of metallurgical bonding is not the limiting factor for bonding load reduction in the considered interconnection structure. A systematic study of the bump and pad collapse as a function of the applied pressure was conducted, and is summarized in the graph of Fig. 3. A bonding pressure of 350MPa yields a bump collapse of 3.20µm, which is sufficient to compensate for non-coplanarities and achieve full assembly yield. The lateral displacement of the bump resulting from volume conservation was found to be only 1.06µm, suggesting a minimal risk of bridging in fine-pitch applications ENIG Bonding Pressure (MPa) Fig. 3. Collapse of Cu bump with ENIG surface finish as a function of bonding pressure. Formation of Cu interconnections, 10µm in diameter, plated with ENIG surface finish, has been previously demonstrated at 30µm pitch by thermocompression at 200 C and 365MPa bonding pressure. Compression trials carried out at this nominal pressure led to a collapse of the bump by 3.5µm, as indicated by the SEM images of Fig. 4, before and after compression. At this pressure level, the model predicts a total collapse of the bump by 3.44µm. The empirical data correlate well with the predictions, with a 1.7% error margin. Deviations between model and experiments can be attributed to the discrepancies between the materials properties used in the model with respect to the actual ones. Characterization of the mechanical properties of the Cu bumps, including elastic and tangent moduli and yield strength, is ongoing for more accurate modeling. The cross-section of an assembly in nominal bonding conditions shown in Fig. 4 confirms the deformation behavior of the interconnection structure, showing deflection of the Cu landing pad on the substrate side alongside collapse of the bump. Very little deformation of the pad on the die side was observed as compared to the substrate side, contrary to the model predictions, as the substrate pad was directly resting on a soft, highly-deformable polymer layer, shifting the strain distribution. Since Au-Au solid-state bonding can be achieved at much lower pressures than considered, the limiting factor for bonding pressure reduction is the offset from non-coplanarities. A key innovation in surface finish has been proposed to address this challenge, as detailed in the following sections. 1861

4 Collapse (μm) (c) Fig. 4. SEM images of a Cu micro-bump array a) before and b) after thermocompression bonding at 200C 365MPa for 60 sec; and (c) of the cross-section of a copper interconnection formed in the same conditions [28]. configurations reported in Table 2, to optimize the surface composition with regards to metallurgical bonding and cost. The mechanical behavior of Pd was considered isotropic elastic-plastic, and represented with a bilinear kinematic hardening law with the parameters shown in Table 1. Typical bump and pad collapse displacement contours obtained with the EPAG surface finish are presented in Fig. 5 for bonding pressures varying in the MPa range. This contour suggests that plastic strain was distributed more uniformly between bump and pads compared to the ENIG model of Fig. 3. This indicates a lower risk of failure in the subwafer dielectric layers. The collapse of the Cu bump and pad as a function of the applied bonding pressure is shown in Fig. 6, for all given surface finishes. The model predicted an almost 3X decrease in the bonding pressure required to bring about a 3µm total collapse at 20µm pitch, from the reference 350MPa with ENIG to 120MPa in any of the EPAG configurations. 3. Novel EPAG Surface Finish 3.(a)Process Modeling Based on previous results, elimination of the Ni interface would be desirable to improve the deformation behavior of the interconnection structure. The Ni layer degrades electrical performance, especially at high frequencies due to skin effect and can also cause shorting due to Ni spread, thus limiting its use for fine line technologies [33]. It is, however, beneficial as a thick barrier layer to prevent interdiffusion of Cu and Au, which could be detrimental to the thermo-mechanical stability of the joint [34]. A new surface finish, EPAG recently developed by Atotech GmbH, is considered for this study. The EPAG process allows deposition of nm Palladium (Pd) layers directly on Cu, and subsequently nm thick Au layers on the Pd. The EPAG process has been shown to be particularly suitable for fine-line applications. No extraneous Pd or Au deposition is observed even with only 15µm spaces between Cu traces, while the autocatalytic nature of the process prevents the attack of the sub-15µm fine-line Cu structures. With solder, the thin Pd and Au layers are entirely dissolved yielding similar IMC formation and reliability than with Immersion Sn and OSP finishes [33]. Also, compatibility of EPAG with Au, Cu or Ag wire bonding was demonstrated. An additional advantage of EPAG over ENIG is its better high-frequency performance for signal transmission. Losses along traces were measured to be substantially lower. In case of thermocompression bonding, the electroless Pd layer is expected to act as a diffusion barrier preventing intermixing of Cu and Au, while autocatalytic Au still provides a soft, low-modulus contact surface to enhance contact plasticity and metallurgical bonding. The finite element model from the previous section was altered to evaluate the effect of surface finish composition on the Cu interconnect deformation behavior under thermocompression. The ENIG surface finish, used as reference, was replaced with thin layers of Pd and Au. Further, the Pd and Au thicknesses of the EPAG surface finish were varied in the nm and 0-250nm range, respectively, in the Fig. 5. Bump and pad collapse displacement contour of the Cu interconnection structure with EPAG4 surface finish, after thermocompression at 100MPa (left), 120MPa (middle) and 150MPa (right), with a corresponding bump collapses of 2.39µm, 3.64µm and 5.58µm, respectively EPAG legs ENIG Bonding Pressure (MPa) Fig. 6. Collapse of the Cu bumps and pads with respect to ENIG and EPAG surface finishes as a function of the applied bonding pressure, obtained by modeling of the thermocompression process at 180 C. 1862

5 The EPAG slope is higher than that from the ENIG structure because of its higher sensitivity to loading. Since the Pd-Au layers are relatively thin and more ductile than stiff Ni, higher plasticity is achieved the EPAG model at a given pressure, hence a higher bump collapse. The lateral displacement of the Cu-EPAG interconnection at 120MPa was found minimal, a mere 0.88µm, thus eliminating the chance of bridging for fine-pitch applications. The lateral displacement was slightly lower as compared to that of the reference ENIG model, due to the low bonding pressure applied. At 120MPa, the total bump collapse varied only by 3.5% with different bump stack designs, in the µm range. A highest bump and pad collapse of 3.64µm was observed at 120MPa with 100nm Pd and 250nm Au (EPAG4). It was also observed that an increase in thickness of the Au layer on both bump and pad interfaces resulted in a higher total collapse at a given bonding pressure. This can be attributed to the low yield strength of Au, leading to higher plasticity levels at the interface with increased thickness. Lastly, an EPAG surface finish with only Pd showed a similar behavior as other EPAG compositions. A pure Pd surface finish as such could be a costeffective solution to bring this technology to finer pitches, provided that the thin electroless Pd layer can effectively prevent Cu oxidation with a reasonable shelf life, and that direct Pd-Pd metallurgical bonding can be achieved at temperatures below 200 C. Finite element modeling proves that the novel EPAG surface finish would bring significant bonding load reduction, while maintaining high plasticity levels at the mated interfaces to enable metallurgical bonding. A thorough experimental plan was carried out to confirm these simulation results. 3.(b) Test Vehicle Fabrication For this parametric study aimed at the optimization of the EPAG surface finish composition, a simple daisy-chain test vehicle was fabricated using standard industry processes, with a minimum pitch of 100µm, to ensure excellent assembly yield. The test vehicle design comprises of a 5mm x 5mm Si die, 600µm in thickness. The test die features 760 Cu micro-bumps, 30µm in diameter and 10µm in height, arranged in three peripheral rows at 100µm pitch and a central area array at 250µm pitch. The daisy-chain pattern is divided into individual chains, with four two-point probe structures for corner daisychains and eight for half-edge daisy-chains, while the area array is split into four individual daisy-chains as shown in Fig. 7. A 600µm-thick 6 Si wafer was utilized to fabricate the Si dies using semi-additive plating processes. A 2µm-thick SiO 2 layer was first deposited using Plasma-Therm PECVD. Then, a 30nm Ti 500nm Cu seed layer was sputtered over the oxide layer. The dogbone routing layer was patterned by photolithography followed by electrolytic plating of 2.5µm. An additional lithography step was required to pattern the microbumps, which were then electroplated to a 10µm height. After photoresist stripping and seed layer etching, surface finish is applied to prevent Cu oxidation. Test substrates were fabricated from 6 x 6 Cu-clad FR-4 organic laminates for ease of subtractive processing. The Cu cladding on the 1mm-thick FR- 4 core was etched down from 50µm to 10µm, followed by a standard photolithography and back-etch processes to build the dogbone Cu pattern without a seed layer. After photoresist stripping, surface finish was applied. Surface finish on both wafers and substrates was plated by Atotech Germany. The Au and Pd layer thicknesses were designed to evaluate the effect of the interconnection stack on: a) bonding pressure reduction while maintaining a 3µm bump collapse to compensate for non-coplanarities, and b) metallurgical bonding, confirmed by detailed interfacial characterization, and compared to the ENIG control reference. For that purpose, the various compositions of EPAG reported in Table 2 were considered. The as-plated Si die with the EPAG4 surface finish can be observed in Fig. 8. An XRF measurement of the EPAG4 surface finish on the dicing mark of the wafer indicates an average thickness of 282nm of Au and 124nm of Pd, which correlate reasonably with the assumptions from the model. Table 2. EPAG surface finish Pd-Au thickness legs for Si die and FR4 substrate Leg Pd (nm) Au (nm) Si Die Wleg Wleg EPAG Substrate EPAG EPAG EPAG Fig. 7. Test vehicle design with daisy-chain structures for interconnection yield and reliability evaluation: 5mm x 5mm die (left) and 30mm x 20mm substrate with probing pads (right). Fig. 8. Optical micrographs of as-plated Si die with EPAG4 surface finish. 3.(c)Experimental Model Validation Initial compression tests were carried out on the Si dies with EPAG surface finish to understand the evolution of the bump height with changes in bonding pressure. It can be seen from Fig. 9 that the as-plated bumps had rounded tips and showed collapse of the initial dome shape to give complete 1863

6 planarization at 120MPa (64N) and 300MPa (161N) respectively. Fig. 9. Confocal images of Cu bumps with EPAG finish asplated showing a rounded-tip shape, and after compression at 300MPa and 120MPa, showing complete bump planarization, and partial planarization with slightly reduced contact area, respectively. Further, assembly was performed by thermocompression bonding using a semi-automatic Finetech Fineplacer Matrix flip-chip bonder with a placement accuracy of ±3µm. Thermocompression bonding was carried out at 190 o C and 120MPa, applied for 3s, to form Cu-EPAG interconnections. Electrical measurements of the daisy-chain resistances confirmed perfect electrical yield. Optical images of the crosssection of an assembly formed in such conditions are presented in Fig. 10. Flattening of the initially rounded bump is observed, as well as a slight deviation of the Cu pad on substrate side, as predicted by the model. Fig. 10. Cross-sections of Cu interconnections formed by thermocompression bonding at 120MPa 3s 190 o C. Conclusions This paper models, designs and demonstrates, for the first time, low-pressure, low-temperature all-cu interconnections without solders at multi-fine pitch. With previous studies on Cu-Cu interconnections using standard ENIG surface finish, metallurgical bonding is achieved with high bonding pressures. In order to reduce the bonding pressure, innovations in the areas of surface finish are explored. The bonding mechanism and deformation behavior at the interface during thermocompression bonding was studied using finite element models. The novel EPAG surface finish without a thick Ni(P) barrier layer showed 3X reduction of bonding pressure compared to ENIG. For the same bonding pressure, the total bump and pad deformation increased with a marginal increase in Au thickness from 100nm to 250nm. This is due to the low yield strength of Au, giving higher plasticity at the interface. The distribution of deformation between bumps and pads however raises concerns for low-k dielectric failures. To address this fundamental challenge, novel interconnection concepts are required, where the pressure-induced deformation is completely confined within the bump, while still providing a sufficient driving force to enable metallurgical bonding of the mated interfaces. Manufacturable solutions to this technical challenge at bonding pressures below 50MPa are currently under investigation by GT PRC. In summary, a new breakthrough in all-cu interconnection design, material and manufacturable assembly process technology is presented, with reduced bonding pressures for scalability to 20µm pitch and below. Acknowledgements This study was supported by the Interconnections and Assembly industry program at Georgia Tech PRC. The authors are grateful to the industry sponsors and mentors for their funding and technical guidance. The authors would like to thank Atotech GmbH, especially Mrs. Maja Tomic and her team, for surface finish plating. References [1] P. Totta, "History of Flip Chip and Area Array Technology," in Area Array Interconnection Handbook, K. Puttlitz and P. Totta, Eds., ed: Springer US, 2001, pp [2] F. Tung, "Pillar connections for semiconductor chips and method of manufacture," ed: Google Patents, [3] M. Gerber, C. Beddingfield, et al., "Next generation fine pitch Cu Pillar technology: Enabling next generation silicon nodes," in Electronic Components and Technology Conference (ECTC), IEEE 61st, 2011, pp [4] D. S. Duvall, W. A. Owczarski, and D. F. Paulonis, "TLP bonding: a new method for joining heat resistant alloys," Journal Name: Weld. J. (N.Y.), v. 53, no. 4, pp ; Conference: 54. AWS annual meeting, Chicago, IL, [5] H. Liu, K. Wang, K. E. Aasmundtveit, and N. Hoivik, "Intermetallic Compound Formation Mechanisms for Cu- Sn Solid Liquid Interdiffusion Bonding," Journal of Electronic Materials, vol. 41, pp , [6] T. Kazumasa, U. Mitsuo, T. Naotaka, T. Yoshihiro, and T. Kenji, "Micro Cu Bump Interconnection on 3D Chip Stacking Technology," Japanese Journal of Applied Physics, vol. 43, p. 2264, [7] K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano, and K. N. Tu, "Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability," Journal of Applied Physics, vol. 97, p , [8] C. L. Wong and J. How, "Low cost flip chip bumping technologies," in Electronic Packaging Technology Conference, Proceedings of the 1st, 1997, pp [9] J. H. Hall, "Method of providing electrical contacts by sputtering a film of gold on a layer of sputtered molybdenum," ed: Google Patents, [10] C. F. Luk, Y. C. Chan, and K. C. Hung, "Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies," in Electronic Components and Technology Conference, Proceedings., 51st, 2001, pp

7 [11] G.-S. Park, et al., "Low-Temperature Silicon Wafer-Scale Thermocompression Bonding Using Electroplated Gold Layers in Hermetic Packaging," Electrochemical and Solid-State Letters, vol. 8, pp. G330-G332, [12] N. Malik, et al., "Hermeticity and Reliability of Au-Au Thermocompression Bonds, Realized at Low Temperature," ECS Transactions, vol. 64, pp , [13] C. H. Tsau, S. M. Spearing, and M. A. Schmidt, "Fabrication of wafer-level thermocompression bonds," Microelectromechanical Systems, Journal of, vol. 11, pp , [14] H. Oppermann, L. Dietrich, M. Klein, and B. Wunderle, "Nanoporous interconnects," in Electronic System- Integration Technology Conference (ESTC), 3rd, 2010, pp [15] A. Shigetou, T. Itoh, K. Sawada, and T. Suga, "Bumpless interconnect of 6-µm pitch Cu electrodes at room temperature," in Electronic Components and Technology Conference, ECTC 58th, 2008, pp [16] R. Reif, A. Fan, C. Kuan-Neng, and S. Das, "Fabrication technologies for three-dimensional integrated circuits," in Quality Electronic Design, Proceedings. International Symposium on, 2002, pp [17] C. S. Tan, D. F. Lim, et al., "Cu Cu diffusion bonding enhancement at low temperature by surface passivation using self-assembled monolayer of alkane-thiol," Applied Physics Letters, vol. 95, p , [18] C. M. Whelan, M. Kinsella, L. Carbonell, H. M. Ho, and K. Maex, "Corrosion inhibition by self-assembled monolayers for enhanced wire bonding on Cu surfaces," Microelectron. Eng., vol. 70, pp , [19] W. Yang, H. Shintani, M. Akaike, and T. Suga, "Low temperature Cu-Cu direct bonding using formic acid vapor pretreatment," in Electronic Components and Technology Conference (ECTC), IEEE 61st, 2011, pp [20] W. B. a. Ziptronix, "A Path to 3D Integration using Silicon Vias and DBI (Direct Bond Interconnect)," in EMC-3D SE Asia Technical Symposium, [21] A. S. a. SEMATECH, "Scaling 2.5D/3D: the next R&D challenge," in 2nd Annual IEEE Global Interposer Technology Workshop, Georgia Institute of Technology, Atlanta, GA, USA, [22] A. A. O. Tay, M. K. Iyer, R. R. Tummala, V. Kripesh, E. H. Wong, M. Swaminathan, et al., "Next generation of 100-µm-pitch wafer-level packaging and assembly for systems-on-package," Advanced Packaging, IEEE Transactions on, vol. 27, pp , [23] N. Kumbhat, A. Choudhury, V. Sundaraman, and R. R. Tummala, "Interconnect assemblies and methods of making and using same," ed: Google Patents, [24] A. Choudhury, N. Kumbhat, P. M. Raj, Z. Rongwei, V. Sundaram, R. Dunne, et al., "Low temperature, low profile, ultra-fine pitch copper-to-copper chip-last embedded-active interconnection technology," in Electronic Components and Technology Conference (ECTC), Proceedings 60th, 2010, pp [25] S. A. Khan, N. Kumbhat, et al., "High current-carrying and highly-reliable 30µm diameter Cu-Cu area-array interconnections without solder," in Electronic Components and Technology Conference (ECTC), IEEE 62nd, 2012, pp [26] N. Kumbhat, A. Choudhury, M. Raine, G. Mehrotra, P. M. Raj, R. Zhang, et al., "Highly-reliable, 30µm pitch copper interconnects using nano-acf/ncf," in Electronic Components and Technology Conference, ECTC th, 2009, pp [27] V. Smet, M. Kobayashi, W. Tao, P. M. Raj, and R. Tummala, "A new era in manufacturable, low-temperature and ultra-fine pitch Cu interconnections and assembly without solders," in Electronic Components and Technology Conference (ECTC), IEEE 64th, 2014, pp [28] W. Tao, V. Smet, M. Kobayashi, V. Sundaram, P. M. Raj, and R. Tummala, "Modeling, design, and demonstration of low-temperature Cu interconnections to ultra-thin glass interposers at 20 µm pitch," in Electronic Components and Technology Conference (ECTC), IEEE 64th, 2014, pp [29] M. R. Pinnel, "Diffusion-related behaviour of gold in thin film systems," Gold Bulletin, vol. 12, pp , [30] G. O. Mallory, J. B. Hajdu, A. Electroplaters, and S. F. Society, Electroless plating: fundamentals and applications: American Electroplaters and Surface Finishers Society, [31] M. S. Colla, B. Wang, H. Idrissi, D. Schryvers, J. P. Raskin, and T. Pardoen, "High strength-ductility of thin nanocrystalline palladium films with nanoscale twins: Onchip testing and grain aggregate model," Acta Materialia, vol. 60, pp , 2// [32] K. Timpano, "Mechanical characterization of gold thin films for RF-MEMS," in Proc. Virginia Space Grant Consortium Student Research Conf, [33] M. Ozkok, "Direct EP and direct EPAG - Novel surface finishes for gold-, copper wire bonding and soldering applications," in Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 7th International, 2012, pp [34] D. F. Lim, J. Wei, K. C. Leong, and C. S. Tan, "Surface Passivation of Cu for Low Temperature 3D Wafer Bonding," ECS Solid State Letters, vol. 1, pp. P11-P14, January 1,

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