Interconnection M aterials, Pro cesses and Tools fo r Fine-pitch Panel Asse mb ly of Ult ra-thin Glass Substrates

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1 Interconnection M aterials, Pro cesses and Tools fo r Fine-pitch Panel Asse mb ly of Ult ra-thin Glass Substrates Vanessa Smet, Ting-Chia Huang, Satomi Kawamoto #, Bhupender Singh, Venky Sundaram, Pulugurtha Markondeya Raj and Rao Tummala 3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, USA # Namics Corporation, Niigata, Japan vanessa.smet@prc.gatech.edu Abstract The needs for higher speed and bandwidth at low power for portable and high-performance applications has been driving recent innovations in packaging technologies with new substrate platforms with finer lithographic capability and dimensional stability, such as ultra-thin glass, to enable offchip interconnections pitch scaling, down to 30µm. Copper pillar flip-chip thermocompression bonding (TCB) has subsequently become a pervasive technology in the past decade, and is now considered as the next interconnection and assembly node for smart mobile and high-performance systems. However, additional innovations are needed to achieve high-throughput thermocompression bonding on fragile and thin glass, with short cycle times and process conditions within HVM (high-volume manufacturing) tool capability. These include material advances in surface finishes and pre-applied underfill materials with built-in flux, along with a unique co-development strategy to provide highspeed solutions with optimized TCB profiles that consider the dynamic thermal behavior of high-density glass substrates, underfill curing kinetics, as well as tool compatibility. These innovations are the key focus of this paper. Finite element heat transfer and thermomechanical modeling were carried out to emulate assembly processes and compare the behavior of glass substrates to that of current technologies. Residual stresses created during the cool-down phase were extracted to help define process windows for stress management in interconnections, by fine control of intermetallics (IMC) formation. Emerging surface finish chemistries compatible with high-density wiring with sub- 10 m spacings, such as OSP or EPAG (electroless Pd, autocatalytic Au) finish, were also evaluated for their effect on the formed IMC systems. A new set of no-flow snap-cure underfill materials with high thermal stability, beyond existing conductive films or pastes, was developed in synergy with tools and processes for compatibility with advanced substrate technologies. Model predictions were validated with assembly trials on ultra-thin glass and organic substrates with 100µm thin cores. Design guidelines for bonding tools, materials and processes were finally derived, for high-speed thermocompression bonding, customized to the performance, reliability and cost needs of next-generation mobile and highperformance systems. Introduction Smart mobile and high-performance systems constitute two of the fastest moving markets, with aggressive increase in bandwidth, functionality and miniaturization requirements. These are met by increasing I/O densities for applications processors and logic devices, and added memory, following the shrinkage of the silicon die node. This unprecedented growth rate has led to significant advances in IC packaging technologies, including off-chip interconnections pitch scaling, projected to reach below 30µm in the coming decade. Traditional reflowed solder used for flip-chip assembly, despite their many advantages such as bump collapse and selfalignment, good wettability and accommodation of noncoplanarities and warpage, have reached their pitch limitation at 150µm in high-volume manufacturing, severely constraining I/O densities [1, 2]. Copper pillar flip-chip thermocompression bonding has become the technology of choice for further pitch scaling with consistently high yield and reliability [3, 4]. The Cu pillars typically have a thin SnAg solder cap that provides a limitedly-collapsible finepitch bump with higher flexibility compared to solid-state systems such as Au stud bumps. Thermocompression bonding is also highly beneficial for warpage reduction, as the heat is generally applied through the die, the substrate typically being maintained at a low temperature, ideally below that of the glass transition temperature of laminates. Precise and dynamic control of the thermal gradient and assembly sequence is however critical for warpage control, and subsequent potential cracking of the fine-pitch solder joints [5, 6]. Further, the use of no-flow underfills and non-conductive films or pastes (NCF or NCP) has been demonstrated as the most promising solution to handle ultra-thin low-k dies, protect the small and fragile Cu pillar interconnections and increase throughput by combining the assembly and underfilling steps [7-11]. Snapcuring of the pre-applied underfill in assembly was shown to reduce stress on the die, in the interconnections, and to further reduce substrate warpage [2]. A variety of pre-applied materials with built-in fluxing action have been developed by various research groups and by industry, for commercial solutions compatible with production tools and processes [12-16]. The composition of such materials, including fluxing agents, filler sizes and content, is finely tuned for viscosity and flowability control, adequate curing kinetics for highspeed bonding and enhanced reliability [16, 17]. The TC + NCP (thermocompression with non-conductive paste) process has been demonstrated at 25um pitch in lab-scale, and is readily in OSATs mass production at 40um area array pitch, qualified on die sizes of 10mmx10mm and below [2, 8]. However, a compromise has to be found between performance and cost, as the throughput of thermocompression processes is inherently limited by their serial nature in opposition to batch reflow. In parallel, emerging 2.5D and 3D integration trends reinforced the needs for low-cte substrates with high dimensional stability and sub-5µm lithographic design rules, such as silicon, low-cte laminates and more recently ultra /15/$ IEEE Electronic Components & Technology Conference

2 thin glass [18, 19]. Interposer technologies entered highvolume production in 2011 with Xilinx Virtex 7 products, while stacked memories have recently entered the market with HMC, HBM, DRAM and wide I/O technologies [6]. Innovations in surface finish and pre-applied underfill materials are required to maintain compatibility of current assembly processes with these advanced substrate platforms. Indeed, standard finishes like ENIG and ENEPIG face fundamental limitations with increased risks of bridging due to thick Ni when applied to high-density wiring with sub- 10um spacings between Cu traces [20]. Ni-free finishes, such as OSP or the new EPAG (electroless Pd, autocatalytic Au) finish developed by Atotech GmBH, have been proposed to address this challenge, but the elimination of the barrier layer leads to the formation of thicker intermetallic (IMC) systems because of faster interdiffusion rates, which in turns affect the final joints composition and their reliability [20]. Stress management in the package structure is addressed by the use of no-flow underfill materials. A new class of no-flow underfills with thermal stability beyond that of existing materials is also highly sought after to enable high-speed thermocompression bonding on high-density ultra-thin substrates with high thermal conductivity. Efforts are also ongoing to develop novel snap-cure materials with built-in fluxing action and thermal stability over 100 C, exceeding the throughput and reliability performance of current NCP and NCF materials. A synergistic approach towards material design, development and qualification of novel interconnection and assembly materials, tools and processes is thus required to advance thermocompression bonding to the next node, while maintaining throughput, cost and reliability performances. This paper reports a unique co-development strategy to address this grand challenge, introduced in the first section. It starts with the finite element heat transfer modeling of the assembly process to compare the behavior of glass to that of silicon and low-cte laminates. The effect of substrate thickness and density on steady-state and dynamic heat transfer was evaluated with respect to bonding heating profiles and throughput. Thermomechanical modeling was conducted to extract residual stresses produced during the assembly cool-down phase, especially at the solder-imcs interface. Novel surface finish chemistries such as EPAG and time-dependent plasticity (creep) of solders were considered in this parametric study. Interfacial stresses were found to dramatically increase with the reduction of solder volume subsequent to pitch scaling, bringing serious concerns for post-assembly failures. Daisy chain structures at 50µm inline and 40/80µm pitch were fabricated on test wafers and then assembled on 100µm-thick glass and organic substrates to verify the model predictions, leading to design guidelines for implementation of materials and processes for thermocompression bonding with considerations of chippackage interactions. Rationale for materials, tools and processes co-design A focused co-development strategy was defined with materials development, customization of assembly processes, and considerations to bonding equipment to achieve assembly of fine-pitch solder-capped Cu pillars on ultra-thin glass substrates. The interdependence of processes, particularly heating profiles, materials including surface finish, preapplied underfill and substrate core, package and interconnection structures and thermocompression tool is captured in Fig. 1. Fig. 1. Chip-package interactions with interdependence of assembly materials, processes and tools leading to codevelopment strategy. In particular, the heating profile is designed to attain the melting point of the selected solder alloy based on the dynamic heat transfer through the substrate. It is thus conditioned by the substrate thickness and material properties such as thermal conductivity or density, but also needs to take into account the tool capability, maximum admissible temperatures by the die and its low-k layers and thermal stability of the no-flow underfill material. In typical thermocompression flip-chip assemblies, the pre-applied underfill is dispensed on all bonding sites available on a substrate strip or panel. The temperature of the stage onto which the substrate is resting thus needs to stay below the thermal stability limit of the underfill throughout the process, to prevent any early flux activation, reaction or polymerization of the polymer that would degrade the assembly yield. As most no-flow underfills are epoxy-based systems, their thermal stability temperature limit is typically low, in the 70 90C range. To provide adequate stress relief and control the micro-bump shape, initiation of the underfill polymerization is required prior to cooling, thus limiting the time at reflow temperature. Polymerization in epoxy systems is a time- and temperature-dependent mechanism, illustrated in Fig. 2. Snap-cure NCPs are expected to reach this stage in under 3s at 260C [15]. Full cure of the underfill to attain the final stable properties is achieved by batch oven-cure. The thermal gradient between tool head and stage also conditions warpage and residual stresses in interconnections, and can lead to post-assembly early failures if not appropriately defined. Further, reliability of the Cu pillar joints is highly dependent on residual stresses created by cooling the assembly from the stress-free point corresponding to the solder liquidus temperature down to room temperature. Considering the viscoplastic nature of solder alloys implying a time-dependent plasticity, residual stresses proportionally increase with cooling rates. Stresses at the IMC-residual solder interfaces vary with the intermetallics to solder volume ratio, and can be further limited by a fine control of the 476

3 intermetallics growth. As interdiffusion occurs at a much faster rate in liquid phase, the thickness of intermetallics formed during assembly is mostly defined by the time spent over the melting point of the solder, and the intermetallic system formed, depending on the surface finish applied on the bond pad and the potential presence of a Ni barrier layer between the Cu pillar and its solder cap. Fig. 2. Illustration of the time- and temperature-dependence of the curing behavior of an epoxy-base no-flow underfill. With materials, processes and tools so intricately coupled, the ultimate goal is to develop global solutions for high-speed thermocompression bonding on ultra-thin glass considering chip-package interactions. Assembly process modeling In order to understand the specificity of assembly on highdensity ultra-thin glass substrates, thermal modeling was carried out to emulate the thermocompression bonding process. 2D FEM Model: Effect of Substrate Materials The simplified 2D finite element model (FEM) of a Si die assembly with fine-pitch Cu pillar interconnections shown in Fig. 3 was first built to compare the behavior of 100µm-thick glass substrates to that of silicon and organic (FR-4) substrates of the same thickness. The thermal properties of all substrate materials are reported in Table 1. Table 1. Thermal properties of silicon, glass and FR-4. Material property Silicon Glass FR-4 Thermal conductivity (W/m.K) Density (g/cm 3 ) Heat capacity (J/g.K) A standard production heating profile was applied as loading condition with the stage maintained at 70 C throughout the process and the tool head ramped up to a peak temperature of 400 C, considering the thermal stability limits of no-flow underfills and the bonding tool s capability. The steady-state temperature reached in the solder cap is represented in the graph of Fig. 3 for organic, silicon and glass substrates. The values should be used only for semiquantitative comparison purposes but not as absolute values because of model simplifications. The steady-state temperature strongly depends on the substrate thermal conductivity, its inherent capacity to dissipate heat conditioning its ability to create the necessary temperature gradient within the package structure to reach the melting point of the solder alloy. Solder caps are typically made of SnAg alloys of various compositions, with melting points in the C range. Glass exhibited a similar behavior as FR-4, with steady-state temperatures in the solder nearing its melting point. This was expected as glass inherently has similar properties as organic materials, qualifying as a thermally insulating material, as opposed to silicon which is an excellent thermal conductor, with a thermal conductivity an order of magnitude higher than that of glass and FR-4. However, it has been demonstrated that the thermal properties of glass could be made to match that of silicon by incorporating Cu-filled through-package vias in the glass core, acting as pathways for thermal dissipation [21, 22]. The thermal behavior of glass can thus vary from that of an insulating material like organics to that of a highly conductive material like Si depending on its metal loading, determined by routing metal layers and Cu-filled through-package and blind vias. This constitutes the specificity of assembly on highdensity glass substrates, with required customization of the heating profiles to the considered package structure. Fig. 3. 2D FEM heat transfer model and steady-state temperatures in solder cap of a Cu pillar flip-chip assembly formed at 70 C stage temperature and 400 C tool peak temperature, on 100µm-thick glass, silicon, and organic substrates, respectively. This simple modeling also highlights the need for higher stage temperatures to reach the melting point of solders when assembling on highly-conductive substrates. A new class of no-flow underfill with thermal stability above 100 C is thus required, which is very challenging in epoxy-based systems. 3D Single-bump Model: Steady-state & Dynamic Behaviors In order to predict the temperature distribution in assembly more accurately, a more realistic 3D FEM model was build, as shown in Fig. 4. The modeled package structure comprises of a 600µm-thick Si die and a substrate with a 100µm-thick glass core, coated on both sides by a 20µm-thick polymer acting as build-up layer to support Cu metal routing. The interconnection structure was an ultra-short Cu pillar, 5µm in height, with a 10µm solder cap, built on a Cu pad on the die 477

4 side and landed on a similar pad on the substrate side. The bump diameter was scaled using the standard half-pitch design rule applied in industry. A bump diameter of 25µm with a 50µm inline pitch was considered for the first evaluation and model calibration. To reduce the model complexity, the underfill material was not considered in this preliminary study. Adiabatic air convection at room temperature was applied as boundary condition on the microbump sidewalls, representing a worst-case scenario from a heat transfer standpoint, but an accurate emulation of assembly with flux. The temperatures of the stage and bond head were imposed as boundary conditions in the axial direction. was obtained for a h value of 100 W/m 2.K, which was applied in all further modeling. Fig. 5. Experimental set-up for calibration of h thermal convection coefficient, with a thermocouple pressed between a Si die and the bonder stage. Fig. 6. Experimental and modeling predictions of the steadystate temperature in bumps as a function of the tool peak temperature with parametric variations of h coefficient. Fig. 4. 3D FEM model of a single Cu pillar and solder cap interconnect between a Si die and a glass substrate with 2 metal layers. Based on Fourier s law of heat conduction, the steadystate temperatures reached in the bumps not only depends on the thermal loading, but also on the thermal resistances, in particular the contact resistances between the tool head and the Si die, and between the substrate and the bonder stage. These contact resistances are equipment-dependent, and can be implemented in the model by using a thermal convection boundary with an empirically defined thermal convection coefficient h. The experimental set up of Fig. 5 was used to fit the h coefficient, taking into account the interaction with the Finetech Matrix semi-automatic flip-chip bonder used for labscale developments. Expected temperatures for different thermal loadings were measured using a thermocouple. Simulations were run with three values of h coefficients: 50, 100 and 1000 W/m 2.K. A deviation between measurements and predicted values of the steady-state temperature in the bumps was expected due to the thermal resistance between die and thermocouple. The optimal thermal convection coefficient was thus selected by matching the slope of the experimental and modeling curves of the steady-state bump temperature as a function of the tool head temperature for a stage temperature of 70 C. As can be seen from the graph of Fig. 6, the best fit The evolution of the steady-state temperature achieved in the solder micro-bump as a function of the peak temperature of the bond head is plotted in Fig.7, for assembly on 100µmthick glass and FR-4 substrates, respectively. The predicted temperatures only vary by a few degrees for both substrates, confirming a similar heat transfer behavior in steady-state. A tool temperature of ~390 C is required to achieve the melting point of SnAg alloys (230 C) with a stage temperature of 70 C. For uniform reflow of the solder, higher bump temperatures, in the C range, are desirable. Stage temperatures of 90 C and above should thus be considered for good joint formation. Dynamic heat transfer modeling was carried out to evaluate the time required to reach steady state, which limits the assembly cycle time. Results are presented in Fig. 8 for assembly on 100µm-thick glass with 2 heating rates: 6 C/s which is the maximum heating rate achievable with the labscale equipment used in this study, and 200 C/s, which corresponds to production rates. If the steady-state temperature in the bumps can be achieved in under 10s in production conditions, it takes about a minute to reach the same condition with the lab-scale Finetech bonder. 478

5 3D Daisy Chain Model: Effect of Interconnection Pitch In order to evaluate potential thermal coupling effects between adjacent bumps with pitch scaling, a 3D daisy chain model comprising of a hundred Cu pillar interconnections stitched together was built, as shown in Fig. 9. Simulations were run for pitches in the µm range, with proportional re-scaling of the bump diameter to half the pitch, and with 2 different boundary conditions: air convection and presence of a no-flow underfill. In both cases, the predicted steady-state temperatures in the solder bumps varied by 0.1 C at most between the single-bump and daisy chain model, as confirmed by the values reported in Table 2. The dynamic behavior was also found identical, indicating that there is no strong coupling between adjacent bumps, even at ultra-fine pitch. Consequently, a single-bump model is sufficient to provide a realistic emulation of the assembly process. Fig. 7. Predicted steady-state temperature attained in solder cap as a function of the tool peak temperature, with stage temperatures of 70 and 90 C, and assembly on glass and organic substrates, respectively. Dynamic heat transfer is predominantly governed by the substrate density and thickness, and was expectedly found similar for ultra-thin organic and glass substrates. The bump temperature was found to increase at the same rate as the heating of the tool head, even in production conditions, indicating that these rates are below the theoretical limitation of the package structure. Assembly cycle times thus derive from thermocompression tools capability, and the targeted temperature gradient between tool head and stage. Higher stage temperatures of 100 C and above would subsequently result in an increase in assembly throughput. Fig. 8. Dynamic heat transfer modeling of assembly on 100µm-thick glass with tool peak temperatures of 350 (black), 370 (blue) and 400 C (red), a constant stage temperature of 70 C, and heating rates of 6 and 200 C/s. Fig. 9. 3D model consisting of 100 interconnections stitched in a daisy chain pattern for evaluation of interconnection pitch effect. Table 2. Steady-state temperature in the Cu pillar bump as a function of the interconnection pitch with a 100µm-thick glass substrate (assembly with a stage temperature of 70 C and peak tool head temperature of 400 C). Pitch / bump diameter (µm) Steady-state temp. in bump ( C) Single bump Daisy chain 20 / / / / / Experimental validation of model predictions A matrix of experiments was conducted with a simple test vehicle consisting of an IC chip bonded on a Cu-clad organic substrate to validate the model predictions. The thickness of the organic substrate was varied from 100 to 800µm. The 479

6 details of the test vehicle and bonding conditions are shown in Fig. 10. Assembly was carried out by thermocompression bonding with flux and capillary underfill. Fig. 12. Die-to-package measurements for bump collapse evaluation with varying substrate thicknesses and bonding conditions. Fig. 10. Test vehicle and bonding conditions for empirical validation of the modeling data. The heating profiles were evaluated based on the quality of the formed joints with regards to wetting and intermetallics formation, as well as collapse of the micro-bumps. The peak temperature of the tool was varied from 290 to 390 C for each substrate thickness, while the stage temperature was maintained at 70 C. Results from this empirical evaluation are reported in Fig. 11. While proper wetting was obtained at a tool peak temperature as low as 350 C for a 800µm-thick substrate, as confirmed by uniform IMC formation at the bonded interface, adequate solder melting was not achieved in the case of a 100µm-thick substrate, even when rising the tool temperature up to 390 C. These results are further confirmed by the die-to-package gap measurements, representative of the collapse of the micro-bumps, presented in Fig. 12. The minimum gap was obtained for the thickest substrate with uniform values from 350 C tool peak temperature. Adequate collapse was achieved from 390 C for the 400µm-thick substrate, but limited collapse was observed for the 100µmthick substrate in all conditions. As predicted by thermal modeling, a stage temperature higher than 70 C is required to achieve proper melting of the solder with ultra-thin substrates, with tool peak temperatures below 400 C. Fig. 11. Experimental matrix for thermal model validation: cross-section of assemblies showing IMC formation and solder wetting with varying substrate thicknesses and bonding conditions. As predicted by thermal modeling, a stage temperature higher than 70 C is required to achieve proper melting of the solder with ultra-thin substrates, with tool peak temperatures below 400 C. The stage temperature was raised to 90 C and the results from both series of experiments are compared in Fig. 13. Proper solder wetting and bump collapse could then be achieved with a peak temperature of 390 C. Fig. 13. Comparison of IMC formation and solder wetting with a 100µm-thick organic substrate with the bonding heating profile. A second test vehicle, emulating a mobile processor, was used to further validate these results, consisting of a 10mmx10mm Si die, 200µm in thickness, comprising ~5500 interconnections with 4 peripheral rows at 40/80µm staggered pitch, and a central area array at 150µm pitch in a daisy chain configuration. The micro-bumps were Cu pillars, 15µm in height, with a 2µm Ni barrier layer, and a 17µm-thick SnAg solder cap. The die was assembled on a 100µm-thick glass substrate with multilayered routing by thermocompression bonding with a stage and a tool peak temperature of 90 C and 390 C, respectively. Assembly was carried out with flux, and capillary underfill (CUF) was applied after completion of the bonding process. The assembly yield was confirmed by electrical measurements of the daisy chain resistances. The cross-section images of Fig. 14 show a good joint shape, with adequate IMC formation as indicated in the SEM image where the solder was etched to expose intermetallic compounds. 480

7 very little residual solder. The interconnection stack-up thus have to be carefully designed to balance plastic strains between the Cu pillar and the solder cap, while the assembly process needs to be finely adjusted to control the IMC-toresidual solder ratio. Fig. 14. Optical and SEM images of the cross-section of an assembly on a 100µm-thick glass, with Cu pillar and solder cap interconnections formed by thermocompression bonding with a stage and tool peak temperatures of 90 C and 390 C, respectively. These experiments thus confirm the modeling results, for both glass and organic substrates, highlighting the need for higher stage temperatures for bonding on high-density glass substrates. The heating profiles also affect residual stresses created in the package structure during the assembly cooldown phase as well as warpage, potentially leading to early failures by joint cracking [6]. Thermomechanical modeling was thus conducted to understand this interaction. Thermomechanical modeling: stress management Pitch scaling is accompanied by a reduction of the interconnection form factor, particularly of the solder volume to prevent bridging. The 2D axisymmetric FEM model of Fig. 15 was built to evaluate the residual stresses generated in a die-to-glass substrate package during the assembly cool-down phase. The interconnection stack-up comprises of a Cu pillar, 5µm in height and 10 µm in diameter, a 2 µm-thick Ni barrier layer, and a solder cap of varying thickness. A Ni barrier layer was also applied on the substrate pad to represent a standard ENIG or ENEPIG surface finish. A micron-thick layer of Ni 3 Sn 4 intermetallic was also considered, as would be expected by the end of the bonding process. The assembly was considered stress-free at the liquidus temperature of the SnAg solder, and cooled down to room temperature at a rate of 6 C/s. The von-mises stresses at the interface between residual solder and intermetallics are shown in Fig. 15 as a function of the solder height. A dramatic increase in stress from 20 to 170MPa can be observed as the residual solder height is reduced from 14 to 3µm, with an inflection point at about 6µm. This can be explained by the major difference in mechanical properties of solders and intermetallic compounds. Furthermore, considering the viscoplastic nature of solder alloys, these stresses vary with the strain rate, and consequently the cooling rate. Cooling in production conditions at 200 C/s yields an increase of the von-mises stress in the solder by 20%, and in the IMC layers by 7%. Such high stress levels can drastically shorten the fatigue life of solders, and even lead to post-assembly failures with joints cracking at the interface between species. These are further aggravated in subsequent process steps such as board-level reflows, resulting in a joint mostly dominated by IMCs with Fig D axisymmetric model of a Cu pillar with solder cap interconnection, and evolution of von-mises stress at the IMC-to-residual solder interface after assembly cool-down at 6 C/s with variations of solder volume. The latter point is illustrated in Fig. 16 with cross-section images of Cu pillar assemblies as-bonded and after moisture reflow test (MRT). While the bonding heating profile was kept same for both assemblies, the organic substrate s thermal conductivity varied with core thickness and metal loading. A higher temperature was reached in the bumps of the bottom substrate, and more time spent in liquid phase, resulting in formation of thicker IMCs. While both assemblies were perfectly yielded as-bonded, the daisy chains of the bottom one systematically failed after MRT. The joints were found composed of intermetallics only, with apparent Kirkendall voids and phase cracks as shown in Fig. 16. Cu pillar interconnects thus exhibit a higher sensitivity to process conditions with pitch scaling, which in turns narrows process windows and requires a higher degree of customization. Fig. 16. Cross-section of Cu pillar flip-chip assemblies on 2 organic substrates with different thermal conductivities, as bonded and after moisture reflow screening test. Thermocompression bonding was performed with a stage temperature of 70 C and a tool peak temperature of 390 C maintained for 5s. This mechanism is further exacerbated by the emergence of Ni-free surface finishes, where the barrier layer is eliminated for compatibility with high-density wiring on the substrate. OSP or the novel EPAG finish are promising 481

8 solutions for protection of Cu traces with sub-10µm spacings. Due to its limited thickness, the EPAG finish acts as an OSP and is entirely dissolved in the solder during assembly, resulting in direct bonding on bare Cu as depicted in Fig. 17. The intermetallic compounds formed thus differ from ENIG or ENEPIG systems, with formation of Cu 6 Sn 5 instead of Ni 3 Sn 4. The former grows 10 times faster than the latter in liquid phase, judging by their respective interdiffusion coefficients of µm 2 /s and µm 2 /s at 150 C. Thicker IMCs increase the risk of joint failures, thus imposing stringent requirements on bonding conditions for stress management. base composition to extract the material s limitations. Ongoing work consists of varying fluxing agents and fillers, leading to joint optimization of material properties and bonding processes. Fig. 18. Typical composition of a pre-applied material, highlighting material, tool and process interactions. Fig. 17. Intermetallics formation on different surface finishes: OSP, thick and thin ENEPIG, and EPAG [20]. No-flow underfill material development Stress management has become a critical bottleneck of fine-pitch flip-chip assembly that can be partly addressed with the use of pre-applied materials, such as no-flow underfills, NCFs or NCPs. The latter protect the thin low-k dies and fragile interconnections during bonding, enable a fine control of the joint shape and solder spread to alleviate risks of bridging, and results in a significant reduction of the overall warpage [2]. They also indirectly increase throughput by combining the assembly and underfilling steps. The development of a new class of pre-applied materials with thermal stability in the C range is essential in enabling high-speed thermocompression bonding on highdensity substrates with sub-100µm thicknesses. The material properties, including fluxing action, reaction speed, curing kinetics and final physical properties, have to be co-developed with the assembly process, taking into account the package and interconnection structures, heating profiles and the tool s capability. The ultimate goal is to improve the assembly throughput by shortening the cycle times to below 5s, while not compromising on reliability. Co-development efforts are ongoing by GT PRC and its industry partners to provide manufacturable solutions to this complex problem. The typical composition of pre-applied materials is summarized in the diagram of Fig. 18, with 3 major components: fillers, fluxing agent and curing system. The effect of each constituent on the overall process is detailed. A generic epoxy-based system containing a fluxing agent but no fillers was used as a base, and its composition was progressively modified to attain the expected performance. The first step in this approach was the qualification of the Conclusions This paper introduces a novel co-development strategy of materials, tools and high-speed processes to extend the applicability of fine-pitch thermocompression bonding to high-density ultra-thin glass substrates. As the thermal properties of glass substrates can be finely tuned by implementing through-package vias acting as thermal structures, bonding on glass requires highly customized processes taking chip-package interactions into account. Thermal and thermomechanical modeling were carried out to provide guidelines on heating profiles for stress management in interconnections and at die level. Bonding with higher stage temperatures was found necessary for assembly on substrates with sub-100µm thickness, which gives rise to new challenges in the thermal stability of pre-applied underfill materials. Emergence of surface finish chemistries deprived of barrier layers, intended to accommodate high-density wiring on substrates, also aggravated the stress level in interconnections. Stress and warpage management were highlighted as critical bottlenecks of advanced integration. It is addressed in this paper by the proposed development of a new class of no-flow underfills to meet the speed, cost and yield requirements for mass production. GT PRC and its industry partners are currently undertaking this task with considerations of advances in substrates and interconnections technologies and tools innovations to provide manufacturable solutions for high-throughput assembly of next-generation smart mobile and high-performance systems. Acknowledgments This study was supported by the Interconnections and Assembly industry program at Georgia Tech PRC. The authors would like to thank their industry partners to make this co-development effort possible, in particular Atotech GmbH for their support of surface finish, Kulicke & Soffa for providing a perspective on production thermocompression tools and Namics Corporation for the development of new pre-applied materials for high-speed assembly. 482

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