Advanced Copper Column Based Solder Bump for Flip Chip Interconnection

Transcription

1 Advanced Copper Column ased Solder ump for Flip Chip Interconnection Advanced Copper Column ased Solder ump for Flip Chip Interconnection Hiroshi Yamada, Takashi Togasaki, Kazuki Tateyama, and Kazuhito Higuchi Materials and Devices Research Laboratories Research and Development Center, Toshiba Corporation 33, Shin-Isogo Cho, Isogo-ku Yokohama 35, Japan Phone: Fax: Abstract A Flip Chip interconnection technology which enables reduction of strain in the bumps and uniform encapsulation of underfill resin has been developed by applying the advanced copper column based solder bumps. The solder bump has a copper column at the center of its bottom and is designed for high reliability flip chip interconnection. The copper column shape and the solder volume were obtained by employing Finite Element Model (FEM) simulation to analyze the plastic strain in the solder bumps. In the fabrication process, a microstructural resist patterning technique to form the copper column was precisely developed. Also, the electroplating technique to control the copper column shape and the solder volume has been developed by utilizing voltammetric analysis. The relations between the encapsulant flow and the encapsulation bump layout design parameters were obtained by the evaluation of the encapsulation flow characteristics under the LSI chip based on the laminar model. Concerning reliability, the thermal fatigue lifetime of the flip chip interconnection was found to be equal to or longer than that of the conventional interconnection. Key words: Flip Chip Technology, Copper Column ased Solder ump, Underfill Encapsulation Resin, and Reliability.. Introduction Flip chip interconnection technology is currently the most advanced interconnection technology and is widely used for high density and high speed assembly of products such as MCMs and personal electronic equipment. Recently, high speed mobile communication terminals and high density processing modules in high speed computers utilizing flip chip interconnection have been reported -4. For more than a decade, epoxy underfill resin has been used successfully to increase interconnection reliability while reducing the strain in the bumps 3. Recently, small stand-off height and high viscosity attribute to silica filler have made uniform encapsulation difficult. Furthermore, the pressure loss at the gap between the bumps obstructs the encapsulation flow and tends to cause void around the bumps 4. The underfill encapsulation is considered to become more difficult and bump obstruction more striking as a result of the trend toward longer chip size and higher I/O number. The authors have developed the flip chip interconnection technology which enables reduction of strain in the bumps and uniform encapsulation of underfill resin by applying the copper column based solder bumps. The solder bump has a copper column at the center of its bottom and its shape is designed for high reliability flip chip interconnection. Several types of solder bumps which have rigid pillar or stud made of Au, Cu, or Pb-5%Sn in Pb-63%Sn solder have been reported 5-7. y employing bumps of this type, it is possible to realize improved flip chip interconnection reliability since the stand-off height is sufficient to preclude any contact between the chips, thus, enabling fine pitch interconnection and uniform underfill encapsulation resin. Many types of copper pillars or column solder bumps have been proposed in view of their ease of fabrication compared with other metals such as Au or Pb-5%Sn 8. However, it has long been known that the large strain caused by the different deformation of each metal in the copper column based solder bumps decreases interconnection reliability 5. Recently, GA or CSP are made of FR-4 substrate which has 8µm ~ 35µm thick The International Journal of Microcircuits and Electronic Packaging, Volume, Number, First Quarter 998 (ISSN ) 5

2 Intl. Journal of Microcircuits and Electronic Packaging copper layer for terminal footprints 9. In the case of direct attachment of LSI chips onto FR-4 substrate for these packages by flip chip interconnection, it is necessary to make the same structure as for the conventional copper column solder bump, and thus the strain in this type of bump must be reduced in order to realize low cost, and high performance electronic products. This paper describes the flip chip interconnection technology which enables reduction of strain in the bumps and uniform encapsulation of underfill resin. The copper column design and solder volume were optimized to reduce strain in the bumps. A microstructural resist patterning technique and precise electroplating technique were developed to form the bumps for the optimized design. The encapsulation flow characteristics under the LSI chip were evaluated for uniform underfill resin. Also, the reliability of the flip chip interconnection in the case of utilizing the copper column based solder bump was also investigated in this work.. Design Parameters of Copper Column Solder ump The bump shape is decided based on the relation among the weight of LSI (G), the pressure balance of molten solder DP), and the surface tension of the molten solder (T). When the restoration force (F s ) is defined as the resultant force of DP and T, the bump height is calculated by the balance between F s and G as follows, D Fs Pπ πdt sinθ () P T + () R R circumference which is calculated from the radius R and the radius R. R r, R r + a, x r ( y b) + a Furthermore, the bump limited metallurgy of the substrate D P, that of the LSI chip D, and the bump height h j has the following relation, D DP b ( D DP ) a + h (4) j h j 4 4 r D a D / sin a θ r + ( h j b) And the solder bump volume is calculated as follows, V h j 0 πx dy The solution of equation (7) was calculated by numerical analysis using the data D 0.00mm and bh j /. From the above equations ()-(7), the values (a, b, r) and the design parameters (, D P, F s ) are represented as a function of h j. Also, the deformation volume of the bump after the reflow process was defined as follows, Dh j h 0 - h j (8) where h j is the bump height after reflow interconnection process, and h o is the bump height of F s 0. Figure shows the FEM simulation model for analyzing the strain in the bumps and investigating the effect of copper column height. The deformation of solder bumps which was characterized by the relative share displacement (Dl) and the relative axial displacement (D z) under thermal cycle test (TCT) (-65 C (30min)~5 C (30min)) condition was analyzed. The equivalent plastic strain (D g peq ) in solder bump was estimated by elastic plastic analysis. Furthermore, the thermal fatigue life of flip chip interconnection was predicted by the following equation which was obtained by another experiment, (3) (5) (6) (7) Figure. Schematic view of bump shape and its design parameters. Figure shows the schematic view of the bump shape and its design parameters. The side shape of the bump is decided based on the peq Nf ε (9) Figure 3 shows the results of calculated deformation volume of the solder bump using the data V5.5 x0 4 mm 3 which is for initial bump height of 70µm. The shapes of bumps are deformed and 6

3 Advanced Copper Column ased Solder ump for Flip Chip Interconnection their height decreases as the number of bumps per chip is reduced. In this Figure, also shown, the case of the LSI chip assembled on the.. Copper Column Solder ump Fabrication Process The bumps are fabricated by the electroplating method to control the copper column shape and the solder volume precisely. In order to fabricate the bump, a microstructural resist patterning technique was developed to control the bump height, the electroplating technique utilizing voltammetric analysis was developed. Individual fabrication processes are described in different literature 0,... Microstructural Resist Figure. FEM simulation model. substrate that has different pattern of solder dam. The experimental results show good agreement with the values obtained from the calculation results. The difference in the small bump density region may be dependent on the flux behavior that affects the surface tension of the molten solder. Figure 3 also shows the results of FEM simulation. oth of the equivalent values (D g peq ) decrease as the copper column height decreases. Particularly noteworthy is the fact that D g peq of encapsulated structure was an exceedingly small value compared with that of unencapsulated structure. From this D g peq calculation and prediction of Nf 50, the flip chip interconnection reliability of the copper column based solder bump can be expected to show excellent results if the underfill encapsulation resin is used. The bump height which decreases as the bump density is reduced must be kept at a sufficient value for a uniform underfill resin encapsulation. The uniform underfill resin encapsulation is carried out when the gap between the LSI chip and the substrate has a sufficient value. However, as shown in Figure 3, the bump height decreases in accordance with the reduction of bump density. As the encapsulant contains silica filler to reduce its CTE and the strain in the bump, small stand-off height and high viscosity attributable to silica filler make the encapsulation difficult. The copper column based solder bump releases this severe restriction and increases flip chip interconnection reliability, even if the number of bumps per LSI chip is few, as in the case of memory LSI chips or GaAs MMICs. The alkaline solubility of the positive type photoresist changes after the exposure, resulting in the differential dissolution of the exposed and unexposed parts as shown in Figure 4. This change can be explained in terms of two contrary effects: a dissolution inhibition effect in the unexposed area, and a dissolution promotion effect in the exposed area. The authors attempted to increase the dissolution effect parameter defined by the equation below, since the positive type photoresist can be developed sharply when the parameter V n /V o has a high value. Dissolutio n effect parameter : Vn / Vo Figure 4. Differential dissolution of the resist. γ (0) Figure 5 shows an SEM micrograph of a microstructural resist pattern. The vias of the resist had a 0µm pitch and a 5µm diameter and a 0µm depth and were arranged 5µm apart. These resolution values are sufficient to fabricate precise copper column solder bumps. Figure 3. Relation between bump height and deformation volume of the bump. Figure 5. SEM Photograph of the microstructural resist pattern. The International Journal of Microcircuits and Electronic Packaging, Volume, Number, First Quarter 998 (ISSN ) 7

4 Intl. Journal of Microcircuits and Electronic Packaging.3. Electroplating Technique for Copper Column Figure 6 shows the electroplating apparatus which was used in the bump fabrication process. The electrolyte was recalculated so as to be sufficiently agitated on the wafer surface. The final current distribution at the wafer surface is mainly produced by the primary current distribution which depends on the equipment design and the ion concentration. Figure 8. In the case that the gap width (d) is finite, the fluid flux (Q) in parallel plate is less than the value represented by equation () using the coefficient C b to consider the effect of sidewalls. Figure 7. SEM photograph of the fabricated copper column based solder bump. n Q C A h P () b Figure 6. Schematic depiction of the electroplating apparatus. Primary current distribution was improved by optimizing equipment design such as the dimension between the wafer and the anode. Furthermore, the plating rate distribution due to the ion concentration was considered as follows. The ion concentration distribution at the wafer surface is influenced by the electrolyte flow conditions. The cyclic voltammetric stripping (CVS) method in which some platinum working electrodes are plugged in the wafer was used to investigate flow influence. The CVS method enables sensitive evaluation of plating rates, and thus can clarify the ion concentration. The plating rates on each working electrode were measured while ignoring the influence of electrolyte resistance and electrode surface condition. As a result of this investigation, the final current distribution was improved and the plating current distribution was controlled within ±0% under optimal conditions. This value satisfies the specification for copper column based solder bumps. Figure 7 shows the fabricated copper column based solder bump on the LSI chip. where C b is a constant that depends on the value of d/h. Encapsulant flow can be modeled as in Figure 8 using the parallel plate model with infinite width for area without bump and with finite width (d) for bump area. The flux of the fluid can be represented for the bump area as equation () and for the area without bump as equation (3) using this model, 3. Flow Characteristics in Resin Encapsulation 3.. Effect of ump Gap and ump Pitch on Driving Force Loss The model of the laminar flow in parallel plate with finite width was used to evaluate the driving force loss at the bump gap 3 in Figure 8. Flow model of encapsulant for LSI with peripheral bump. Q P Cb A h d.86 P ().86 (3) Q A h P Furthermore, the driving force loss (R Q) can be represented as equation (4), 8

5 Advanced Copper Column ased Solder ump for Flip Chip Interconnection R Q P P (4) Q in equation () equals Q in equation (3) due to the flux succession. Thus, the coefficient of the driving force loss (R) at the bump gap is given by equation (5), P P h Q A.86 P d C b R (5) rate and the flow time in this experiment is shown in Figure 9 and the point at which the flow rate decreased discontinuously is also shown. It is recognized that a discontinuous decrease of flow rate occurs when the flow rate decreases to the region of 6.0x0 - mm/s ~ 6.8x 0 - mm/s. It is considered that the filler packing occurred at this moment and transportation limit velocity is considered to be in the region of 6.0x0 - mm/s ~ 6.8x0 - mm/s. The condition necessary for complete encapsulation is considered to be that the flow rate is Defining the bump size factor (b) as equation (6), R is considered to be directly proportional to b,.86 P h d C b β (6) The relation between the experimental R and the calculated b shows good correlation and the obstructive effect of the bump on the encapsulant flow can be calculated using this relation. R is given as equation (7) from the relation between R and the calculated b. R.77 0 (7) 7 β (Pa s/m) Substituting equation (7), the flow distance L and the flow rate dl/dt for LSIs that have peripheral bump arrangement are represented as equations (8) and (9). where dl dt ( a β + a h t) a3 β L (8) a a a , , ( a β + a h ) a4 h t where a x 0-3. (9) (9) Figure 9. Relation between flow rate and flow time. higher than the transportation limit velocity. Judging from these factors, the condition necessary for complete encapsulation was defined as the flow rate is higher than 7.0x0 - mm/s until the encapsulation is complete. The maximum chip size permitting a complete encapsulation (Lmax) can be calculated by applying equation (9) under the condition mentioned above. The Lmax for LSIs with peripheral bump arrangement (LmaxP) is given by equation (0) using the bump size factor (b), 0.94 L max P a h a β (0) 5 6 where a x0-3, a 6.3x0-6. The relation between the LmaxP for peripheral bump arrangement and the stand-off height (h) or bump pitch (P) is shown in Figure 0. This result enables the uniform underfill encapsulation resin even if a lot of silica fillers were distributed in the resin to reduce its coefficient of thermal expansion (CTE). 3.. Encapsulation for Peripheral ump Arrangement The flow rate of samples with stand-off height of 30 µm discontinuously decreased when the flow distance reached 5.5mm or 6.0mm and the encapsulation was incomplete. It is considered that the flow partially stopped due to packing of silica filler. It is known, in fluid flow including powder, that packing of powder occurs if the range of fluid velocity is less than a certain value called the transportation limit velocity 3. The relation between the flow Figure 0. Relation between LmaxP and bump pitch. The International Journal of Microcircuits and Electronic Packaging, Volume, Number, First Quarter 998 (ISSN ) 9

6 Intl. Journal of Microcircuits and Electronic Packaging 4. Flip Chip Interconnection Reliability 5. Conclusion Figure shows a cross-sectional view of the flip chip interconnection employing the copper column based solder bump. The LSI chip has 34 bumps. The bump size is 00µm and the pitch is 00µm. The copper column is 0µm and the copper wiring layer for footprint is 0µm. The bump height is 50µm and this Figure presents a sufficient value for uniform encapsulation. Figure shows the dependence of cumulative failure % on the number of TCT (-65 C(30min)~5 C(30min)) cycles using FR-4 substrate. The samples were considered to be failures when the bump resistance reached 00 mw. The change of bump resistance during TCT was monitored by the four probe method. The flip chip interconnection technology which enables reduction of strain in the bumps and uniform encapsulation of underfill resin has been developed applying the copper column based solder bump. The bumps are designed by employing the FEM simulation model, fabricated microstructural resist and precise electroplating technique. Encapsulation flow characteristics under the LSI chip were evaluated based on the viscous laminar model and the obtained relation between the maximum chip size permitting the encapsulation and the encapsulation parameters of h, d, and P. Furthermore, the thermal fatigue lifetime of the flip chip interconnection was found to be equal to or longer than that of the conventional interconnection. The copper column based solder bump flip chip interconnection technology is especially effective in the case of FR-4 substrate for low cost and high performance electronic products. Acknowledgment Figure. Cross-sectional view of the flip chip interconnection structure. The reliability of the solder bumps depended on the CTE of encapsulated underfill resin and increased as the CTE of the resin decreased. Particularly noteworthy is the fact that the thermal fatigue lifetime of the copper column based solder bump is equal to or longer than that of the non-copper column solder bump. This effect is due to the flip chip interconnection reliability is mainly dependent on the mechanical characteristics of the underfill resin. Figure. Dependence of cumulative failure % on the number of thermal cycle test. The authors are grateful to Dr. Y.Uematsu and Mr. M. Saito for their encouragement throughout this work, and would also like to thank other members of their group for assistance with the experiment. References. Rao R.Tummla, et al., Overview of Packaging for Enterprise System/9000 ased on the Glass Ceramic Copper/Thin Film Thermal Conduction Module, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, CHMT, Vol. 5, No. 4, pp , August 99.. T. Togasaki et al., ump Interconnection for Chip Components and LSI Chips for High Density Modules, Proceedings of the International Microelectronics Symposium, ISHM 94, oston, Massachusetts, November 5-7, pp. 66-7, F. Nakano et al., Resin-Insertion Effect on Thermal Cycle Resistivity of Flip Chip Mounted LSI Devices, Proceedings of the International Microelectronics Symposium, ISHM 87, Minneapolis, Minnesota, September 8-30, pp , D. Suryanarayana et al., Enhancement of Flip Chip Fatigue Life by Encapsulation, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, CHMT, Vol. 4, No., pp. 8-3, March G.G. Heinen et al., Multichip Assembly with Flipped Integrated Circuit, Proceedings of the International Microelectronics Symposium, ISHM 89, altimore, Maryland, October 4-6, pp , I. Shoji et al., Thermal Fatigue ehavior of Flip chip Joint 0

7 Advanced Copper Column ased Solder ump for Flip Chip Interconnection and Shear Creep Property, Third Symposium on Microjoining and Assembly Technology in Electronics, Yokohama, Japan, February 6-7, pp , S. Fujiuchi et al., Collective Screen Printing for Carrier ump and SMT Pads, Proceedings of the 995 Japanese International Electronics Manufacturing Technology, IEMT Symposium, Omiya, Japan, December 4-6, pp. 09-, R.R. Tummala, et al. Editors, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, K. Doi et al., Prediction of Thermal Fatigue Life for Encapsulated Flip Chip Interconnection, Proceedings of the International Microelectronics Symposium, ISHM 95, Los Angelos, California, October 4-6, pp. 47-5, Hiroshi Yamada et al., A Fine Pitch and High Aspect Ratio ump Array for Flip Chip Interconnection, Proceedings of the International Electronics Manufacturing Technology, IEMT Symposium, altimore, Maryland, September 8-30, pp. 889, 99.. Hiroshi Yamada et al., A Fine Pitch and High Aspect Ratio ump Fabrication Process for Flip Chip Interconnection, Proceedings of the 995 Japanese International Electronics Manufacturing Technology, IEMT Symposium, Omiya, Japan, December 4-6, pp. -4, Kazuhito Higuchi et al., Advanced uild-up Wiring Technology for MCM-D/L, Proceedings of the International Microelectronics Symposium, ISHM 96, Minneapolis, Minnesota, October 8-0, pp , Takashi Togasaki et al., Flow Characteristics in Resin Encapsulation for Flip chip Interconnection, Proceedings of the International Microelectronics Conference, IMC, pp , April 4-6, 996. About the authors Mr. Hiroshi Yamada received a.e. Degree from Department of Synthetic Chemistry Nagoya University, Japan, in 986. He joined Toshiba Corporation in 986 and working at Materials and Devices Research Laboratories in the Research and Development Center, where he has been working on research on the assembly and packaging technology. He is currently the research scientist of Materials and Devices Research Laboratories, and has been developing the high density and high speed interconnection technology. He is a member of the Society of Polymer Science, Japan, IEICE, IMAPS, and IEEE. Mr. Takashi Togasaki received a.e. Degree in Electronics Engineering from Tohoku University, Japan, in 990. He joined Materials and Devices Research Laboratories, Toshiba Corporation in 990. Since then, he has been primarily engaged in research and development on high density and high speed interconnection technology. Mr. Togasaki is a member of the IEICE. Mr. Kazuki Tateyama received.e. and M.E. Degrees in Applied Physics from Hokkaido University, Sapporo, Japan, in 99 and 994, respectively. He joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan, in 994. He is engaged in the research and development of high density and high speed interconnection technology. Mr. Tateyama is a member of the IEICE. Mr. Kazuhito Higuchi received.e. and M.E. Degrees in Electrical Engineering from Tokai University, Japan, in 989 and 99, respectively. He joined Materials and Devices Research Laboratories, Toshiba Corporation in 99. Since then, he has been primarily engaged in research and development on high density multichip module technology. Mr. Higuchi is a member of IMAPS. The International Journal of Microcircuits and Electronic Packaging, Volume, Number, First Quarter 998 (ISSN )