UNIVERSITI MALAYSIA PERLIS. Test 1 Session 2008/2009 Semester I. 6 th August EMT 453 Semiconductor Packaging [ Pembungkusan Semikonduktor ]

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1 UNIVERSITI MALAYSIA PERLIS Test 1 Session 2008/2009 Semester I 6 th August 2007 EMT 453 Semiconductor Packaging [ Pembungkusan Semikonduktor ] Masa : 1 jam Please make sure that this question paper has TEN (10) printed pages including this front page before you start the examination. This question paper has SEVEN questions. Answer any FIVE questions only. Sila pastikan kertas soalan ini mengandungi SEPULUH (10) muka surat yang bercetak termasuk muka hadapan sebelum anda memulakan peperiksaan ini. Kertas soalan ini mengandungi TUJUH soalan. Jawab mana-mana LIMA soalan sahaja.

2 Question 1 Briefly explain the microsystem and microelectronics packaging? Microsystem is a microminiaturized and integrated system based on microelectronics, RF, photonics, micro-electro-mechanical systems, and packaging technologies. [6 marks] Microelectronics is based on three circuit elements; transistors, capacitors and resistors, fabricated at sub micron dimensions as an integrated circuit or IC and is measured in micrometer (µm) scale. Question 2 Sketch the illustration of the below statement 1. Peripheral Interconnection 2. Area Array Interconnection [4 marks] Question 3 Imagine you are one of the package design engineer and you have a functional ICs that will be ready soon to be packaged. Explain at least THREE (3) importance criteria or requirement that should be taken or fulfill before package the ICs. [9 marks] Must provide acceptable electrical properties, including capacitance, resistance and inductance. IC assembly technologies should provide a low cost solution for the electrical interface between the chip and package. High throughput manufacturing. High reliability. Repairability or replaceability where interconnection between IC and package should provide removal of the failed IC. Question 4 Name the package technology as shown in Figure 1 (a) to (c) [9 marks] (a) (b) (c) (d) (e) (f) 2

3 Figure 1 : Package Technology (a) Dual In Line Package (b) TAB (c) QFP. (d) Flip Chip (e) Pin Grid Array (f) Single in line Package Question 5 i. Briefly explain why electronic interconnection and packaging technology should involve multidisciplinary field? ii. [2 marks] List down FIVE different professional fields often needed when interconnection and packaging technology is used for hardware realisation of an electronic system or product. Product development should involve experts from the various fields, and the interdependence of the fields may be the most important to make a good product. Electronics Materials properties and materials compatibility Mechanics Chemistry Metallurgy Production technology Reliability, etc. [5 marks] Question 6 Describe the typical development phases for serial product development from the conceptual idea to established production. i. This is best done as a graphic description with explaining text. ii. [7 marks] With your own word, explain why there generally is a heavy time pressure for finishing the development work. [9 marks] 3

4 Market research Pre-study Gives product idea Gives product suggestion Defining overall specifications Gives definition of product, simulation/lab model of critical parts Prototype A Main principles analyzed, important parts implemented, technology chosen Prototype B Detailed design, correct form and components. Ready for industrialization. Industrialization Prototype adapted to producability in available production equipment. New production line built if needed, pilot series made. Marketing started, service planned Full scale production Product sale, maintenance, service The development starts with market investigations, and a description of what properties and specifications the market needs. This is coupled to our own ideas for the new product. The ideas are refined and made concrete during several rounds of studies and evaluation. Then the implementation starts. The main specifications and the main functional blocks are defined, and simulations are performed. Critical parts and details are made in hardware. Several generations of lab models and prototypes are made, evaluated and modified. At each stage the model is made more like the production version. At each stage a new decision is made: Do we still believe there is a market for the product, with the performance and cost we can obtain? It is easy to discontinue development at an early stage, and little money is lost, but it is very costly to discover that the market is not there after full production has started. It may also be concluded that the development is too slow and more resources should be allocated to speed things up. In the first period expenses for development and industrialisation accumulate. The profit comes later, during the full scale production and sale 4

5 Question 7 Gordon Moore predicts that the transistors on a chip double every 24 months. This increased product functionality because of more transistors on the single ICs. Discuss the THREE (3) complexity and challenges in perspective of packaging to support Moore s law. [9 marks] Silicon to package to board interconnection, example flip chip package with high I/O thus more functionality can be added. Within package interconnect example narrower line (to provide high density wiring) and micro via. These provide more I/O to product. Power management since the quantity of transistors is increasing, more heat is produced internally, so it need good thermal conductivity to dissipate the generated heat. Need good understanding of heat transfer mechanism, material, metallurgical properties Integration of functionality such as silicon level integration (function combined on single chip) and package level integration (stacked discrete chips and packages) Question 8 Describe the detailed process of how the die is separated from the wafer. Process of Die Separated from wafer [8 marks] Wafer mounting is the process of providing support to the wafer to facilitate the processing of the wafer from Wafer Saw through Die Attach. During wafer mounting, the wafer and a wafer frame are simultaneously attached on a wafer or dicing tape. The wafer frame may be made of plastic or metal, but it should be resistant to warping, bending, corrosion, and heat. The dicing tape (also referred to as a wafer film) is just a PVC sheet with synthetic adhesive on one side to hold both the wafer frame and the wafer. Wafer saw follows wafer mountingis the step that actually cuts the wafer into individual dice for assembly in IC packages The wafer saw process consists of the following steps: 1) the frame-mounted wafer is automatically aligned into position for cutting; 2) the wafer is then cut thru its thickness according to the programmed die dimensions using a resin-bonded diamond wheel rotating at a very high rpm; and 3) the wafer goes through a cleaning process using high pressure DI water sprayed on the rotating workpiece and then dried by air-blowing. Question 9 Wire bonding is the dominant technology used in 1 st level interconnection. i. State three types of wires that normally used in wire bonding [3 marks] ii. List down and explain at least FOUR out of eight possible metallurgical systems involved wire bonding process. [8 marks] iii. Sketch the possible process optimization flow in developing and improving wire bonding process. [5 marks] Gold wire, Aluminum Wire and Copper Wire 5

6 Au-Au system Gold wire bonded to a gold bond pad is extremely reliable because the bond is not subject to interface corrosion, intermetallic formation, or other bond-degrading conditions. Even a poorly welded gold-gold bond will increase in strength with time and temperature. Gold wire welds best with heat although cold ultrasonic Au-Au wire bonds can be made. Either thermocompression or thermosonic bonds are easily and reliably made. Thermocompression bondability, however, is strongly affected by surface contamination. Au-Al system Au-Al welding system is the most commonly used in wirebonding process. However, this bonding system can easily lead to formation of Au-Al intermetallic compounds and associated Kirkendall voids. The formation can be accelerated with the temperature and time of the operational life. There are five intermetallic compounds that are all colored: Au5Al2 (tan), Au4Al (tan), Au2Al (metallic gray), AuAl (white), and AuAl2 (deep purple). AuAl2 can initially form in the interface between gold and aluminum during bonding process even at room temperature and could transform to other Au-Al compounds depending on the temperature, time and bonding configurations. Therefore, this system often presents a problem in reliability of the bonds. Au-Cu system Bonding gold wires to bare copper lead frames can cause the formation of three ductile intermetallic phases (Cu3Au, AuCu, and Au3Cu) with overall activation energies of 0.8 to 1 ev. The formation of these intermetallic compounds can decrease the bond strength at higher temperatures ( oC) as a result of Kirkendall voiding. The degradation is apparently dependent on the microstructure, weld quality, and impurity content of the copper. Cleanliness of the bonding surface is extremely important to ensure good bondability and reliability in Cu-Au systems. In addition, if polymer material is used for die attach, the polymer must be cured in an inert atmosphere to prevent oxidation. Au-Ag system The Au-Ag wire bond-system is very reliable for very long times at high temperatures. This bond system does not form intermetallic compounds and does not exhibit interface corrosion. Gold-wire bonds to silverplated lead frames have been successfully used in high production for many years. Bondability problems can be caused by contaminants like sulfur. Thermosonic Au-Ag bonding is usually performed at high temperature approximately 250oC) which dissociates thin silver-sulfide films thus increases bondability of silver. Al-Al system The aluminum- aluminum wire bond system is extremely reliable because it is not prone to intermetallic formation and corrosion. Aluminum wire on aluminum metallization weds best ultrasonically, although a thermocompression bond can be produced by high deformation. Al-Ag system Aluminum wire bonded to a silver-plated lead frame is often used in thick-film hybrids (usually in alloy form with Pt or Pd). The Ag-Al phase diagram is very complex, with many intermetallic phases. Kirkendall voids can occur in this metal system, but typically at temperatures higher than the operating range of the microcircuits. In practice, Ag-Al 6

7 bonds are seldom used because of their tendency to degrade due to interdiffusion and to oxidize in the presence of humidity. Chlorine is the main driving element of the corrosion process. Aluminum wires with large diameters are routinely bonded to Pd-Ag thick-film metallization in automotive hybrids. However, the bonding surface must be prepared by washing with solvents, followed by careful resistivity-monitored cleaning in deionized water. Then the hybrids are covered with a silicone gel for further protection. Al-Ni system Al-Ni bonds using large diameter, >75 mm, aluminum wires are less prone to Kirkendall voiding and galvanic corrosion, thus more reliable than Al-Ag or Al-Au bonds under various environments. This system has been used in high production on power devices and high-temperature applications such as aircraft turbine blades for over fifteen years. In most cases, the nickel is deposited from electroless boride or sulfamate solutions, which results in reliable bonds. However, phosphide electroless nickel solutions that codeposit more than 6 or 8% of phosphorous can result in both reliability and bondability problems. The main difficulty encountered when bonding to nickel plating is bondability rather than reliability due to nickel surface oxidation. Thus, packages should be bonded soon after they are Ni-plated, protected in an inert atmosphere, or chemically cleaned before bonding. Changing bonding machine schedules, such as impacting the toolwire-plating with the ultrasonic energy applied, can improve bondability to slightly oxidized nickel surfaces. Various surface preparation techniques (such as sandblasting) are sometimes applied before or after Ni plating to increase bondability. Cu-Al system Copper wire can be bonded to both gold and aluminum substrate. Au-Cu system has been discussed before. For Cu-Al system, there exist five intermetallic compounds favoring the copper-rich side. Thus, there is the possibility of various intermetallic failures similar to those of Au-Al system. However, intermetallic growth in Cu-Al bonds is slower than in Au-Al bonds. The intermetallic growth in Cu-Al bonds does not result in Kirkendall voiding bur lowers the shear strength at o C due to the growth of a brittle CuAl2 phase. In the temperature range oC, bond strength significantly decreases with the increase of the total intermetallic thickness. The rate of Cu-Al intermetallic formation relies on the ambient atmosphere composition. For example, the copper-aluminum bond system is adequately reliable as long as some oxygen is present in the package because Cu oxide prevents or inhibits the growth of void-like grooves under the bond. However, the presence of Cl contamination and water can cause corrosion of the aluminum metallization containing copper-aluminum intermetallics. 7

8 To develop and improve a production, the key stages generally include initial process design and development, process characterization, process control, as well as process optimization. These stages form a continuous loop between characterization and control, with periodic optimization and development, as shown in the following procedure diagram. Question 10 Briefly explain the semiconductor packaging process as below. a. Wafer Backgrinding b. DTFS (Deflash, Trim, Form and Singulate) c. Sealing d. Electrical Testing [16 marks] Wafer backgrinding - Is the process of grinding the backside of the wafer to the correct wafer thickness prior to assembly. Also referred to as 'wafer thinning.' Deflash - removal of flashes from the package of the newly molded parts.. Flashes are the excess plastic material sticking out of the package edges right after molding. Trim - cutting of the dambars that short the leads together. Form - forming of the leads into the correct shape and position. Singulation - cutting of the tie bars that attach the individual units to the leadframe, resulting in the individual separation of each unit from the leadframe Sealing is the process of encapsulating a hermetic package, usually by capping or putting a lid over the base or body of the package Leadfinish is the process of applying a coat of metal over the leads of an IC to: 1) protect the leads against corrosion; 2) protect the leads against abrasion; 3) improve the solderability of the leads; 4) improve the appearance of the leads. 8

9 There are two widely used leadfinish techniques in the semiconductor industry, namely, plating and coating. 9