Chemical/Mechanical Balance Management through Pad Microstructure in Si CMP

Transcription

1 Chemical/Mechanical Balance Management through Pad Microstructure in Si CMP Post CMP Cleaning Austin 2017 Ratanak Yim (Viorel Balan) R. Yim 1,2,5, C. Perrot 2, V. Balan 1, P-Y. Friot 3, B. Qian 3, N. Chiou 3, G. Jacob 3, E. Gourvest 2, F. Salvatore 4, S. Valette 5 1 CEA LETI, Univ. Grenoble Alpes, 2 STMicroelectronics, 3 Dow Electronic Materials, 4 ENISE, 5 Univ. Lyon, Ecole Centrale de Lyon

2 Si CMP Challenges for 3D Monolithic CoolCube TM SiO 2 SOI wafer Bonding Interface Si SiO 2 Si Si CMP Bonding Interface Si First gate fabrication Insulator planarization Direct bonding Second gate fabrication Perfect surface quality in order to build the 2 nd transistor Planarization Challenges: Si Thickness Control :SPEC < 10nm + Si Range < 1nm Multilayer metal contact Excellent Silicon Surface Quality with Low Material Consumption 2

3 Outline Chemical and Mechanical Synergy of the CMP Process Chemical action Mechanical action Correlation Results Between Wafer Surface Quality and Pad Microstructure in Advanced Si CMP Pad CMP Si Wafer Conclusion 3

4 CMP: CoMPlex Process SYNERGY between : CHEMICAL action SLURRY Chemistry MECHANICAL action PAD + Abrasive particles CMP Surface Chemical Modification Mechanical Removal Material Chemical/Mechanical Balance to Adapt to Each CMP Process 4

5 Pad Characteristics and its Actions PAD CHEMICAL action Pores + Grooves à Slurry Transport MECHANICAL action Pores + Asperities à Wafer Contact CMP The Pad Plays a Major Role in the Chemical/Mechanical Balance of the CMP Process 5

6 Pad Porosity Advanced Polishing Pad Conventional Polishing Pad Pores SEM Cross section SEM Cross section Item Pore size Porosity Pad A Extra Small Medium Pad B Small High Pad C Small Extreme high Pad D Large High 4 Pads with Different Pore Sizes and Porosities Evaluated for Advanced Si CMP 6

7 Blanket Silicon Wafer Polishing Conditions Polishing Tool: LK PRIME TM POLISHER CLEANER P3 P2 P1 Cleaner A Cleaner B Only one CMP process step P4 metrology Consumables: Pad: Dow Pads DD: 3M Brush or AF38 DD Slurry: High Purity Colloidal Silica Process Conditions: Pressure: 1.5psi Rotation: Platen at 43 rpm Flow: 200 ml/min Downforce: 7 lbf (ex-situ conditioning) Same Conditioning to Compare Intrinsic Pad Properties 7 ICPT2016 Cédric Perrot

8 Pad and Wafer Characterizations Pad Characterization: Pad Roughness Parameters Height Distributions Asperities Properties Pad Wafer Characterization: Si Wafer Wafer AFM Topography Wafer Wafer AFM Distribution Wafer Surface Roughness AFM Height Distributions Defect Level (SP2) Si RR (Precision Balance) Wafer Surface Quality = f (Pad Texture Parameters) 8 ICPT2016 Cédric Perrot

9 Pad & Wafer Roughness Correlation Results Conventional Polishing Pad Advanced Polishing Pad Pad Sq = 5-10µm Si Wafer Rq = 1,3A Wafer Roughness (A) Pad Conventional pad Advanced pads Sq = 23µm Si Wafer Pad Roughness (µm) Rq = 1,8A Low Pad Surface Roughness = Low Wafer Surface Roughness 9

10 Pad & Wafer Roughness Correlation Results Advanced Polishing Pad Conventional Polishing Pad 4.0 Wafers polished on Advanced pads 3.5 Pad Pad 3.0 Sq = 5-10µm Si Wafer Frequency (a. u.) 2.5 Wafer polished on Conventional pad 2.0 Sq = 23µm 1.5 Si wafer (pad A) Si wafer (pad B) Si wafer (pad C) Si wafer (pad D) Rq = 1,3A Si Wafer Rq = 1,8A Wafer surface height (nm) Low Pad Surface Roughness = Low Wafer Surface Roughness 10

11 Wafer Surface Quality Sq Wafer Surface Quality Sp Lower Post CMP SI Roughness with Smaller Pad Asperities Wafer Surface Roughness Driven by Pad Asperities Height: Atomic Si Planarization 11

12 Pad Texture Open Pad Open Texture Sz Texture Open = Empty Volume/Projected Area Low Pore Size = Low Texture Open 12

13 Pad Texture Open Inpact on RR & Sq Wafer Surface Quality RR Increasing Open Pad Texture Increase RR but Decrease Surface Quality à Chemical Effect of Slurry 13

14 Pad Texture Open Impact on RR & Defectivity Post CMP DEF RR Increasing Open Pad Texture Increase RR and Decrease Defectivity Level 14

15 Si Wafer Quality Surface & Pad Texture Open Si Wafer Si Wafer Removal Roughness Rate (nm/min) (nm) Si Wafer Defect Level Conventional Pad Large Pore Size = CHEMICAL action Advanced Pad Conventional Pad Pad Pad Texture Open (µm) Pad Texture Open Open (µm) (µm) Lower Higher Si Wafer Si Removal Defect Roughness Level Rate with High with Low High Pad CMP Texture Si Open Advanced Pad Small Pore Size = MECHANICAL action Chemical / Mechanical Balance in Si CMP Can Be Managed Through Pad Microstructure 15

16 Conclusion CHEMICAL action MECHANICAL action PAD SLURRY Chemistry + Abrasive particles CMP Pores + Grooves à Slurry Transport PAD CMP Pores + Asperities à Wafer contact Large pore size à Higher RR à Lower defectivity level Small pore size à Better Surface Roughness CMP Si Chemical/Mechanical Balance Management through Pad Microstructure Advanced Pad & Advanced Wafer Characterizations: Better Understanding of Roughness Transfer from Pad to Wafer Achieve Better CMP Performance 16

17 Thank you for your attention Leti, technology research institute Commissariat à l énergie atomique et aux énergies alternatives Minatec Campus 17 rue des Martyrs Grenoble Cedex France

18 Planche de pictos DISPOSITIFS MÉDICAUX INTERNET DES OBJETS CAPTEURS IMAGING SENSOR SERVEURS ET CALCUL INTENSIF NANO ELECTRONIQUE COMPOSANTS PHOTONIQUE ÉNERGIE ÉLECTRONIQUE DE PUISSANCE SÉCURITÉ RF 18