Balancing Technical and Business Challenges in CMP R&D. Robert L. Rhoades, Ph.D. CAMP Conference (Lake Placid, NY) August 10-12, 2009

Transcription

1 Balancing Technical and Business Challenges in CMP R&D Robert L. Rhoades, Ph.D. CAMP Conference (Lake Placid, NY) August 10-12, 2009

2 Outline Background and Business Climate for CMP STORM Development CMP Applications and Examples Conclusions 2

3 Balancing Act COST Technology 3

4 Interconnects at Intel Interconnect Technology CMP Evolution 1000 nm Two Our Al Expertise, Metal layers, BPSG 350 nm Four Al metal layers, W polish, PSG 500 nm ILD planarization, W plugs w etch back 180 nm STI, 6 Al Metal layers 250 nm STI, Five Al metal layers, SiOF Process, Application, Equipment, & Slurry Evolve, but not as much on Pads Source: Courtesy of Ken Cadien Former Intel fellow 130 nm 3 6 Cu Layers, PMD, W, STI 65 nm 4 11 Cu Layers PMD, W, STI, OSG 90 nm 3 9 Cu Layers, PMD, W, STI OrganoSilicate Glass (OSG) CMP Applications Oxide Polish Pre-Metal Dielectric Interlevel Dielectric STI Polish Poly Polish Tungsten Polish Copper Polish Barrier Polish High k Gate 4

5 Driving Forces Today Since 2005, consumer products have become primary industry driver. Source: 2007 Industry Strategy Symposium Hans Stork, CTO, Texas Instruments Short product life cycles. Consumers demand More for Less. Consumers demand More in Less Space. Source: 2007 Industry Strategy Symposium Steve Newberry, CEO, Lam Research Corporation Contributing factors for Moore s Law device shrinks, multi-level stacks & larger wafers. Result = Fierce Competition + Control Unit Costs + Develop Technology Fast + Ramp Volume Quickly 5

6 Competitive Advantage Revenue Loss from Being Late to Market Acceleration with CMP Outsourcing: Scenario 1: First time CMP implementation Customer Internal Technology Integration Project: Equipment Purchase & Delivery Design, Integrate, Optimize & Quality CMP Implementation with Entrepix: Optimize & Qualify Ramp Customer Generating Revenue Ramp Strategic Factors in the IC Industry, FSA Forum, June 05 Dr. Handel Jones, Chairman & CEO IBS, Inc. Project Phases Scenario 2: CMP capacity expansion Customer Internal Capacity Expansion Project: Equipment Purchase & Delivery Qualify Ramp Customer Gen. Rev. CMP Capacity Expansion with Entrepix: Qualify Ramp Customer Generating Revenue Scenario 3: CMP burst or flex capacity absorption Customer Internal Capacity Expansion Project: Equipment Purchase & Delivery Qualify Ramp Customer Gen. Rev. CMP Capacity Expansion by IDM already qualified at Entrepix: Ramp Customer Generating Revenue Scenario 4: CMP technology improvement or cost reduction Customer Internal Capacity Expansion Project: Develop, Optimize & Qualify Ramp Customer Generating Revenue CMP Capacity Expansion with Entrepix: Qualify Ramp Customer Generating Revenue TIME 6

7 Business Realities Time IS Money Labor cost + cycles of learning + opportunity cost Competition in most markets is fierce Quality & reliability can not be compromised Each process module must be efficient 7

8 Business Response Minimize Manufacturing Costs Benchmarking Yield Enhancement Optimize Unit Processes Focus on Efficiencies Preserve Capital Extend Equipment Life Keep Depreciated Fabs R&D Consortia Install Less Overcapacity Delay Capital Expenditures Accelerate Development While Reducing Costs Reduce Cycles of Learning Extend Proven Technologies Lower % of Engineering Wafer Starts Leverage Outside Expertise 8

9 Applications for CMP Continue to Expand Numerous complex puzzles Qty Qty Qty 5 CMOS CMOS CMOS New Apps Substrate/Epi Glass (oxide) Glass (oxide) Glass (oxide) Doped Oxides GaAs Tungsten Tungsten Tungsten Nitrides GaN Copper Copper NiFe & NiFeCo InP Shallow Trench Shallow Trench Noble Metals CdTe & HgCdTe Polysilicon Polysilicon Al & Stainless Ge and SiGe Low k Polymers SiC Cap Ultra Low k Ultra Thin Wafers Diamond & DLC Metal Gates Direct Wafer Bond Si & Reclaim Gate Insulators Through Si Vias SOI High k Dielectrics 3-D Packaging Quartz Ir & Pt Electrodes MEMS Titanium Magnetics Nanodevices Integrated Optics Each application of CMP requires an optimized process that meets both performance and cost targets 9

10 Comprehensive CMP Solution #1 Accelerate Time to Revenue #2 Reduce Cost and Risk 10

11 CMP Metrics Five key metrics for a CMP process Removal Rate and Uniformity Defectivity Planarization (step height, dishing/erosion, surface roughness, etc.) Process Stability (consistent performance from wafer-to-wafer) Cost per Wafer 11

12 CMP Development CMP Development Sequence Generate Test Wafers Consumables Screening Process DOE's Optimize Uniformity Optimize Planarity Optimize Defectivity Repeatability (multiple runs) Stability (marathon) Release for Device Qualification Zoom in on CMP process development Screening Tests Assumes fundamentals of pad/slurry research are already done by suppliers Test wafer availability and quality often impact timeline, validity of results, etc. Optimization Initial process DOE s generally focus on removal rate and gross surface quality Optimization stages can be interchanged or executed in parallel Repeatability Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application Marathon Failure at any stage usually means backing up at least one stage to try again 12

13 STORM STORM Screening Tests Optimization Repeatability A proven approach to successfully developing new CMP processes Marathon 13

14 Intro to CMOS Example Project launched to develop a planarized integration for an existing facility running mostly 0.5um and larger devices which did not require CMP. Integration included 2 levels of oxide CMP (PMD and ILD) and 2 levels of tungsten CMP (contact and via1). Initial estimate was roughly 24 months to purchase, install, and qualify CMP equipment plus develop the integration and be ready for production ramp. By leveraging an outsource CMP provider, integration work was started almost immediately and executed in parallel with the equipment lead time. 14

15 Timeline Comparison Key aspects of predicted time savings: Development could begin as soon as test wafers were ready. Equipment purchase, lead time, and installation in parallel. Faster cycles of learning, fewer wafers, lower cost compared to internal. Project Phases Initial Project Timeline for Tool Purchase and Internal Development Production Ramp Qualification Development Install Equip. Purchase Timeframe Acceleration = 12+ months Adjusted Project Timeline with CMP Outsource through Entrepix: Production Ramp Volume Production Revenue Enabled Qualification Development Install Equip. Purchase 3 mos 6 mos 9 mos 12 mos 15 mos 18 mos 21 mos 24 mos 27 mos 30 mos Time 15

16 Timeline Detail Detailed Timeline for CMP Process Module Development Patt. Wafers Blanket Wfrs CMP Lab Days Week #1 Week #2 Week #3 Week #4 Week #5 Week #6 Week #7 Week #8 Week #9 Week #10 Week #11 Week #12 Week #13 Week #14 Task or Milestone Details Phase 1: PMD Planarization Duration ~6-8 wks X Generate test wafers BPSG X CMP process - Initial characterization X Polar evaluation of results X PMD 2nd round optimization X Week #15 Week #16 Week #17 Week #18 Week #19 Week #20 Week #21 Week #22 Week #23 Week #24 Week #25 Week #26 Week #27 Week #28 Week #29 Week #30 Week #31 Week #32 Week #33 Week #34 Week #35 Week #36 Week #37 Week #38 Week #39 Week #40 Week #41 Week #42 Phase 2: Tungsten Contacts Duration ~8 wks X Mask layout and photo optimization X Generate test wafers 3rd party tungsten CVD X CMP process - Initial characterization Incl. SEM X-sections X Polar evaluation of results X Contact 2nd round optimization X Phase 3: ILD1 Planarization Duration ~6 wks X Generate test wafers X CMP process - Initial characterization X Polar evaluation of results X ILD 2nd round optimization X Phase 4: Tungsten Vias Duration ~6 wks X Mask layout and photo optimization X Generate test wafers 3rd party tungsten CVD X CMP process - Initial characterization X Polar evaluation of results X Via 2nd round optimization X Prototype Run (Begin Qual Lots) Duration 4-6 wks X Mask layout and photo optimization X Verification of entire process flow X Evaluation of prototype devices In-line and EOL (ongoing) Polish processes developed: 4 (PMD, W Contact, ILD, W Via1) Total patterned wafers: < 125 Total blanket test wafers: < 200 Total CMP lab shifts: < 12 16

17 Issues Resolved As might be expected, a few issues were encountered during the project. Examples are given below and further detail is provided in a few cases. Issue Composition and thickness of ILD dielectric layer Alignment marks (inconsistent contrast on wafers with CMP) Pattern density effects Ti/TiN liner and CVD W deposition thicknesses Poor contact fill (seen on first contact lot) High NMOS leakage and poor p- field inversion How Resolved Technical inputs from Entrepix with confirmation on 1 st engineering lot Technical dialogue between Entrepix and customer engineering team Verbal description of effects confirmed with data from test structures adjustments made in design rules Starting point suggestions followed by optimization on 1 st and 2 nd engineering lots Suggestions from Entrepix and Novellus helped solve issue in one cycle of learning (Traced to insufficient strip after contact etch) Changed PMD dielectric composition from TEOS to PSG or BPSG 17

18 Issue #1 High Rc Hollow contact Improved contact Hollow contacts with high resistance on first lot. Initial brainstorming between customer and outsource provider led to short list of likely causes. 4485A W-PLUG 3.JPG 4485A NOTCH A1.JPG Resolved with one round of optimization. Resolution involved optimizing post etch strip and was confirmed on next product lot. 18

19 Issue #2 - Leakage The first integration lot showed unexpectedly high NMOS leakage and p-field inversion issues. Technical brainstorming identified trapped charge in TEOS layer as a possible cause of the observed issue. NMOS leakage by PMD oxide Result BPSG PSG TEOS PMD glass composition P-field inversion by PMD oxide TEOS BPSG Normal Quantile BPSG 40 Split lot data confirms that changing to either BPSG or PSG for pre-metal dielectric resolves both issues. Result BPSG PSG TEOS TEOS PMD glass composition Normal Quantile 19

20 CMOS Summary By leveraging the capabilities of an outsource CMP provider, the project timeline for developing a 0.35 um integration in a fab was accelerated by roughly one year. Acceleration was driven by two primary factors. First, the team did not have to wait on internal CMP equipment to be purchased and installed, thus avoiding 6-9 months of delay. Second, several key cycles of learning were assisted by insights and guidance from the external technical staff. Substantial benefits and time savings realized through effective utilization of CMP outsourcing. 20

21 MEMS over CMOS Key Process Metrics & Constraints Metric Incoming Value Post-CMP Target Actual Oxide film thickness 6.5 um 3.0 um 3.02 um Step Height 2.8 um < 0.4 um 0.2 um Removal Rate (um/min) n/a Critical Concerns: Thick oxide layer over CMOS Final topography must be < 0.4um Smooth No sharp corners anywhere Batch to batch consistency Removal Rate (Ang/min) Run # Photos downloaded from web sites, including Sandia National Lab 21

22 Direct Wafer Bonding Example #1: TEOS on X Material Stack Incoming Ra (A) Post-CMP Ra (A) Oxide surfaces tend to bond well when polished to sufficiently low Ra TEOS on Silicon 7 3 Incoming roughness driven by surface prep of underlying material Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness TEOS on SiC TEOS on Polysilicon TEOS on AlN TEOS on Metal Example #2: Inlaid Cu in TEOS Incoming topography >2.5 ka Flat across Goal of <200 A total topography Feature POST-CMP TOPOGRAPHY ACHIEVED Angstroms 22

23 3D Flash Example Scalability of the floating gate approach for NAND Flash appears to be coming to an end Floating gate interference, inability to scale tunnel oxide, and interpoly dielectric scaling fails Issues likely insurmountable in range of nm Some are proposing Charge Trap Flash (CTF) TANOS Bit-Cost Scalable (BiCS) Flash 23

24 Challenges with CTF Inversion Layer V read-pass V read V read-pass ONO To Bitline N+ N+ N+ N+ V read-pass > Vt prog + margin V prog-pass > Vt prog + margin Pass disturbs on selected string Apply to both lateral and vertical NAND CTF 24

25 Wish List for 3D WISH LIST FOR 3D MONOLITHIC FLASH Laterally scalable Easily stackable Reasonable program/erase voltages High program bandwidth Good endurance Good retention MLC capability All at low cost 25

26 Schiltron Design Inversion Layer V read 2 nd Gate ONO To Bitline N+ N+ N+ N+ 1 st Gate V read-pass Off V read-pass Double-gate approach Close electrostatic interaction for short channel control and lateral scalability Electrical shielding of memory charge from pass voltages 26

27 World s Smallest DG-TFT 48nm gatelength CMP2 350 A channel thickness CMP1 27

28 String Structure CMP1 CMP2 XTEM perpendicular to wordline gate direction 28

29 Conclusions Efficient development of new products is required for any device manufacturer to remain competitive CMP process development can be done efficiently as a sequence of stages (STORM) Screening Tests Optimization Repeatability Marathon Creative approaches can enable all of the following: Accelerate timelines Preserve capital Reduce cost and risk 29

30 Contact Info Anyone desiring further information please contact: Rob Rhoades Chief Technology Officer Tel: Fax: