3D Stacked Integrated Circuit (3DS-IC) Standardization. Yann Guillou - SEMI

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1 3D Stacked Integrated Circuit (3DS-IC) Standardization Yann Guillou - SEMI SEMICON Europa 2012

2 Outline SEMI Standard program 3DS-IC Standardization Committee Charter Organization Task force overview On-going activities Conclusions 2

3 About SEMI Standards Established in 1973 Experts from the microelectronic, display, PV, and related industries Exchange ideas and develop globally-accepted technical standards We are international United States Japan Europe Taiwan Korea China

4 The SEMI Standards Program Today All aspects of an automated fab are addressed Over 4,300 volunteer experts (more than 1600 companies represented) 23 global technical committees 200 task forces Currently over 800 SEMI Standards and Safety Guidelines available

5 SEMI Standards Program Consensus-based Standards Development SEMI Standards are created through developing consensus in the industry. Worldwide distribution of document drafts and ballots ensures global consensus. SEMI Standards activities are open to all interested parties, free of charge

6 Benefits of SEMI Standards Benefits for your company Improve communication within and across industries Increase manufacturing efficiency, reduce costs Accelerate product development Enable faster commercialization and interoperability Simplify installation and testing Increase market access and acceptance Benefits for participating Influence the final standard Get a head start in complying with the standard Network and build relationships Enhance industry visibility

7 Outline About SEMI SEMI Standard program 3DS-IC Standardization Committee Charter Organization Task force overview On-going activities Conclusions 7

8 1 st SEMI 3DS-IC Standard Published! SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).

9 3DS-IC Standards Committee Charter To explore, evaluate, discuss, and create consensusbased specifications, guidelines, and practices that, through voluntary compliance, will; promote mutual understanding and improved communication between users and suppliers of 3DS-IC materials, carriers, automation systems and devices, and enhance the manufacturing efficiency and capability and shorten time-to-market so as to reduce manufacturing cost in the 3DS-IC industry. Committee formed in Fall 2010 Inaugural meeting held in January 12, 2011

10 Participating Companies * Over 140 registered TC members 3MTS eda2asic Maxim Semilab Altera Elpida Micron Shin-Etsu Polymer AMD Entegris Miraial SigmaTech Amkor Epistar Neocera Sonoscan Applied Materials esilicon Nikon Precision Strasbaugh ASE EVG NIST SUSS Brewer Science Fraunhofer Novellus Tamar Technology BroadPak IBM Olympus-ITA Texas Instruments Brooks Automation Intel Qualcomm Tezzaron CEA/LETI ITRI Quartet Mechanics Tokyo Electron CNSE KLA-Tencor Rudolph Technologies TSMC Corning KYEC Salland Xilinx Dynaloy Lintec SEMATECH Zygo * partial list

11 Organization chart North America 3DS-IC Committee Chairs: Urmi Ray (Qualcomm) Sesh Ramaswami (Applied Materials) Chris Moore (Semilab) Rich Allen (SEMATECH) Taiwan 3DS-IC Committee Chairs: Tzu-Kun Ku (ITRI) Wendy Chen (King Yuan Electronics) Yi-Shao Lai (ASE) Leader: Wafer Bonded Stacks Task Force Rich Allen (SEMATECH) Inspection & Metrology Task Force Leader: Thin Wafer Handling Task Force Urmi Ray (Qualcomm) Raghunandan Chaware (Xilinx) Richard Allen (SEMATECH) Leader: Middle End Process Task Force Arthur Chen (NTUST) Erh Hao Chen (ITRI) Jerry Yang (SEMATECH) Leader: Yi-Shao Lai (ASE) David Read (NIST) Chris Moore (Semilab) Victor Vartanian (SEMATECH) Leader: Testing Task Force Sam Ko (KYEC) Roger Hwang (ASE) Tzong-Tsong Miau (ITRI) 11

12 Task Force Overview Wafer Bonded Stacks TF Approved late January 2011 Charter: The BWS Task Force will actively create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process. Scope: Identify new wafer parameters that reflect adequate ranges for bonded wafer stacks Modify/create document to reflect adequate ranges for bonded wafer stacks Identify other SEMI standards that are adversely affected by BWS parameters Update referenced standards: create/modify standards to reflect BWS parameters

13 Task Force Overview Inspection & Metrology TF Approved late January 2011 Charter: Develop standards for metrology and inspection methods to be used in measuring the properties of TSV s, bonded wafer stacks, and dies used in the 3DS-IC manufacturing process. Scope: Examples of needed standards include (but are not limited to): TSV physical properties (i.e., depth, top, bottom CD, side wall, etc.) Bonded wafer stack properties (i.e., overlay, bond inspection) Defect metrology Dies

14 Task Force Overview Thin Wafer Handling TF Approved late January 2011 Charter: Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DS-IC highvolume manufacturing (HVM) Define thin wafer handling requirements including physical interfaces used in 3DS-IC manufacturing Define shipping requirements, including packaging, reliability, and other relevant criteria. This will also include MPGA ship/handle requirements

15 Task Force Overview Test Task Force Formed on October 26, 2011 Charter: The Testing Task Force will develop standards, guidelines, and/or specifications for electrical testing related activities used in 3DS-IC manufacturing for the ultimate goal of yield enhancement. Scope: Activities related to electrical testing of prebond and bonded wafers/devices include (but not limited to): Design for Test (DfT) such as test structures and placement; Test methodologies such as contact method and test procedures; Test fixtures such as probe card and probe interfaces, and Data mining test results.

16 Task Force Overview Middle-End Process Task Force Formed on February 9, 2012 Charter: Develop the standards and define the specifications for middle-end process (MEOL) related manufacturing flow. Current Phase of Standard and Specification development focused on the middleend process on wafers with or without TSVs, including post final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line (RDL) formation and carrier de-bond.

17 On-going documents Bonded Wafer Stacks TF Doc Doc Doc new! Thin Wafer Handling TF Doc New Standard: Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack New Standard: Specification for Identification and Marking for Bonded Wafer Stacks New Standard: Specification for Glass Wafers for Use in Bonded Wafer Stacks New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers

18 On-going documents Inspection & Metrology TF Doc Doc New Standard: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures New Standard: Guide for Measuring Voids in Bonded Wafer Stacks Doc Doc Doc new! New Standard: Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks New Standard: Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures

19 On-going documents Middle-End Process TF Doc new! Doc new! New Standard: Guide for Alignment Mark for 3DS-IC Process New Standard: Guide for CMP and Micro-bump Processes for Frontside TSV Integration Testing TF Doc new! New Standard: Guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products

20 Conclusions Get involved! Get your company support Register today: For more information, please visit the SEMI 3DS-IC Site: Next meetings: October 30, 2012 at SEMI HQ (San Jose, CA) November 26, 2012 at ITRI (Hsinchu, Taiwan) For more information on 3DS-IC activities, please contact: Yann Guillou, SEMI Europe, Paul Trio, SEMI North America, Catherine Chang, SEMI Taiwan,