Modeling for DFM / DFY

Transcription

1 Modeling for DFM / DFY A Foundry Perspective Walter Ng Senior Director, Platform Alliances 5/24/ Chartered Semiconductor Manufacturing Ltd. All rights reserved. No part or parts hereof may be reproduced, modified, adapted, distributed, republished, displayed, broadcast, transmitted in any manner or means or stored in an information retrieval system without the prior written permission of Chartered Semiconductor Manufacturing Ltd.

2 The Great Divide Before n n1 Masses Δt1 Early Adopters n1 > n2 Less Early Adopters Δt2 >> Δt1 Greater Time Separation Now n n2 Masses Δt2 t Early Adopters t 2

3 The Challenge - Today s Product Cycles Steeper product ramps, shorter dwell in market Product Life Most Product Roadmaps - Obsolete own existing products with improved derivative or new product Volume Missing a Product ramp may have significant impact on a company s market share Typical of consumer applications: Graphics, Gaming, Communications, Networking, etc. < 100 days Time 3

4 Today s State-of-the-Art Foundries Fab7 Automation Architecture Scheduling Adexa Plant Special Processing (SPSR) Control Systems Preventative Maintenance System Reticle Management System Mfg Reporting System Data Analysis System Yield Reporting System Information Handling IYS Yield Automation Real Time Dispatcher Material Control System (MCS) Automation/ Workflow Manager YMS Recipe Management System ACE XP Alarm & OCAP Management Reporting In-line Planner & APC (DataMart) Defect (JMP) Material Wafer System ET SI View SPC Manufacturing Execution System Mgmt (MES) Control Integrated Sleuth Yield Systems (IYS) dataconductor WIP Eqpt Mgt FDC Run-to- System System System Equipment Carrier Mgt Statistical Fault & Real-time Run-to-Run Flow Mgt (include User Mgt Detection & Yield Mgt Defect Mgt Mgt Run (FOUP) Process Lot Control databases Wafer Sleuth NPW) Classification System System Control (FDC) & (APC) System SPC Control History (KLA-ACE) (KLArity) Business Rules (SPC) ediagnostics System Reporting SPACE Brookside Catalyst KLArity Xsite CIM, SiView MES Database Real-time databases Off-line databasessystem Datamining ACE XP Equipment Integration SPACE Manager (EIM) & Data Collection Material Handling Automation icare Stocker Controller Stocker Inter-bay AMHS Controller Sort & Final Test Data Inter-bay AMHS Intra-bay AMHS Controller Intra-bay AMHS Process Reliability Monitor Data Reticle Stocker (Pod & Bare) Integrated Stocker-Sorter SMS Limited Yield Modeling Load Port Load Port Process Eqpt Load Port OHT Load Port In-line Metrology & inline E-test Eqpt Off-line databases Load Port OHT Load Port Setup Metrology Eqpt Load Port Load Port Support Eqpt Load Port Web Portal Load Port 4

5 Process Characterization PDF CV Test Chip Suite BEOL BEOL CV CV (CA,M1,Mx,Mx) (CA,M1,Mx,Mx) CA induced M1 short CA induced M1 FEOL short FEOL 2 2 CV CV (AA (AA to to M1, M1, M2, M2, Mx) Mx) Metal CMP Metal CMP MC CA Marginality (Misalign, size, etc.) Printability evaluation MC (M1 CA -> Marginality M3) (Misalign, size, etc.) Printability evaluation Salicide (M1 -> M3) FEOL FEOL 1 1 CV CV (AA (AA to to M1) M1) Topography effects Salicide Poly, AA defectivity Topography effects Printability evaluation (up to Poly, M1) AA defectivity Consumables improvement Printability evaluation (up to M1) CA defectivity (short/open) Poly Poly CV CV (AA (AA and and PC) PC) Consumables improvement Other Systematics (NP Transitions, CA defectivity etc) (short/open) BEOL defectivity Other Systematics (NP Transitions, etc) PC defectivity (incl. triple gate oxide) MC defectivity PC defectivity (incl. triple gate oxide) BEOL defectivity Reduced Defectivity Observability MC defectivity Pull and test after M1 Reduced Defectivity Observability Pull and test after M1 STI topography (and M2) Contact Stacks STI topography (and M2) Contact Stacks STI seam Very Limited Marginaility STI seam pdfastest pdfastest Very Limited Marginaility PC ECD variations Pull and test after M1 PC ECD variations Parametric Parametric (Agilent) (Agilent) Pull Test Test and test after M1 Salicide resistance Salicide resistance pdfastest Printability evaluation (PC) Printability evaluation (PC) Pull Pull and and test test after after M1, M1, Mx, Mx, Mx Mx pdfastest pdfastest pdfastest Parametric Parametric (Agilent) (Agilent) Pull Pull Tester Tester and and test test after after salicide salicide pdfastest pdfastest P D YRS Fab and Test datapower WAMA CV Infrastructu re pdfastest CV test chips pdcv Process Learning Process- Design Integration Knowledge Base Product Design Circuit Surfer YRS pdfx D Build yield infrastructure using PDF CV Characterization vehicles advantages: Short cycle time in process feedback Able to identify process issue Enhance process margin P 5

6 Design to Manufacturing to Test COT Model Challenge Design Manufacturing Testing RTL Synthesis Design Planning Block Design DFT ATPG Chip Physical Assembly Extraction Verification Mask OPC ORC Prototype Tape out Testing Yield Analysis Failure Analysis Design for Manufacturing / Design for Yield DFT DFT Design to Manufacturing to Test Hand-off Coordination more critical than ever before More Manufacturing and Testing concerns addressed as part of Design DFY / DFM Manufacturing Models being made available to customers Tools and Technologies being validated and customer enabled Manufacturing tools and control improving significantly DFT Traditional Test Insertion done as part of design As a part of Test and Failure Analysis, DFT needs to be able to support Faster Yield Ramps 6

7 Motivations for DFM Models Chip Designers need to achieve Design Closure Timing, power, signal Integrity and now manufacturability Chip Designers need to be able to predict timing and electrical performance accurately The traditional approach of worst case static-timing analysis is becoming unacceptably conservative Chip Designers have increasing concerns on Types of significant (first order) process variation drivers What are they? How these are measured? How these are modeled? How these process variations are modeled and used or can be used in design automation tools and flows 7

8 Sources of Process Variation (FEOL) CD Variation Exposure System Lens aberration, flare, etc. Within-die exposure dose non-uniformity Mechanical Performance Vibrations in reticle scanning and wafer scanning stages, etc. Focus Variations Illumination Performance Mask Errors Polarization control of the laser Puncture, Burr, Blotch Resist Effects Line Edge Roughness Vth Variation Mainly due to random dopant fluctuations in the channel region. These fluctuations affect the threshold voltage of the individual devices independently. Pelgrom s model can also be used to describe the standard deviation due to random dopant fluctuations. Overlap Capacitance CGSO/CGDO represent the overlap capacitances between the source/drain and the gate Slide courtesy of Samsung 8

9 Source of Process Variation (BEOL) Each Layer and Via variation modeling Thickness variation model (CMP effect) Width variation model (Litho effect) CMP/Litho simulation Lithography effect Slide courtesy of Samsung 9

10 Variation Models radius > die size 4 Die-to-die [4] Effective radius > die size Systematic [1][2] Effective radius < 2-3 mm Random [3] Effective radius < device size 1 2 radius ~ 2-3 mm radius < device size 3 Slide courtesy of Samsung Device model parameters such as Vth, Tox and source/drain sheet resistance are varied to reflect parametric process variation effect on circuits. Less attractive due to growing complexity of the manufacturing process and increased sensitivity of the circuit design to these variations 10

11 Process Variations in Today s Models Device Level Interconnect Level Process Variation Contributors on interconnect Type Modeling At Present Short term Long term At Present Design Implementation Short term Long term Litho Etch CMP Optical defocus Photo resist Wide Edge Effects (biasing, trapezoidal, dishing, erosion) Dielectric deposition and polishing Systematic Systematic Systematic IA Spec at process corners: Per layer di thickness wctyp-bc Per layer cu thickness wctyp-bc Upgrade IA Spec with WEE table: Replace a single value with a lookup table Litho model for silicon image prediction CMP model for thickness prediction and parasitic extraction Closure at wc & bc corners with OCV derating factors Advance extraction Model base extraction Metal deposition and polishing Systematic Wearing of consumable parts Systematic Statistical model? Statistical analysis 11

12 DFM Parasitic Extraction (PEX) Extraction of nanometer effects supported by DFM PEX S1 W S2 Metal Metal Biasing (Resistance vs space & width) (bias vs space & width) Trapezoidal metal (Resistance vs space & width) M1 M1 Metal Metal Dishing/Erosion (thickness vs density) (thickness vs space & width) gate Substrate Contact Capacitance (minimum space between gate and via) 12

13 DFM PEX for 90nm 13

14 DFM Technology Kit Model Support DFM Focus Area Tool Vendor (Primary tool) Rule / Model Based DFM Rule Checking Decks Mentor (CalibreYA) Rule Critical Area Analysis Litho. Simulation CMP Simulation DFM Aware Chip Integration Flow Simultaneous Leakage Reduction and Yield Optimization Statistical STA Ponte (YA) Mentor Mentor (LFD) Clearshape (In-shape) Cadence CP Synopsys Magma Cadence Blaze-MO TBD Model Model Model Model Model Rule / Model Rule / Model Rule / Model Rule / Model Model 14

15 Summary One of the key challenges in supporting leading edge tape outs is requirement for very fast product yield ramp. This requires as much of a first-time right methodology and very fast test, failure analysis and repair capability. Progress is being made in the DFY/DFM area. Manufacturers like the Common Platform have been qualifying and enabling promising tools and technologies in this area by supporting DFM models Supporting models based technologies are not easy because they require running adequate silicon on a relatively stable process Challenges In Model Development Cost Significant Capital Costs in Foundry, Shrinking Wafer Margins Timeline Process stability Lack of Model Standards (i.e. no standard in Litho simulation model) Unwillingness of cross-eda cooperation Logistics of Managing Model Updates Industry requires progress in Model or Model Interface Standards to substantially proliferate Model-based DFM 15

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17 Critical Area Analysis Models Critical Area Visual Hot Spots Typical CAA flow Fail Rates Item Unit Mature Ramp - Early MC on GP Open (ppb) MC on Active Open (ppb) ACT Open (/cm²) ACT Short (/cm²) GP Open (/cm²) GP Short (/cm²) M1 Open (/cm²) M1 Short (/cm²) Critical Area Reporting Layout GDSII (DRC cleaned) Fail rate for CAA (from Si) CAA (Ponte YA) 1) Critical area extraction Slide courtesy of Ponte Solutions 17 2) Visualization 3) Yield scoring 4) Priority list to fix

18 CMP Modeling Test Wafer GDSII Fabrication Measurement Lab CMP Analysis Measurement Database CMP model Cu thickness, Oxide thickness, Surface height Slide courtesy of Cadence 18

19 Basic Components of Statistical STA Library Development Spice Netlist Design Flow Logic Synthesis Cell Layouts Silicon Variation Models Statistical Cell Characterization CMP Simulation Litho Simulation Length/Width Tox/Vt variation SSTA Cell Library Each Layer s width & thickness Variation Statistical RC Extraction Statistical Static Timing Analysis Netlist Physical Design RC Extraction Static Timing Verification Physical Verification Statistical Optimization 19

20 Litho Simulation Model Development 20