Silicide-Based Release of High Aspect-Ratio Microstructures

Transcription

1 -Based Release of High Aspect-Ratio Microstructures Li-Wen Hung and Clark T.-C. Nguyen Dept. of EECS, University of California at Berkeley Berkeley, CA, USA ABSTRACT A new method for releasing high aspect-ratio microstructures has been demonstrated that utilizes silicidation to form gaps between movable microstructures and their substrates in substantially faster times than conventional sacrificial layer-based release methods and with much less concern for stiction or attack of unintended layers. The key enabling element is the use of a self-sufficient chemical reaction (such as silicidation) to provide volume shrinkage that then induces a gap between surfaces involved in the reaction. Using this -based approach, 260:1 aspect-ratio gaps have been released in less than 2 minutes, which is much shorter than the 40 minutes or more that would otherwise be required by wet-etching. This silicidation-based approach to releasing microstructures greatly increases the achievable lateral dimensions of etch hole-free suspended microstructures and stands to substantially lower the time and cost required to produce such structures. 1. INTRODUCTION Release processes, whereby sacrificial material between two structural materials is removed to free them from one another, often comprise the most limiting and costly steps in MEMS fabrication. Such processes generally employ liquids or gases to etch and are fraught with numerous perils, including stiction [1]; the need for long release times governed by mass transport rates that lengthen as gap aspect-ratio increases [2]; the (ensuing) attack of unintended layers due to finite etchant selectivity; and the formation of etch by-products (e.g., bubbles, gunk) that remain in the gaps. These yield-limiting phenomena often force alterations in MEMS designs (e.g., release holes) that compromise the performance of applications employing high-aspect ratio gaps. Indeed, the set of affected applications is quite large, from inertial sensors that must incorporate mass-reducing etch holes into their proof masses to speed up the release process [3]; to sealed encapsulation chambers, many of which are achieved via cap-to-wafer bonding methods rather than more area-efficient film deposition strategies [4], since the latter often ending up requiring lengthy etches to release structures within the encapsulation; to GHz high- Q mechanical resonators [5], for which the size of the electrode-to-structure gap spacing needed to achieve low impedance and good power handling is limited nearly entirely by the release etch process. This work erases such limits by introducing a new method for forming high aspect ratio gaps between movable (or immovable) structures that avoids etching and its associated drawbacks, entirely. Instead, the method here employs a self-sufficient chemical reaction to provide volume shrinkage that then induces a gap between surfaces involved in the reaction. Using this -based approach, μm 2 membranes with membrane-to-substrate gaps of only 385nm a 260:1 lateral dimension-to-vertical gap aspect ratio have been Table 1 Properties of common s licidation Volume t Temperature t sili Shrinkage δ Ni 2 ~250C % 0.44 Ni ~400 C % 0.62 Ti 2 ~850 C % 0.8 Pt ~500 C % 0.35 Co 2 ~750 C % ~750 C % 0.97 t si = nm of consumed per nm of metal (t m =1) t sili = nm of formed per nm of metal (t m =1) δ = nm of step height change per nm of metal (t m =1) released in only 2 minutes, which is much shorter than the 40 minutes or more that would be required to wetetch a 385nm sacrificial oxide under a membrane of similar size. In addition, 32.5 nm gaps have been formed between a Ge film and a silicon substrate, verifying the efficacy of this method for attaining sub-50nm gaps, such as needed for capacitive RF micromechanical resonators. 2. SILICIDE-INDUCED GAPS The key recognition behind the present work is that etching is not needed to form a gap. Rather, a gap can also form if a method is available for shrinking the volume of a submerged layer. If this method is a chemical reaction, as in this work, then it is preferable that it be self-sufficient such that all the reactants and the products of the reaction remain on the wafer. This self-sufficient property eliminates the need for diffusion paths so eliminates the root of the problem that plagues etch-based release processes. reover, this reaction should be fast and dry to enhance throughput and to avoid problems with stiction and bubble formation. One reaction that satisfies the above criteria is silicidation [6], whereby silicon, the most commonly used material in CMOS and MEMS, reacts under elevated temperatures with a variety of metals to form s. Table 1 [6] lists properties of common s pertinent to volume shrinkage-based gap formation. Here, silicidation temperatures range from 250 C to 850 C depending on the types of metals and on the phases of s. The data also includes information gauging the amount of volume shrinkage afforded by a given silicidation reaction, assuming a starting metal sitting flush atop a silicon substrate, as illustrated in the schematic above Table 1. Fig. 1 illustrates one method by which silicidation can be used to form a submerged gap. Here, 10nm of molybdenum () is sandwiched between silicon () below and a capping layer of oxide above. Upon heating via rapid thermal annealing in a low oxygen environment, the and react to form 2, whereby 10x2.56 =25.6nm of silicon is consumed to form 10x2.59 =25.9nm of 2. This means the step height changes

2 oxide or nitride metal Anneal PECVD = nm 500nm licon Substrate Fig. 1: Process flow and SEM cross-section of a 192nm air gap formed between oxide and. Here, 200nm- reacts with silicon but not oxide at the anneal temperature. a- or poly- metal Anneal 300 nm = nm PECVD Amorphous licon licon Substrate Fig. 2: Process flow and SEM cross-section of a 128nm air gap formed between amorphous silicon and. Here, 150nm forms s unevenly on both sides due to differences in single-crystal and amorphous silicidation behavior. from the 10nm original metal thickness to now only =0.3nm, leaving a =9.7nm gap between the top of the and the bottom of the oxide cap. The advantages of this -based approach over etch-based release processes are numerous and include: 1) Greatly reduces the time needed for release, since the time required is governed by a single interface reaction time rather than by lateral transport rates; 2) Avoids damage to structures not involved in the release, which is an important limiting side-effect of sacrificial layer-based approaches, where the etchant used often has a finite selectivity to other surrounding layers, so attacks and removes them; 3) Avoids surface tension-based sticking or problems with bubble formation during release that commonly plague wet release approaches; 4) Allows the formation of gaps in sealed chambers, i.e., no need for access routes. 3. EXPERIMENTS Fig. 1 and Fig. 2 summarize processes used for basic demonstration of -induced gaps. In Fig. 1, 200nm of sputtered molybdenum is patterned by wet etching into strips, followed by 600nm of PECVD capping oxide deposited at 300 C. After just one minute of annealing at 750 C, a gap forms when volume shrinkage during silicidation pulls the d silicon surface away from the capping oxide. The rounding at the gap edges results from rounding of the original metal corners during isotropic wet etching. The gaps essentially take on the shape of the metal layer, and the shape of is a mirror image of the metal relative to the silicon surface. The process of Fig. 2 differs from that of Fig. 1 only in the use of a semiconductor top layer, where PECVD amorphous silicon is used instead of oxide. Otherwise, the silicidation procedure is essentially the same, except that now s form on both the top and bottom surfaces of the gap. This process has the advantage of allowing a conductive semiconductor structural material, which is needed for electrostatic transduction. For applications where silicidation at the bottom of the conductive 200 nm Fig. 3: SEM cross-section showing a roughened surface caused by thin oxide at the silicon-metal interface. 10um 100um = nm 2um microstructure is not desired, e.g., due to stress imbalance issues, it can be prevented by depositing a thin layer of dielectric between the microstructure and the metal, similar to the thin side-wall spacers used in CMOS to prevent silicidation on the polysilicon gate [7]. For applications where sub-10nm dielectric layers can compromise device performance, such as capacitively transduced high-q resonators and switches, conductive materials that do not react with metal at the silicidation temperatures can be used as structural layers. Some good candidates include silicon carbide, polycrystalline diamond, or metals with higher silicidation temperatures. For repeatable and high quality formation, the interface between the metal and semiconductor must be clean and native-oxide-free. To insure this, a buffered hydrofluoric acid (BHF) dip and slight in-situ sputter etch precede the actual metal sputtering step in the above processes. The importance of doing this is immediately apparent when oxide is present at the interface. In particular, when samples before metal deposition are shortly dipped in piranha instead of BHF with no sputter etch, and the same thermal annealing conditions applied, silicidation either does not happen or the surface becomes very rough, as shown in Fig. 3. To gauge the permissible temperature ceiling during process steps before and after the silicidation anneal, over- samples were heated in a conventional oven at 350 C for 6 hours before and after the one minute 750 C silicidation anneal, with no change in step height versus a -over- sample without extra thermal treatments. This confirms that microstructures can be released at the very end of a process as long as processing temperatures after metal deposition do not exceed the silicidation temperature. reover, once the is formed, thermal processes generally do not change the size of the gap. re General Geometries Mere patterning of the capping layer before the silicidation anneal yields suspended movable structures with (c) (d) 1um Fig. 4: SEM cross-sections of a 100μm-wide 410nm-thick oxide diaphragm suspended 385nm above the substrate and a zoom-in. The original thickness was 400nm. (c) and (d): Smaller diaphragms released in the same annealing step.

3 Capping Channel Width = 15um Channel Height = 0.8um Ge 10um Fig. 5: Cross-sectional SEM of an array of oxide-capped micro-channels on a silicon substrate fabricated via induced release. Release Cantilever = 32.5 nm 200 nm Fig. 8: SEM cross-section of a 32.5nm gap formed between a bottom 2 and a top Ge capping layer. Even smaller gaps should be achievable via a thinner metal layer. 1um 1.2um amorphous -Sub Fig. 6: SEM of a 1.2μm-thick oxide cantilever separated from the substrate by a -induced gap. Fig. 7: SEM of a released folded-beam comb-driven structure with springs bent by a probe tip. Fig. 9: A -induced gap formed over a 1.2um PECVD amorphous silicon film deposited at 300 C. more general geometries. Figs. 4-7 present images of various patterned oxide structures released via the described approach, including a μm 2 membrane with a 260:1 lateral dimension-to-vertical gap aspect ratio and membranes with smaller sizes formed by the same one minute thermal anneal step (Fig. 4); an array of 15µm-wide, 0.8μm-high, 9mm-long microchannels that attest to the repeatability of this approach (Fig. 5); a 20μm-long, 2μm-wide oxide cantilever (Fig. 6), and a folded-beam comb-driven resonator with springs bent by a probe, confirming that they are released (Fig. 7). Successful release of such compliant microstructures is possible because silicidation is a dry process, so does not suffer from stiction. In all cases, the release anneal takes no more than two minutes, and no etchant is consumed, making this approach much faster and cheaper than etch-based release methods. Tiny s. Among the most powerful capabilities provided by silicidation is its ability to achieve tiny sub-50nm gaps, which are essential to vibrating RF micromechanical resonators using capacitive transduction. Fig. 8 shows a 32.5nm gap underneath a Ge capping layer, achieved via a silicidation reaction between metal and the underlying silicon substrate, with comparatively little reaction with the capping Ge layer. The thirty seconds required for silicidation contrasts sharply with the 40+ minutes of wet-etching often required for small-gapped RF micromechanical resonators [5]. Indeed, release times required by etch-based release processes increase with gap aspect-ratio, while those needed for based release remain virtually the same. Clearly, the described -based release process scales much better than etch-based counterparts. The smallest achievable gap is ultimately limited by the surface roughness of the which is generally on the order of 10nm or less for nickel [8], titanium [9], and cobalt [10]. spacings this small should be very helpful towards capacitively transduced resonators with the sub-50ω impedances desired by conventional wireless circuits. Although silicidation occurred with the silicon substrate and not the Ge in this process, it should be noted that -induced release is not limited to silicidation with single crystal silicon, but also works with amorphous and polycrystalline systems, and with semiconductor materials other than silicon, e.g., Ge. For example, Fig. 9 presents a gap formed between a top oxide capping layer and a 1.2μm PECVD amorphous-silicon layer deposited at 300 C. This confirms that the described -based release process can be applied to MEMS/NEMS built atop CMOS or on substrates other than silicon, such as glass, as long as a thin layer of semiconductor is available. It also suggests methods by which -based release can form lateral gaps, perhaps using PECVD and/or atomic layer deposition (ALD) methods to deposit conformal lateral semiconductor and metal films with well-controlled thicknesses at temperatures lower than the silicidation temperature. 4. APPLICATIONS To demonstrate the use of -induced gaps in a practical application, the three-mask process shown in Fig. 10 uses titanium (Ti) as a structural material and as the siliciding metal to fabricate beam resonators. Here, is sputter deposited after a short in-situ sputter etch to remove native oxide, then patterned using a commercial aluminum wet etchant (pre-mixed phosphoric and acetic acid mixture) at 50 C. Next, 300nm of 300 C PECVD oxide isolation liner is deposited and patterned via a BHF dip, followed by sputter deposition of 700nm of Ti structural material at 300 C. The Ti is then dry etched via a Cl 2 /BCl 3 plasma, with the etch stopping on the underlying or oxide layer. The structure is finally released via a one minute rapid thermal anneal step. As shown in Fig. 10, 2 forms the ground plane/drive electrode for this clamped-clamped beam, and the oxide layer prevents the beam from shorting with the. Fig. 11 presents the SEM of a released 320μm-long,

4 (c) Ti (d) Ti 2 Fig. 10: Process flow yielding a titanium clamped-clamped beam released via silicidation: Sputter and pattern molybdenum over silicon substrate; deposit 300nm 300 C PECVD oxide and remove over device areas and bond pads; (c) sputter and pattern 700nm titanium structural material; and (d) release via rapid thermal annealing at 750 C. Fig. 12: Mixing measurement setup and measured resonant peak under vacuum for a Ti clamped-clamped beam released via silicidation, with Q=1,082. Here, P RF =10dBm (network analyzer output), V LO =10V P-P, and V P =20V. Sacrificial Material Etch Holes Permeable Material Sealing Layer 30um Titanium Beam (a-1) Structure Sub. Sacrificial Metal (a-2) Sub. Package or Frame Released Structure Material Probe tip Fig. 11: SEM of a 320μm-long, 3μm-wide, 700nm-thick titanium clamped-clamped beam using the process of Fig. 10. Bending via a probe tip confirming release. 3μm-wide Ti clamped-clamped beam displaced laterally by a probe tip. Fig. 12 further presents the mixingmeasured [5] frequency characteristic (in vacuum) for a 20μm-long, 2μm-wide beam with 150nm electrode-toresonator vertical gap spacing, confirming functionality of the beam and applicability of the -based release process in an actual application. 5. CONCLUSIONS AND FUTURE WORK By utilizing a volume shrinkage-based method for forming gaps between structural layers and thereby avoiding the need for etching, the -based release process demonstrated in this work is cheaper, cleaner, and faster than conventional etch-based methods, as it requires no etching, consumes no chemicals, and has little dependence on mass transport processes. Using this method, structures with aspect-ratios exceeding 260:1 have been released in less than two minutes substantially less than the 40 minutes otherwise required by an etch-based release process. Although this work features s based on, it should be understood that any of the metals in Table 1 could also be used. But the benefits of silicidation methods go far beyond mere release of high-aspect ratio gaps. In particular, the fact that silicidation is a heat-induced and selfsufficient reaction that does not require a diffusion path suggests the possibility for localized and post-package release without any need for release holes in the package structure. To expand upon this, Fig. 13 [11] presents one conventional approach to wafer-level encapsulation where release holes in the encapsulating cap are needed to allow release etchants to access a sacrificial layer that completely encases the structure under the cap. nce the diffusion paths are quite tortuous, the time required for release is generally quite long and etch by-products have difficulty diffusing out. On top of this, the need to seal the etch holes can compromise both the package and device within (if the sealant also deposits on the device). In contrast, silicidation (requiring no diffusion path) (b-1) Sub. (b-2) Sub. Fig. 13: Cross-sectional summaries of a conventional thinfilm package where (a-1) etch holes provide access for sacrificial material removal and (a-2) a deposition step is required to seal; and a -based release packaging method that obviates the need for etch holes and sealing that comprises (b- 1) deposition and patterning of a proper succession of semiconductors and metals and (b-2) a short silicidation anneal. can form gaps submerged beneath the cap layer with no need for etch holes, as shown in Fig. 13. The packaging process would require just minutes of anneal time and would be local to areas with the right metalsemiconductor pairings. Efforts towards post-package and release of capacitive resonators are ongoing. ACKNOWLEDGMENT. This work was supported by DARPA. REFERENCES. [1] R. Maboudian and R. T. Howe, Critical review: Adhesion in surface micromechanical structures, J. Vacuum Sci. Technol., vol. B15, no. 1, pp. 1 20, Jan./Feb [2] C. Torres-Raya, et. al, Fabrication, chemical etching, J. Mater. Res., vol. 23, no. 12, Dec [3] I. Lee, et. al, "Development and analysis of the vertical capacitive accelerometer," Sensors and Actuators A: Physical, vol. 119, pp. 8-18, [4] K. R. Lee, et. al, Fabrication of capacitive absolute pressure sensor using -Au, J. Phys.: Conf., ser , [5] J. Wang, et al., GHz, IEEE Trans. Ultrason., Ferroelect., Freq. Contr., vol. 51, pp , Dec [6] K. Maex and M. Rossum, Properties of Metal s, INSPEC Publication, [7] J. J. SUNG and C.-Y. Lu, Limitation of spacer thickness, IEEE Electron Device Lett., vol. 10, pp , [8] M. Bhaskaran, et. al, "Characterization of nickel thin films by spectroscopy," Micron, vol. 40, pp , [9] C. Lavoie, et al., Surface roughening during titanium formation... Proceedings of MRS, vol. 440, pp , [10] G.-P. Ru, et al., "Surface and interface morphology of Co 2," Materials Characterization, vol. 48, pp , [11] K. S. Lebouitz, et al. "Vacuum encapsulation of resonant devices using permeable polysilicon," MEMS'99, pp

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