Copyright 2009 Year IEEE. Reprinted from IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES. Such permission of the IEEE does not in any way

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1 Copyright 2009 Year IEEE. Reprinted from IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics products or services. Internal of personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to

2 566 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 32, NO. 3, SEPTEMBER 2009 Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages Aibin Yu, Navas Khan, Giridhar Archit, Damaruganath Pinjala, Member, IEEE, Kok Chuan Toh, Vaidyanathan Kripesh, Member, IEEE, Seung Wook Yoon, Member, IEEE, and John H. Lau, Fellow, IEEE Abstract This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation. Index Terms AuSn-solder, electrical, interconnection, system-in-package (SiP), 3-D package, through silicon via (TSV). I. INTRODUCTION T HREE-DIMENSIONAL packages can provide the advantages of shorter signal routing, reduced wiring density at the second level, and smaller size [1]. One of the biggest challenges in 3-D packaging is thermal management [2], especially when the package size becomes smaller and smaller while the power (heat) sources in the package are not decreasing, or even increasing. Therefore, on the one hand, 3-D package is a preferred technology for system in a package and system on a package (SiP/SoP) applications; on the other hand, current 3-D package applications are limited to die and package level stacking for lower power applications, such as memory devices, baseband, and logic devices. As the power density of a singlechip packaging is incessantly increasing and is expect to be higher than 100 W/cm for high-performance systems, such Manuscript received March 10, 2008; revised November 12, First published April 10, 2009; current version published August 26, The work was supported by the Defense Advanced Research Projects Agency (DARPA) under Agreement HR This work was recommended for publication by Associate Editor B. Courtois upon evaluation of the reviewers comments. A. Yu, N. Khan, D. Pinjala, V. Kripesh, S. W. Yoon, and J. H. Lau are with the Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR), Singapore ( yuab@ime.a-star.edu.sg). G. Archit and K. C. Toh are with the School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCAPT Fig. 1. Illustration of 3-D stacking of silicon carriers for high-power chips integration. as defense systems, etc. 1 As a result, when designing stacked 3-D packages, it is important to pay special attention to thermal management. Conventional cooling like air cooling and direct liquid cooling have been developed, but they are not suitable for high-power (higher than 100 W/cm ) heat dissipation from the 3-D packages [3]. Besides the thermal management, process compatibility for wafer-level integration and interconnect reliability, etc., are also key challenges for wafer-level 3-D package technology and worth studying in detail. This paper presents micro fabrication process and wafer-level integration of a silicon carrier that consists of two silicon chips and an optimized liquid cooling channel structure embedded in between the two silicon chips. Silicon is chosen as carrier material because it is a suitable material for integration of both electrical and fluidic structures in the same substrate with micro fabrication process. More importantly, silicon has good thermal conductivity. Therefore, the silicon carrier has the potential to provide excellent thermal solution for high power chips. As shown in Fig. 1, two (or more) carriers can be stacked over each other with silicon interposers in between to make up of a stacked cooling module for integration of high power chips. II. DESIGN OF SILICON CARRIER The silicon carrier developed in this work consists of two silicon chips. Fig. 2 shows a schematic drawing of the silicon carrier. Fig. 2(a) and (b) shows the top view and cross-sectional view of the carrier. TSVs are designed along the periphery of the carrier at a pitch of 0.5 mm. Totally, there are 144 TSVs in the design. After bonding, electrical interconnection through the 1 [Online]. Available: htm /$ IEEE

3 YU et al.: FABRICATION OF SILICON CARRIERS WITH TSV ELECTRICAL INTERCONNECTIONS 567 Fig. 2. Schematic drawing of a silicon carrier. (a) Top view of a carrier. (b) Cross-sectional view of a carrier. carrier is made through TSV with on wall metallization. The designed electrical resistance between the top chip and the bottom chip through one TSV is lower than 1. The fluidic channels are connected out through the inlet and outlet ports in the carrier. There are sealing rings around both the fluidic path and the individual TSV to isolate the fluid from the electrical interconnection. The depth and the diameter of the TSV are 400 m and 150 m, respectively, whereas the depth and the width of the fluidic channels are 300 m and 350 m, respectively. III. INTEGRATION OF FABRICATION PROCESS A. Fabrication of Silicon Chip Fig. 3 describes the fabrication process for the silicon chips. The fabrication process starts with an 8-in silicon wafer. First, a layer of SiO 3 m thick is deposited by plasma-enhanced chemical vapor deposition (PECVD) process in a Novellus PECVD system and then patterned and etched with TSV and fluidic channel patterns as hard mask. The TSVs and the fluidic channels are etched with a deep reactive ion etching (DRIE) process. As the depth for the TSV and the fluidic channel is different, the DRIE process is separated into two steps. First, via with 100- m depth is etched using photoresist as etch mask, as shown in steps 2 and 3 in Fig. 3; then the photoresist is stripped and the vias and the channels are etched at the same time for 300- m depth, and the SiO layer patterned at the step 1 is used as etching mask. In order to reduce DRIE process time, after etching of the vias to 400 m deep, the silicon wafer is back grinded and polished to 400 m to expose the vias after the DRIE process. After wafer thinning, a passivation layer is deposited on both sides of the wafer. The passivation layer is 1- m SiO that deposited in a Plasma Therm SLR 720 system. After passivation, under bump metallization (UBM) is then sputtered and patterned around the TSV on both sides of the wafer. There is also a UBM ring patterned around the fluidic channels on front side of the wafer. The sputtering is done in a Balzer system. The UBM material used is Ti/Cu/Ni/Au with thickness of 0.1 m, 2 m, 0.5 m, and 0.1 m, respectively. In order to make sure that the sidewall of the TSV is coated with the metal film for electrical interconnection, a thick copper layer is used in the UBM layer and sputtered from both sides of the wafer. However, its electrical conductivity may worse than that of the platted copper. Also, the thick UBM layer makes wet etching of it more difficult. In this paper, the top Au layer Fig. 3. Fabrication process for silicon carrier. is etched with solution of tri-iodide, the Ni layer is etched with solution of AC-100, the Cu layer is etched with solution of A95 and the Ti layer is etched with 49% HF solution that diluted with DI water %HF H O. After patterning of the UBM layer, an inlet and an outlet are opened in the top silicon chip by the laser drill method. B. AuSn-Solder Lift-Off Process The AuSn-solder system is selected as the sealing material. Generally, 80wt%Au 20wt%Sn solder is widely used in the market because of its advantages, such as high reliability, high strength, high corrosion resistance, no thermal fatigue, allowing soldering in fluxless processes, etc. [4], [5]. AuSn-solder can be manufactured by various methods including evaporation, electro-deposition, paste, and solder preform. In this paper, the AuSn-solder is deposited by evaporation and patterned simultaneously by the liftoff process. The AuSn-solder consists of a sequence of Sn/Au layers (totally eight layers of Sn and eight layers of Au). The thickness for each Sn layer and Au layer is 0.2 m and 0.24 m, respectively. The evaporation is done in a Temescal E-Beam Evaporator (Model VES-2550) from Semicore Equipment, Inc. The evaporation rate is 5 Armstrong per second. During the liftoff process, a dry film 20 m thick is used as a mold. C. Wafer Level AuSn-Bonding After solder layer formation, wafer-level bonding is conducted to bond the two wafers together [6]. The bonding is carried out at 350 C, with 15 min of peak temperature hold time and compressive pressure of 4.7 MPa. After bonding, the bonded wafer is diced into single silicon carriers with size of mm. The dicing machine used is DAD 651 from Disco. The spindle speed is rpm and the feed rate 5 mm/s.

4 568 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 32, NO. 3, SEPTEMBER 2009 Fig. 4. SEM image of the fabricated silicon chip. Fig. 6. (a) UBM layer around the TSV after patterning. (b) AuSn solder ring after liftoff. Fig. 5. SEM image of the cross section of TSV. IV. RESULTS AND DISCUSSION A. Results of Silicon Chip Fabrication Fig. 4 shows scanning electron microscope (SEM) images of the silicon chip with the TSVs and the fluidic channels. Fig. 5 shows a cross section of the TSV. As the on wall metallization is done by double-side metal film sputtering, it is no need to fabricate taped TSV, which can simplify the DRIE process and save cost. Fig. 6(a) and (b) illustrates the UBM and AuSn-solder patterns around the TSVs. Both patterns are uniform with smooth edges. Fig. 7. Metal thin film on side wall of TSV. TABLE I ELECTRICAL RESISTANCE FOR DIFFERENT DIAMETERS OF TSV B. Evaluation of Electrical Connection After UBM patterning, electrical connectivity through the TSVs with different diameter has been tested and the results are listed in Table I. It is seen that when the diameter is larger than 150 m, the resistance through a TSV is less than 0.5. Therefore, the diameter of the TSVs in this work is selected as 150 m in order to have higher I/Os. Fig. 7 shows the cross section of the TSV after metallization. It is clearly seen that the side wall of the TSV is covered with a continuous metal layer.

5 YU et al.: FABRICATION OF SILICON CARRIERS WITH TSV ELECTRICAL INTERCONNECTIONS Fig. 8. SEM images of solder surface after shear test. (a) Over-view. (b) Zoomed view. 569 Fig. 9. Cross section of the bonding interface. (a) Cross section of embedded fluidic channels. (b) Cross section of AuSn solder ring after bonding. C. Evaluation of the Bonding Quality High bond strength of the silicon carrier is required for the following dicing and assembly process. In order to measure the bonding strength, shear strength measurements of the diced package samples were carried out by a commercially available shear tester (DAGE-SERIES-4000-T, Dage Precision Industries, Ltd., Aylesbury, U.K.). The shear strength value measured for 20 different samples ranged from 17.8 MPa to 35.1 MPa, and an average value of 27.2 MPa and a standard deviation of 2.2 are obtained. During the shear test, fracture always occurs at the UBM layer, which indicates that bonding strength is stronger than the adhesion strength of UBM layer. Fig. 8 is the SEM images after shear test. It is seen that the metal is peeled from the surface. Fig. 9 is the cross section of the bonding interface. It is seen that uniform interface has been achieved During AuSn bonding, bonding pressure is one of the critical parameters to obtain good bonding results. Fig. 10 shows the cross section of the AuSn-solder ring after bonding at 350 C, 15 min of peak temperature hold time, and compression pressure of 1.7 MPa. It is obviously seen that there is a gap in the middle of the interface. The reason for improvement of bonding quality with high pressure can be explained as that higher pressure can improve contact area between two bonding surfaces from both macro and micro points of view. Normally, silicon wafer is not ideally flat, especially after back grinding and polish and some micro fabrication process. Therefore, high pressure can push the two bonding surfaces contact each other intimately. As the same time, the AuSn-solder layer thickness after evaporation may has some variation and as shown in Fig. 11, root-mean-square (rms) Fig. 10. Crack in the bonding interface with bonding pressure of 3 kn. roughness of the AuSn surface after evaporation is about 25 nm. The rough surface will decrease the contact area between the two bonding surfaces. Therefore, high pressure is required to overcome the thickness variation and the surface roughness to improve the contact area between the two bonding surfaces. Fig. 12(a) and (b) shows the top and the bottom surfaces of a diced silicon carrier, respectively. The yield after dicing is higher than 98%, which indicates the bonding strength is high enough to pass through the dicing step. The meal patterns on both sides provide electrical interconnection and rerouting. The resistance of the electrical interconnection between the top and bottom surfaces of the carrier through one TSV varies between 0.5 and 2.5, with an average value of 1.16 for 20 interconnections. The value includes the resistance of the AuSn solder

6 570 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 32, NO. 3, SEPTEMBER 2009 D. Results of Fluidic Test Hermetic sealing of the bonded carrier is a key requirement of the project. A test setup has been developed to circulate water under high pressure through the carrier. The water flow rate is increased gradually up to 350 ml/min. No leakage is observed at high flow rate. The maximum pressure drop in the carrier is 6 10 Pa. Fig. 11. Surface roughness of AuSn solder after evaporation on UBM layer. The rms roughness is 25 nm. Fig. 12. Optical images of a diced silicon carrier. (a) Top surface. (b) Bottom surface. bonding layer and is 0.16 higher than the designed value. In order to decrease it further, a thicker metal layer and/or larger TSV diameter can be used. Thermal cycling test between 40 C (15 min) and 125 C (15 min) for 500 cycles has been conducted for the bonded silicon carrier. The temperature ramping rate is 15 C per min. After testing, the average shear strength of 20 samples is 26.8 MPa, which is kept almost same as that before thermal cycling test. V. CONCLUSION An integration process for silicon carrier with embedded thermal solution has been developed. The silicon carriers, having both electrical and fluidic interconnections, can act as substrates for chips mounting and then can be stacked over each other with a silicon interposer in between to form a cooling module for high power heat dissipation in 3-D packages. Evaporated AuSn is used as bonding material, and the uniform bonding interface without voids is achieved. Some important results are summarized as follows. 1) An integration process for fabrication of silicon carriers with both embedded fluidic channels and electrical interconnections has been developed. The silicon carrier can be stacked over each other with silicon interposers in between to make up of a stacked cooling module for high power heat dissipation. 2) After on wall metallization of TSV with diameter larger than 150 m and thickness less than 400 m, the electrical resistance through TSV is After bonding, the electrical resistance between top and bottom surfaces of the silicon carrier is 1.16, which is 0.16 higher than the designed value. It can be reduced by using thicker metal layer and/or larger TSV diameter. 3) For a single carrier, no leakage is observed at high flow rate (350 ml/min). The maximum pressure drop in the carrier is 6 10 Pa. 4) High bonding pressure can improve the bonding quality of evaporated AuSn-solder. With bonding pressure of 4.7 MPa, the die shear test strength is higher than 27 MPa and it is more than adequate for dicing/handling of the silicon carrier and to provide leakage free fluidic path. After 500 cycles of thermal cycling test ( 40 C to 125 C), the average die shear strength is 26.8 MPa and shows no degradation after thermal cycling test. ACKNOWLEDGMENT The authors would like to Dr. G. Y. Tang from MMC lab of IME and Mr. S. P. Tan from School of Mechanical and Aerospace Engineering, Nanyang Technological University, for their help in fluidic testing. The authors would also like to thank Dr. E. B. Liao, Mr. N. Ranganathan, Dr. Q. X. Zhang, Mr. K. W. Teoh, Mr. Z. Abdullah, and Ms. L. K. Ng from SPT lab of IME for their advice and help in fabrication of the silicon chip and Mr. W. S. Lee from MMC lab of IME for his help in wafer backside grinding and polish. REFERENCES [1] V. Kripesh, S. W. Yoon, V. P. Ganesh, N. Khan, M. D. Rotaru, F. Wang, and K. I. Mahadevan, Three-dimensional systemin-package using stacked silicon platform technology, IEEE Trans. Adv. Packag., vol. 28, no. 3, pp , Aug

7 YU et al.: FABRICATION OF SILICON CARRIERS WITH TSV ELECTRICAL INTERCONNECTIONS 571 [2] S. F. Al-Sarawi, D. Abbott, and P. D. Franzen, A review of 3-D packaging technology, IEEE Trans. Compon., Packag., Manuf., Technol. B, vol. 21, no. 1, pp. 2 14, Mar [3] M. R. Volgel, Liquid cooling performance for a 3-D multichip module and miniature heat sink, IEEE Trans. Compon., Packag., Manuf., Technol., vol. 18, no. 1, pp , Mar [4] W. Kim, Q. Wang, K. D. Jung, J. Hwang, and C. Moon, Application of Au Sn eutectic bonding in hermetic RF MEMS wafer level packaging, in Proc. 9th Int. Symp. Adv. Packag. Mater., 2004, pp [5] Y. T. Cheng, L. Lin, and K. Najafi, Localized silicon fusion and eutectic bonding for MEMS fabrication and packaging, J. Microelectromech. Syst., pp. 3 8, [6] S.-J. Ham, B. G. Jeong, J. H. Lim, K. D. Jung, K. D. Baek, W. B. Kim, and C. Y. Moon, Characterization and reliability verification of wafer level hermetic package with nano-liter cavity for RF-MEMS applications, in Proc. Electron. Compon. Technol. Conf., Reno, NE, May 29 Jun , pp Aibin Yu received the B.Eng. degree in materials science and the M.Eng. degree in electronic materials and devices from Shanghai Jiaotong University, Shanghai, China, in 1993 and 1996, respectively, and Ph.D. degree in the School of Electrical and Electronic Engineering from Nanyang Technological University, Singapore, in He is currently a Senior Research Engineer with the Laboratory of Microsystems, Modules, and Components, Institute of Microelectronics, Singapore. He has authored and coauthored over 50 peer-reviewed technical publications His research interests include advanced packaging, MEMS design, fabrication, and packaging. Navas Khan received the B.Eng. degree from Bagalore University, Bangalore, India, and the M.Eng. degree in mechanical engineering from Nanyang Technological University, Singapore. He is a Member Technical Staff at the Institute of Microelectronic, Institute of Microelectronics, Singapore. He has many years of experience in the area of system-level and package-level electronic packaging and thermal analysis. His research focuses are 3 D packaging and embedded wafer-level packaging. Giridhar Archit was born in 1982 in Chennai, India. He received the B.Eng. degree in mechanical engineering from the University of Madras, Chennai, India, in 2003 and the M.S. degree in MEMS engineering from Nanyang Technological University (NTU), Singapore, and École Supérieure D Ingénieurs En Électronique Et Électrotechnique (ESIEE), Paris, France. He was a Research Associate at NTU for the from 2007 to 2008, researching wafer-level packaging and hermetic sealing of micro-fabricated fluidic channels and 3-D stacking of MEMS-based silicon modules in collaboration with the Institute of Microelectronics, Singapore. He is currently working on nano-fabrication and nano-lubrication of MEMS, NEMS, and micro-mechanical devices at the National University of Singapore. His research interests are in the area of MEMS, micro/nano-fabrication, failure analysis, and reliability of MEMS and MEMS tribology. thermal management. Damaruganath Pinjala (M 92) received the B.S. degree from Regional Engineering College, Warangal, India, in 1989, and the M.S. degree from the Indian Institute of Technology, Kharagpur, in From 1991 to 1998, he was with the Center for Development of Telematics, Bangalore, India, in the area of thermal management of electronic systems. He joined the Institute of Microelectronics, Singapore, in His current research interests are in electronic and bio-microsystems packaging and Kok Chuan Toh, photograph and biography not available at the time of publication. Vaidyanathan Kripesh (M 01) received the M.S. degree in physics from the University of Madras, Madras, India, in 1987 and the Ph.D. degree in thick and thin film passives for microelectronics modules from the Max Planck Institute for Metalforschung, Stuttgart, Germany, in He has 20 years research experience in the area of advance packaging. He was a Visiting Scientist at Corporate Research, Infineon Technologies, Munich, Germany, in 3-D-integrated circuits. Since March 2000, he has been with the Institute of Microelectronics, Singapore, heading a group of researchers in 3-D-stacked silicon micro modules and wafer-level packaging processes. He has authored more than 60 journal and conference publications and holds 24 patents. He is also an Adjunct Faculty Member at the National University of Singapore, where he teaches microelectronics packaging. His research interests are 3-D silicon stacked modules, Cu/low-k packaging, and wafer-level packaging. Dr. Kripesh is a member of IMAPS, IEEE CPMT, and he is currently the President of IMAPS, Singapore Chapter. Seung Wook Yoon (M 05) received the Ph.D. degree in materials science and engineering from the Korea Advanced Institute of Science and Technology (KAIST), Seoul, in 1998 and the M.B.A. degree from Nanyang Technology University, Singapore, in He is Deputy Lab Director of Microsystem, Module, and Components (MMC) Lab, Institute of Microelectronics (IME), Singapore. His major interest fields are Cu/low-k/ultra low-k packaging, trough silicon via (TSV) technology, 3-D silicon micromodule technology, wafer-level integration, and microsystem packaging. Prior to joining IME, he was a Member of Technical Staff for Advanced Electronic Packaging and Memory Module Development, Hynix Semiconductor, in He worked for the development of lead-free solder applications, multichip packaging, CSP, wafer-level packaging, and was involved in JEDEC 11 activity. He is the author or coauthor of over 80 journal papers and conference papers and is the holder of several U.S. patents on microelectronic materials and electronic packaging. Dr. Yoon is member of the TMS. John H. Lau (M 88 SM 90 F 94) received three M.S. degrees in structural engineering, engineering physics, and management science and received the Ph.D. degree in theoretical and applied mechanics from the University of Illinois, Urbana-Champaign, He has been the Director of the Microsystems, Modules, and Components Laboratory, Institute of Microelectronics (IME), Singapore, since Prior to this, he was with HP/Agilent for more than 20 years. With more than 30 years of R&D and manufacturing experience in the electronics and photonics industries, he has authored and coauthored over 250 peer-reviewed technical publications, authored more than 100 book chapters, and given over 250 workshops and invited presentations. He has been teaching electronics and optoelectronic packaging courses for the IEEE, ASME, IPC, SMTA, ASM, NEPCON, and APEX since The engineers/managers from many prestigious companies had taken his courses with exceptional results and satisfactions. Dr. Lau received many awards from the ASME, IEEE, and other societies for best Transactions and Proceedings papers and outstanding technical achievements. He is also fellow member of the ASME.