Ultra thin chips for miniaturized products

Transcription

1 Ultra thin chips for miniaturized products Authors: Erik Jung, A. Ostmann (*),D. Wojakowski, C. Landesberger ( + ), R. Aschenbrenner, H. Reichl (*) FhG-IZM, TU Berlin (*) Gustav-Meyer-Allee 25, Berlin Hansa-Strasse 24, München ( + ) erju@izm.fhg.de 1 Abstract The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). The use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems utilize single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but active circuitry (IC s) and the necessary thermal management as well. Ultra thin chips (i.e. silicon dies thinned down to ~50µm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB s. Micro via technology allows to connect the embedded chip to the outer faces of the system circuitry. As an ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first approach to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable "box-of-bricks" type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT BGA. 2 Introduction Recent advances in chip thinning allow innovative approaches for single- and multichip packaging /1/, thereby reducing the required footprint of the package on board. Stacking concepts for those packages evolved from stacked LCCs via stackable BGA s towards stackable CSP s with just 0.5mm thickness each /1, 2, 3/. The concepts described in these references are dedicated to IC packaging, however the fundamental technologies developed allow also the direct integration of active circuitry into a PCB itself, serving as a miniaturized sub-system on a motherboard. Basically, the underlying technology of these approaches described in /1/ and /3/

2 lends itself easily to embedding technologies. Such embedding technologies have been investigated and described previously /e.g. 4, 5, 6/, lacking the technological advancement available today. Thin chips facilitate the use and applicability of large area manufacturing techniques commonplace in the PCB industry. However, material compatibilities, process availability and such like have not been investigated so far. Here, steps towards this goal are described and first results presented. 3 Technologies selected 3.1 Chip Thinning For chip thinning down to <<100um, basically three processes are available today. On one hand, all micro-thinning approaches rely on a coarse grinding process to remove of the wafer about 300um silicon bulk. So far, this process is state of the art for mass manufacturing of smart card wafers, requiring wafers with no more than 150um thickness. At this point, the fragility and stability of the silicon balance out. Removing additional material in this coarse fashion induces strong stresses and deep in-silicon damages - leading to very easy wafer fracture. Micro-Thinning now removes additional material and eliminates the stress resulting due to micro defects. Here, Spin Etching /7/ Plasma Etching (ADP Etch, /8/) Grind/CMP /9, 10/ allow to thin the chips down to less than 50um, even down to <10um remaining thickness /11/. The resulting silicon wafer is highly flexible and not any more subject to brittle fracture /Fig. 1/. Fig. 1: Thin silicon wafers can be bent without inducing fracture /7/ Dicing is done using either water jet assisted laser cutting or pre-cutting with a remaining uncut silicon of 50-60um prior the micro-thinning process (Dice-before- Grind, Dice-before-Etch) /12, 13, 14/ As a side notion, the chips must have at that

3 point a final metallization, that can be connected to the subsequent layers via the following process steps (e.g. chemical deposition, electrolytic deposition of metal). 3.2 Chip Assembly For chip assembly to the substrate, the die must be glued to the substrate surface with a suitable adhesive and placement equipment. The mass manufacturability of thin chip assembly has been shown by e.g. Toshiba and Sharp for their multi chip stacked CSP /15, 16/. As in these CSPs wirebonds are used and the wirebonding machine is capable of autonomous operation, initial placement accuracy is not very critical. In contrast to this, placement is a very important issue for the embedding technique as simultaneous exposure by a mask is used for the structuring of vias and metal routing. Therefore vision systems with top-down camera/optics and respective alignment patterns must be incorporated into the placement machine to provide an accuracy of ~15µm. 3.3 Dielectric Coating Covering the mounted IC with the subsequent dielectric layer for interconnect and additional routing requires the deposition of a suitable material. The use of photosensitive polyimide and BCB was successfully shown previously /5/. As the processing temperatures as well as the material compatibility to PCB material (e.g. FR4, FR5, CE etc.) is not given, epoxy materials were selected to serve as a dielectric. Although RCC foils lend themselves easily to lamination and laser drilling, for this first step, spin on, PCB compatible epoxy resin was used for the layer deposition. 3.4 Via Formation & Metal Deposition In today s high density PCB manufacturing, laser drilling with either excimer lasers or CO2 lasers as well as plasma etching /17/ is a well established process for indielectric via formation. Photo definition is another well known process, however it allows only limited material selection. When a photo sensitive epoxy material is selected, transparent films or glass masks can be used to structure the vias through the dielectric to the contacts of the chip. In our case, a photosensitive dielectric was spun on a 100x100mm carrier with embedded chips, using a glass mask and a collimated UV light source the vias were formed. Typically, in a PCB manufacturing facility, after via formation an electroless Cu seed layer is applied and reinforced by electro-deposited 5-15um Cu. In our case, for ease of processing, 6um of electroless Cu, as described in /18/, were deposited. Finally, the subsequent layers can be applied and structured as needed (Fig. 2) 3.5 Thermal Management The assembly of the thin chip to the substrate may be accomplished either on the base substrate itself or on a copper layer (e.g. large area circuitry) underneath (Fig. 3). The latter approach mimicks a built-in heat spreader, that can be attached by thermal vias or by heat traps to a larger heat sink. If for any reason this approach is not sufficient, active cooling by heat pipes or direct liquid cooling has been demonstrated previously to be incorporated into the PCB manufacturing process /19/.

4 Thin die directly on base substrate Thin die on patterned copper Si polymer Cu Base Substrate z.b. FR4 Fig. 2: Schematic of the embedded structure Fig. 3: Different methods for chip attach to the substrat 4 Experimental approach 4.1 Description of the demonstrator The demonstrator was defined to route an embedded 10x10mm 2 silicon chip with ~50µm thickness to peripheral contacts, drilled through to the other board side. Alternatively, as shown previously in /18/, the contacts can be routed to the inner area of the die serving as a non stackable CSP. The base material selected for the substrate was a 0.5mm thick FR4 board with 100x100mm size. The schematic (layout) of the demonstrator is given in /Fig. 4/. Fig. 4: Schematic of the demonstrator The chips had 5um thick electroless nickel with a cemical Cu finish deposited to their aluminium pads to allow the contacting with electroless/electrolytic processes. They were grinded to 150um and spin etched down to a final thickness of 50µm using a carrier wafer. As described above the thin silicon chips were placed into a cross pattern of non filled die bond adhesive dispensed onto the pre-conditioned (dry-bake at 125 C/2hrs) substrate. Curing of the adhesive was done according to the manufacturer s recommendation. Photosensitive epoxy resin was spin coated to the surface of the chip-substrate assembly to a final thickness of 80um in a multiple stage coating process. Using a glass master, the via- and rerouting-pattern was copied by UV illumination onto the dielectric and subsequently developed. Deposition of the metal layer was accomplished using a high speed electroless Cu bath. Fig. 5 shows a sample view on the rerouted chip I/O s., Fig. 6 shows the respective via in cross sectional view. Final capping for solderability and diffusion resistance was performed using electroless nickel deposition /20/.

5 Fig. 5: Vias to the Chip I/O s and routing structures using electroless Cu deposition. Fig. 6: Cross section through a chip contact via The initial results have yielded a evaluation sample of a PCB with embedded thin silicon dice. An image of the demonstrator is given in /Fig. 7/. A full characterisation was not available to date of print. Pads embedded Chip Vias Cu-traces Fig. 7: Demonstrator of PCB with embedded thin silicon chips 5 Future steps After verifying the structures with reliability tests like thermal/humidity exposure and thermal shock/cycling, next steps will approach a two layer embedding of thin chips using the described technology. This would potentially result in a multilayer multi chip stackable CSP as schematised in Fig. 8. On a PCB, optical inserts as demonstrated in /21/ could open up a new field for this PCB compatible embedding approach. Using thin, flexible batteries (Fig. 9), autonomous disposable systems can be created /22/. Fig. 8: Schematic structure of a multilayer multi chip stackable CSP Fig. 9: Thin, flexible batteries allow miniature autonomous systems

6 6 Acknowledgements The authors would like to thank the team of the 3D-CSP and the ChiP task force at IZM Berlin/Munich and TU Berlin as well as the colleagues from the PCB industry having supported this feasibility study with activity and discussion. Part of the work shown here is done in of the BMBF Project "Systemintegration in polymere Schaltungsträger", No.02PP2051, co-ordinated by the FZK-PFT. The support is gratefully acknowledged. 7 References /1/ S. Andersson, "Packaging - Providing Solutions between Silicon and System", IEMT 2000, Santa Clara, Oct. 2000, Keynote Talk /2/ M. Schünemann et al., "MEMS Modular Packaging and Interfaces", 50th IEEE Electronic Components and Technology Conference, Las Vegas, May 2000 /3/ Chino et al., "Half-Stacked Milli-CSP", Proc. IEMT 2000, Santa Clara, Oct. 2000, pp. 141 /4/ Eichelberger et al., US Patent US : "Single chip modules, repairable multichip modules, and methods of fabrication thereof" /5/ Hahn et al., Fabrication of high power MCM by planar embedding technique and active cooling, Micro Systems Technology, 1996 /6/ Klose: Chip First Systeme und Gehäuse, Thesis from Univ. Siegen, Germany, Jan. 2000, ISBN /7/ Landesberger et al., Jahresbericht des Fraunhofer-Instituts IZM, 1999 /8/ Savastiouk et al., "3D Wafer Level Packaging" Proc IEMT Europe 2000, Munich, April 2000 /9/ Gaulhofer et al, "Wafer Thinning and Strength Enhancement to meet emerging packaging requirements", Proc IEMT Europe 2000, Munich, April 2000 /10/ PDF-Brochure from /11/ Landesberger et al., "Vom starren Wafer zum flexiblen Chip", Forum "Dünne Halbleitersubstrate", IZM Munich, Oct. 2000, Munich /12/ Juch, "Erfahrungen mit dem Hochratenätzer XPL-900", Forum "Dünne Halbleitersubstrate", IZM Munich, Oct. 2000, Munich /13/ Richertzhagen, "Vereinzeln von dünnen Wafern mit dem MicroJet Verfahren", Forum "Dünne Halbleitersubstrate", IZM Munich, Oct. 2000, Munich /14/ electronic article in semiconductor/issues/issues/1999/oct99/d ocs/assembly.asp /15/ Fujitsu et al, "Paper Thin Package", SEMI Japan Technology Symposium, Chiba, Dec /16/ Francis, "Thinning Wafers for Flip Chip Applications", HDI Magazine, Vol.2 No. 5, May 1999, pp. 18 /17/ for a thorough process description see best information on /18/ Ostmann et al, " Development of an Electroless Redistribution Process", Proc. IMAPS Europe 1999, Harrowgate, June 1999 /19/ Public report on the project Mikrosystemtechnik mit flexiblen Schaltungsträgern, BMFT Projekt 1994, keyword "ILFAcool", see also documents available at /20/ Ostmann, Simon, Reichl, The Pretreatment of Aliminum Bondpads for Electroless Nickel Bumping, IEEE Conf. on MCM, Santa Cruz, March 1993, pp /21/ Detlef Krabe et al, "New Technology for Electrical/Optical Systems on Module and Board Level The EOCB Approach "., Proc. 50th ECTC, Las Vegas, May 2000 /22/ Brochure from Power Paper,