Fine Pitch Probing and Wirebonding and Reliability of Aluminum Capped Copper Bond Pads

Size: px
Start display at page:

Download "Fine Pitch Probing and Wirebonding and Reliability of Aluminum Capped Copper Bond Pads"

Transcription

1 Intl. Journal of Microcircuits and Electronic Packaging Fine Pitch Probing and Wirebonding and Reliability of Aluminum Capped Copper Bond Pads Tu Anh Tran*, Lois Yong*, Bill Williams**, Scott Chen***, and Audi Chen*** * Motorola Semiconductor Products Sector 31 Ed Bluestein Boulevard Austin, Texas Tu.Anh.Tran@motorola.com, Lois.Yong@motorola.com ** Motorola Semiconductor Products Sector 13 North Alma School Road Chandler, Arkansas 82 RXFP6@ .sps.mot.com ** *Advanced Semiconductor Engineering (ASE), Chung-Hwa Road Sec. 1, Chung-Li Taiwan, R.O.C. s: Scott.Chen@asecl.com.tw, Audi.Chen@asecl.com.tw Abstract The requirement for improved electrical performance and reduced silicon area has driven Copper to replace Aluminum interconnection as silicon technology is scaled beyond.2µm. The front-end change, in turn, pushes wirebond pad pitch from above 1µm to 8µm-66µm range. This creates challenges for back-end to probe and wirebond at fine pitch geometry onto a readily oxidized Copper surface. After several re-metallization structures and types of metallurgy were evaluated, capping Copper bond pads with Aluminum was selected as the primary approach for probing and wirebonding Copper devices. Aluminum re-metallization structure offers many advantages that help leverage existing tooling and knowledge in fab, probing, and wirebonding processes. This paper will describe probe and wirebond experiments used to select the proper adhesion and diffusion barrier between Copper and Aluminum, and Aluminum thickness that can withstand the mechanical stress during probing and wirebonding. Probe mark depth and the impact of probe marks to the underlying barrier and Copper pad were examined. Ball shear, wire rip, and corresponding failure modes, intermetallic coverage and cratering analysis were evaluated at various readpoints of thermal aging study to evaluate the integrity of the re-metallization structure as well as the quality of ball bonds onto the new structure. Contact resistance measurement and reliability assessment were also performed. One re-metallization structure was recommended for Copper High Performance wirebonded devices. Key words: 1. Introduction Copper Interconnection, Aluminum Capped Copper bond Pads, Adhesion/Diffusion, Probe Process, Wirebond Process, and Package-level Reliability. The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) 332 The requirements for improved electrical performance, higher speed, and increased packing density have driven Copper to replace Aluminum interconnection. The challenges for back-end probe and assembly- in processing Copper (Cu) wafers are as follows: (1) the back-end has to accommodate much finer pitch geometry in the range from 8µm to 66µm pad pitches; (2) Cu is readily oxidized in air at low temperature (<2 o C) and forms no

2 Fine Pitch Probing and Wirebonding and Reliability of Aluminum Capped Copper Bond Pads self-passivating layer to stop further oxidation and erosion; and (3) in some wireless applications, the last Cu layer can be as thin as.42µm. There are three main approaches to treating Cu bond pad surface to provide a reliable, probe-able and wirebondable surface: (1) replacing the last Cu layer with an Aluminum (Al) layer; (2) re-metallizing Copper pads with noble metal (for example Gold and Palladium) or self-passivated metal (such as Aluminum); and (3) no additional treatment so that probing and wirebonding directly onto Copper pads must be developed. Capping Cu bond pads with Aluminum was selected as the primary approach for Cu wirebonded devices 1. This approach helps leverage well- established Al probe and assembly flows, and wirebonders using Gold wire. Since Cu diffuses quickly into Al forming very brittle intermetallics that would degrade the device reliability, Cu-Al structure requires a complete isolation from each other by a thin film layer that functions as an adhesion promoter and a diffusion barrier for both Cu and Al. Ta, TaN, Ti/TiN and Tungsten are various barrier materials available for Cu interconnect processing due to their excellent barrier and adhesion properties 2. The process for capping Cu pads with Al begins with a Cu oxide removal process. An adhesion/diffusion barrier is deposited across the wafer, then Al is subsequently deposited. A photoresist layer is applied, exposed, and developed. The barrier and Al layers are etched out, leaving an Al cap slightly larger than the bond pad. The construction of Al capped Cu pads is illustrated in Figure 1. Passivation Dielectric Al Cu Pad 2. Probe Experiments to Evaluate Aluminum Cap Thickness The purpose of the probe experiment was two-fold; (1) to establish the probe process window for Al capped Cu bond pads, and (2) to recommend an Al cap thickness. The Al cap thickness must be sufficient such as to withstand worst case probe conditions without disturbing the underlying adhesion/diffusion barrier. Due to brittle Cu-Al intermetallics and related long-term degradation of the metal stack, the barrier film must be kept intact to ensure separation between Cu and Al layers. Three probe variables were considered, probe tip diameter, probe overdrive, and number of probe touchdowns. Two tip diameters were evaluated, 1.2 mil as the standard production size and 1. mil in anticipation of finer pitch geometry. Three settings of needle overdrive were selected, 4µm, 6µm, and 8µm. The center value, 6µm, is the nominal overdrive used in most production probe. Four settings of number of touchdown were 2 touches (low), 4 touches (normal), 8 touches (high), and 16 touches (expected to force fails). Probe marks were visually inspected and profiled using a profilometer. The effect of probe mark on the underlying barrier was examined using Scanning Electron Microscopy (SEM) images after stripping off the Al cap using the well-established NaOH etching technique. Two methods were employed to detect Cu exposure: EDX to analyze the deepest area of the probe mark for Cu pad exposure, and 2:1 H 2 O 2 :HNO 3 etchant for minutes to detect potential corrosion/migration path between the barrier and passivation. One Al cap thickness would be recommended. Wafers with the selected Al cap thickness would be probed, and sent for assembly evaluation. Figure 1. Structure of Aluminum capped Copper bond pad. 3. Assembly Experiments to Evaluate The test vehicle was a 6.7mm x 6.7mm daisy chain device with one.42µm thick Cu metal layer. Bond pads were designed at 76µm wire pitch with 72µm x 96µm passivation opening. Wafer splits were processed with two adhesion/diffusion barrier metals (barriers A and B) and three Al cap thickness (thin, thick, and The scope of the assembly experiment was five-fold: (1) to thickest). Thin Al thickness had revealed stained or corroded establish a wirebond process window for Al capped Cu pads, (2) Cu lines after probing and acid dipping test. The non-hermetic to assess the quality of ball bonds on the Al capped Cu structure, cap caused a concern in latent reliability degradation. The thickest (3) to evaluate the integrity of the adhesion/diffusion barrier, (4) Al cap was preferred for back-end processing. However, this to assess the reliability of packaged parts, and () to ascertain required the longest metal etching time. whether one barrier is superior to another. This paper will describe probe and wirebond experiments designed The wafers were processed in a standard production flow, to evaluate the integrity of the adhesion/diffusion barri- which includes a plasma clean process prior to wirebonding. Dice ers, and the Al cap thickness that can withstand the mechanical were wirebonded with 1 mil wire (Au > 99.99%) on a machine stress during probing and wirebonding, while minimizing Al with a 6kHz transducer. Power and force settings from the standard etching duration and maintaining the lowest system cost solution. Al interconnect process were used as a baseline to establish One Cu re-metallization structure, one adhesion/diffusion the wire bond process window for Al capped Cu pads. The low, barrier and one Al cap thickness, will be recommended for Cu normal, and high levels of power were-, 7, and 9mW, and interconnect wirebonded devices. three levels of force were- 2, 4, and g. The time parameter was held constant at 1ms. The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) 333

3 Intl. Journal of Microcircuits and Electronic Packaging Wirebond responses were non-stick at first bond, percentage of pad lift/ball lift during wire rip test, Au-Al intermetallic coverage, and pad cratering analysis. Plastic Ball Grid Array (PBGA) substrate strips wirebonded at normal and high wirebond settings were then submitted for barrier evaluations. In order to determine the quality of Au bonds and the integrity of the barrier as an adhesion/diffusion layer between Cu and Al layers, thermal aging test was chosen. Heat treatment for an extended period of time promotes inter-diffusion between Cu and Al layers, thus making this a suitable test to expose weaknesses in the barrier layer or in the deposition method. Substrate strips of wirebonded but not molded devices were aged in a N 2 chamber at 17 o C and removed at,,, 1, 2,, and 1 hours for evaluation. Au-Al ball shear strength and failure mode were obtained. The height of the shear tool was programmed at 3µm above the bond pad. Since fine pitch wirebonding results in low squash height, 3-µm tool height is a widely accepted setting to ensure that the ball will be sheared through the range of fully grown intermetallics 3. Au-Al intermetallics coverage and growth during thermal aging was determined using SEM imaging of the underside of Au ball bonds after they were removed from the Al cap by the NaOH etching solution. Au-Al intermetallics coverage and thickness was also examined in cross-sectional SEM images. Grain boundary staining was achieved using an aqua-regia based etchant (ratio of : by volume of HNO 3 :HCl). The effect of thermal aging to the integrity of the barrier and of the Al cap structure was evaluated by four methods: NaOH etching, Au wire rip test, four-point circuit resistance measurement, and cross-sectional Transmission Electron Microscopy (TEM). Since the NaOH etching solution used to etch off Au bonds from the Al cap dissolves the Al cap and exposes the underlying adhesion/diffusion barrier, inspection of the barrier could be conducted. The extent of barrier disturbance was recorded. The wire rip test was used in place of the standard wire pull test. Although the absolute pull strength was not recorded, visual inspection of failure modes could be used to determine the strength of the pad structure. A strong pad structure is indicated by a break at the annealed area above the ball (typically termed as break at neck ). Two less desirable failures modes are ball lift, where the Au ball bond is detached from the bond pad leaving the Al pad intact; and pad lift, where the Au ball bond is detached from the bond pad, pulling Al and the underlying pad structures with it. Devices submitted to package-related reliability testing were assembled in mm x 17 mm x 1.3 mm 1 mm pitch PBGA. The parts underwent Moisture Sensitivity Level 3 (MSL3), preconditioning (1 cycles of temperature cycling -6 o C/1 o C, bake 12 o C/ hrs, moisture soak 3 o C/6%RH/192 hrs, and 3 cycles of Vapor Phase Reflow). After preconditioning, some parts were subjected to Temperature Cycling (-6 o C/1 o C for 2 cycles), and Autoclave (121 o C, 1%RH, 1PSIG for 144 hours). 4. Impact of Probe Mark to Underlying and Cu Pads Figure 2 shows an example of the profilometry output measuring probe marks in the x-direction. Table 1 summarizes the depths of probe scrubs measured across multiple wafers. The depth of probe mark was heavily dependent on probe conditions. In effect, the heavier overdrive, higher number of probe passes, and smaller probe tip diameter resulted in a deeper probe needle penetration into the Al cap. At the small 1-mil tip diameter, the probe scrub was measured about 8-9kÅ deep with 8X probe touches. The depth of probe mark was independent of the underlying barrier. Probe Scrub 9kÅ Al Cap above Passivation Opening Bond Pad Level Passivation Level Figure 2. Profilometry graph of probe mark. Table 1. Depth of probe marks as a function of tip diameter, overdrive, and probe passes. (depth in kå) Probe Passes Overdrive (um) 1X 2X 4X 8X 16X Black: 1.2 m il tip G re y: 1. m il tip The effect of probe marks on barrier types was evaluated after the Al cap was stripped and revealed the barrier. Although the probe scrub did not penetrate through the entire Al cap thickness, barrier disturbance was found. The deeper the probe marks were, due to either a thin Al cap or heavy probe conditions, the harder the force propagated through the Al cap to disturb the barrier. Figure 3 depicts the progression of barrier disturbance as a response of probe conditions. At normal probe condition, no barrier disturbance was detected. At high probe condition, barrier cracking or trenching was found under thin Al cap whereas only barrier trenching was found under thick Al cap. Furthermore, less disturbance was found on barrier A than on barrier B given the same probe conditions. The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) 334

4 Fine Pitch Probing and Wirebonding and Reliability of Aluminum Capped Copper Bond Pads A Al Cap Thickness = Thin Probe Tip = 1 mil B Al Cap Thickness = Thick Probe Tip = 1 mil The low power/low force combination used in the standard Al process did not produce acceptable bonds on Al capped Cu pads. This indicated that the wirebond process has shifted to the right. Additional process characterization and optimization have been planned. (a) Overdrive = 4 um, # Touches = 4x 6. Aging Behaviors of Au-Al Bonds on Al Cap Structures (b) Overdrive = 6 um, # of Touches = 8x Figure 3. disturbance observed on probed wafers after NaOH etch. No Cu staining or corrosion was found around the barrier and passivation on the thin Al cap, indicating that the Al cap structure was hermetic. At the deepest area of the probe marks, EDX did not detect any Cu exposed from the underlying bond pad. Although no Cu metal was exposed, the barrier disturbance during probing was a concern since this could potentially lead to Cu-Al inter-diffusion path. The thickest Al cap could resolve this concern; however, this would entail longer metal etching time. Therefore, after considering front-end and back-end implications, the mid-range Al cap thickness was recommended as the minimum thickness to ensure pad integrity across the range of probe conditions and as a compromise with fab s metal etch. Wafers with the selected Al cap thickness were probed with a 1 mil probe tip, at 6µm overdrive, six touchdowns, and sent to assembly for evaluation. Through the initial probe experiments, probe process window for Al capped Cu pads was similar to that for standard Al pads. However, further probe optimization was planned to characterize probe parameters to ensure no barrier disturbance at finer pitch geometry. Figures 4 and show ball shear strength as a function of thermal aging time for normal and high wirebond settings for barriers A and B, respectively. Both barriers met the minimum shear strength of 1gf. As the intermetallic thickness increased due to greater inter-diffusion with extended aging, the ball shear strengths at either wirebond setting increased with thermal aging up to hours. Beyond hours, the ball shear strengths decreased. The shape of the curve depicting the shear strength versus time confirms what is found in the literature, in which the ball shear strength increases dramatically from hour to hours, and then increases only slightly beyond hours. Ball Shear Tim e (h rs ) Figure 4. Ball shear strength versus thermal aging at 17 C for barrier A. Ball Shear ( Time (h rs). Wirebond Process for Al Capped Cu Pads An initial five-cell wirebond process evaluation was conducted. At low force setting (2g), non-stick at first bond and ball lift during the wire rip test were found. This was caused by a low Au-Al intermetallic coverage of less than 2%. At a combination of low force and high power settings, pad cratering was seen. Cells with normal and high settings resulted in no failures. These two wirebond conditions were used to process strips for subsequent thermal aging study. From this initial study, it was concluded that the wirebond process for Al capped Cu was different from that for standard Al. Legend for Figures 4 and : Normal Wire Bond Settings High Wire Bond Settings - 1 Std Dev (Normal Wire Bond Settings) x 1 Std Dev (High Wire Bond Settings) Figure. Ball shear strength versus thermal aging at 17 C for barrier B. (sample size/sell: 16 balls/unit x units). At normal wirebond settings, shear strength was similar for both barriers and reached a peak at 2- hours. At high wirebond settings, shear strength for barrier A was higher than that of barrier B. It was verified that there was a statistically significant difference between ball shear readings for the two barriers at high wirebond settings for all temperature readpoints except for the readpoint at hours. The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) 33

5 Intl. Journal of Microcircuits and Electronic Packaging The superior performance of barrier A over B is further illustrated in Figures 6 and 7 where the shear strength per unit area (gf per mil 2 ) is plotted. The ball shear per mil 2 data give an indication of the stability and robustness of the Al Cap Cu process across different wirebond parameter settings. The minimum shear strength per mil 2 of.gf/mil 2 was met by both structures. Ball shear strength per unit area of barrier A was high and stable across the wirebond process window whereas ball shear per unit area of barrier B decreased at the high wirebond setting, approaching the minimum strength limit. Lower values for barrier B could be attributed to lower shear readings and larger ball diameters. Ball Shear per mi (gf/mil2) um ball size 72um ball size The distribution of ball shear failure modes of the two barriers at normal and high wirebond settings is shown in Figures 9 and 1. At normal wirebond conditions, mode 1 (ball lift) was prevalent at time zero for both barriers due to thin Au-Al intermetallic phases (IPs). With increased thermal aging from hours to hours, the failure mode switched to mode 2 (ball shear) as the IP zone grew thicker. A small percentage of mode 3A (pad lift exposing SiO 2 ) was also observed. This failure mode occurred when there was a mixed failure of a fracture through the IPs and an IP-SiO 2 interfacial fracture. It was speculated that mode 3A was device related. At 1 hours, mode 3B with pad lift exposing barrier was more prevalent. The Al cap was completely consumed into the Au-Al IPs. Shearing through the Au- Al IPs would peel off the depleted Al cap, resulting in weaker ball shear strength. For both barriers at high wirebond conditions, mode 2 (ball shear) dominated at all thermal aging intervals until 1 hours where more mode 3B was observed. Norm alw ire B o n d High W ire B o n d Figure 6. Ball shear strength per mil 2 versus thermal aging at 17 C for barrier A. Ball Shear per mil2 (gf/ um ball size 77um ball size Norm alw ire B o n d High W ire B ond % Failure Mode Normal WB Time (hrs) Figure 9. Distribution of ball shear failure modes for barrier A. Figure 7. Ball shear strength per mil 2 versus thermal aging at 17 C for barrier B. 1% Normal WB Figure 8 illustrates four failure modes encountered during ball shear testing: ball lift (mode 1), ball shear (mode 2), pad lift exposing SiO 2 (mode 3A), and pad lift exposing barrier (mode 3B). % Failure Modes 8% 6% 4% 2% % Time (hrs) Figure 1. Distribution of ball shear failure modes for barrier B. Mode 1 Mode 2 Mode 3A Mode 3B The progression of IP growth was also monitored through SEM images of the underside of the bonded balls after etching off the Al metallization and through cross-sectioning of the bonded balls (Figure 11). Balls bonded onto Al cap Cu pads with different barriers exhibited similar behaviors. SEM analysis of the underside of the Au ball at readpoint of 2 hrs showed the progressively increasing intermetallic thickness. Since NaOH etches Al faster than Au, 2 phases of the IP are clearly seen in Figure 11 at 2 hour thermal aging. Figure 8. Failure modes after ball shear and rip tests. The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) 336

6 Fine Pitch Probing and Wirebonding and Reliability of Aluminum Capped Copper Bond Pads After Hour Bake (Higher Magnification) After 2 Hour Bake (Higher Magnification) Al rich region Au rich region After the Al Cap was etched off, the barrier metal left on the bond pad was inspected. No disturbance was found on both barrier metals. This indicates that a ball bond could be created between the Au wire and the Al Cap, without disturbing the under- The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) lying barrier material. The four-point circuit resistance measurements were similar for both barriers. The resistance measurement was taken as a response to forced current through the pad structure. The resistance was measured at ohms consistently across the thermal aging duration. The stability of the circuit resistance and the integrity of the barrier after thermal aging were also confirmed with TEM images of the adhesion/diffusion barriers across thermal aging (Figure 14). Both barriers appeared to be intact after 2 hours. Figure 11. SEM images showing underside of Au ball and ball cross-section through thermal aging. B Al Cu B Cu 7. Aging Behaviors of Cu/ A/Al and Cu/ B/Al Pad Structures Figure 14. TEM images of barrier B structure (barrier A structure looked similar and is not shown). Figures 12 and 13 present results of the wire rip test for barriers A and B at normal and high wirebond settings. Minimal lifted balls or pad lifts were recorded for both barriers at thermal intervals less than hours, indicating a strong pad structure. At hours and longer, the progressive transformation and depletion of Al metallization into the Au-Al IPs was recorded as ball lift exposing barrier (failure mode 3B). Pads with barrier A were more robust than those with barrier B, with less pad lifts and ball lifts across thermal aging. % of Pad Lifts 12% 1% 8% 6% 4% 2% % Normal WB 2 1 Figure 12. Wire rip test results for barrier A. % of Pad Lifts 12% 1% 8% 6% 4% 2% % Normal W B A 1 46% 3B Figure 13. Wire rip test results for barrier B. (sample size/ cell: 222wires/unit x 2 units). 3A 3B 8. Reliability Results Table 2 shows the results of reliability testing for packaged units with the two Al cap structures. Both structures passes 2 cycles of temperature cycling. Some packages failed open or short testing during 96 hours and 144 hours of autoclave. Failure analysis indicated that these failures were not associated with the Al cap structure or the barrier. Bond pads were corroded as a result of fab processing. With subsequent change in fab processing, packages passed autoclave testing without failures. Table 2. Reliability results. A MSL3 Pre-conditioning /8 (a) Air-to-Air Temperature Cycling -6C Autoclave to 1C hours Cycles Cycles Cycles Cycles hours /4 (a) /38 (a) /3 /3 2/38 (c) 3/36 (d) B MSL3 Pre-conditioning 1/8 (b) Air-to-Air Temperature Cycling -6C Autoclave to 1C hours Cycles Cycles Cycles Cycles hours /4 (a) /38 (a) /3 /3 2/39 (b) /37 (a) Parts Removed for Physical Analysis (b) Open - Missing Solder Ball (c) 1 Open - Recovered After Clean, 1 Short - Corroded Bond Pads (d) 1 Short, 2 Open - Corroded Bond Pads 337

7 Intl. Journal of Microcircuits and Electronic Packaging 9. Selecting One adhesion/diffusion The Au-Al intermetallic growth behavior on Al capped Cu pads was in very good agreement with that on standard Al pads. Packaged parts have passed production-level reliability evaluations. Through thermal aging test, Cu pads re-metallized with Al film separated by either barrier performed similarly in many aspects: stable circuit resistance, good adhesion and diffusion property, and strong pad structure over time. There exist, however, some statistically significant differences between the two barriers that indicate the more robust barrier A/ Al structure for back-end processing. Less disturbance was found on barrier A than on barrier B given the same Al cap thickness and probe conditions. A/Al structure provided statistically improved performance over B/Al structure in ball shear strength across the evaluated wirebond process window, and more stable Au-Al intermetallic strength over thermal age duration. Less pad lift was observed on barrier A than on barrier B. About the authors Tu Anh Tran and Lois Yong are presently working at Motorola Final Manufacturing Technology Center focusing on wirebond package development. Bill Williams is in Motorola Final Manufacturing Technology Center focusing on fine pitch probe development for wirebonded packages. Scott Chen and Audi Chen are currently working in the process engineering group at Advanced Semiconductor Engineering (ASE) in Chung-Li, Taiwan. Acknowledgments The authors would like to thank the following people for their support in their respective expert areas: Scott Pozder and Thom Kobayashi in leading the Al Cap Processing team; Gloria Estrada, Dennis Kiffe, Gordon Fowkes and John Milton in conducting thermal age testing; Van Ho and Jeff Bosworth for electrical testing and reliability testing; Chuck Miller, Kevin Hussey, Gary Clark, Ava Morrision, Steve Heineke and Chongnan Kim for surface and physical analyses ; Joan Sibbitt, Tony Angelo, Xuefeng Liu and Mary Di for probe testing and Failure Analysis work; and Andrew Mawer and Thomas Koschmieder for providing N 2 oven support. References 1. T. Tran, Approaches to Probing and Wire bonding onto Copper Bond Pads, Motorola 1999 Hermes Symposium, Austin, Texas, September 2-, C. Ryu, H. Lee, K.W. Kwon, A. Loke, and S. Wong, s for Copper Interconnections, Solid State Technology, pp. 3-6, April K. Dittmer, S. Kumar, and F. Wulff, Influence of Bonding Conditions on Degradation of Small Ball Bonds due to Intermetallic Phase (IP) Growth, Proceedings of SEMICON Singapore, Test, Assembly & Packaging, May, The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2 (ISSN ) 338

Characterization of 0.6mils Ag Alloy Wire in BGA Package

Characterization of 0.6mils Ag Alloy Wire in BGA Package Characterization of 0.6mils Ag Alloy Wire in BGA Package Toh Lee Chew, Alan Lumapar Visarra, *Fabien Quercia, *Eric Perriaud STMicroelectronics Muar, Tanjung Agas Industrial, P.O.Box 28, 84007, Muar, Johor

More information

Cu-Al intermetallic growth behaviour study under high temperature thermal aging

Cu-Al intermetallic growth behaviour study under high temperature thermal aging Cu-Al intermetallic growth behaviour study under high temperature thermal aging C.L Cha, H.J Chong, Yaw HG, Chong MY, Teo CH Infineon Technologies, Melaka, Malaysia Abstract Copper (Cu) wire always gains

More information

Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes

Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes Hugh Roberts Atotech USA Inc., Rock Hill, SC, USA Sven Lamprecht, Gustavo Ramos and Christian Sebald Atotech Deutschland

More information

Copper Wire Packaging Reliability for Automotive and High Voltage

Copper Wire Packaging Reliability for Automotive and High Voltage Copper Wire Packaging Reliability for Automotive and High Voltage Tu Anh Tran AMPG Package Technology Manager Aug.11.2015 TM External Use Agenda New Automotive Environments Wire Bond Interconnect Selection

More information

EFFECTS OF THERMAL AGING ON INTERMETALLIC COMPOUNDS AND VOIDS FORMATION IN AuAl WIRE BONDING. A. Jalar, M. F. Rosle and M. A. A.

EFFECTS OF THERMAL AGING ON INTERMETALLIC COMPOUNDS AND VOIDS FORMATION IN AuAl WIRE BONDING. A. Jalar, M. F. Rosle and M. A. A. EFFECTS OF THERMAL AGING ON INTERMETALLIC COMPOUNDS AND VOIDS FORMATION IN AuAl WIRE BONDING A. Jalar, M. F. Rosle and M. A. A. Hamid School of Applied Physics, Faculty of Science and Technology, Universiti

More information

The Development of a Novel Stacked Package: Package in Package

The Development of a Novel Stacked Package: Package in Package The Development of a Novel Stacked Package: Package in Package Abstract Stacked die Chip Scale Packages (CSPs) or Fine-pitch BGAs (FBGAs) have been readily adopted and integrated in many handheld products,

More information

Cu Bond Wire Reliability and Decapsulation Process

Cu Bond Wire Reliability and Decapsulation Process CMSE Los Angeles April 12 th and 13 th, 2017 Cu Bond Wire Reliability and Decapsulation Process Sultan Ali Lilani - Integra Technologies LLC Ph 510-830-9216 Email: sultan.lilani@integra-tech.com Web: www.integra.com

More information

Motorola MC68360EM25VC Communication Controller

Motorola MC68360EM25VC Communication Controller Construction Analysis EM25VC Communication Controller Report Number: SCA 9711-562 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

Transverse Load Analysis For Semiconductor Applications

Transverse Load Analysis For Semiconductor Applications Transverse Load Analysis For Semiconductor Applications Presenters: Soheil Khavandi Co-authors: Parker Fellows Robert Hartley Jordan James Aaron Lomas Advisor: Jerry Broz, Ph.D. UNR Owen Stedham Award

More information

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Andrew Strandjord, Thorsten Teutsch, and Jing Li Pac Tech USA Packaging Technologies, Inc. Santa Clara, CA USA 95050 Thomas Oppert, and

More information

Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die.

Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die. Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die. A. JALAR, M. F. ROSLE, M. A. A. HAMID. School of Applied Physics, Faculty of Science and Technology Universiti Kebangsaan

More information

NEC 79VR5000 RISC Microprocessor

NEC 79VR5000 RISC Microprocessor Construction Analysis NEC 79VR5000 RISC Microprocessor Report Number: SCA 9711-567 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

THE EFFECTS OF PLATING MATERIALS, BOND PAD SIZE AND BOND PAD GEOMETRY ON SOLDER BALL SHEAR STRENGTH

THE EFFECTS OF PLATING MATERIALS, BOND PAD SIZE AND BOND PAD GEOMETRY ON SOLDER BALL SHEAR STRENGTH THE EFFECTS OF PLATING MATERIALS, BOND PAD SIZE AND BOND PAD GEOMETRY ON SOLDER BALL SHEAR STRENGTH Keith Rogers and Craig Hillman CALCE Electronic Products and Systems Center University of Maryland College

More information

STUDY OF IMMERSION GOLD PROCESSES THAT MAY BE USED FOR BOTH ENIG AND ENEPIG

STUDY OF IMMERSION GOLD PROCESSES THAT MAY BE USED FOR BOTH ENIG AND ENEPIG As originally published in the SMTA Proceedings STUDY OF IMMERSION GOLD PROCESSES THAT MAY BE USED FOR BOTH ENIG AND ENEPIG Don Gudeczauskas, Albin Gruenwald and George Milad UIC Technical Center Southington,

More information

Rockwell R RF to IF Down Converter

Rockwell R RF to IF Down Converter Construction Analysis Rockwell R6732-13 RF to IF Down Converter Report Number: SCA 9709-552 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Evaluation of Pb-free BGA Solder Joint Reliability on Ni-based Surface Finishes using Alternative Shear and Pull Metrologies

Evaluation of Pb-free BGA Solder Joint Reliability on Ni-based Surface Finishes using Alternative Shear and Pull Metrologies Evaluation of Pb-free BGA Solder Joint Reliability on Ni-based Surface Finishes using Alternative Shear and Pull Metrologies Kuldip Johal and Hugh Roberts Atotech USA Inc., Rock Hill, SC Sven Lamprecht,

More information

Dallas Semicoductor DS80C320 Microcontroller

Dallas Semicoductor DS80C320 Microcontroller Construction Analysis Dallas Semicoductor DS80C320 Microcontroller Report Number: SCA 9702-525 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:

More information

Evaluation of Cantilever Probe-Induced Dielectric Cracks in Cu/Low-k Devices

Evaluation of Cantilever Probe-Induced Dielectric Cracks in Cu/Low-k Devices Evaluation of Cantilever Probe-Induced Dielectric Cracks in Cu/Low-k Devices C.D. Hartfield, D. Stillman, J. Aronoff Texas Instruments, Dallas, TX SouthWest Test Workshop - 2004 Outline Objectives Background

More information

Wafer probe challenges for the automotive market Luc Van Cauwenberghe

Wafer probe challenges for the automotive market Luc Van Cauwenberghe Wafer probe challenges for the automotive market Luc Van Cauwenberghe ON Semiconductor Overview Automotive wafer probe requirements Results of experiments Summary Follow on Work Acknowledgements 2 Automotive

More information

Future Electronic Devices Technology in Cosmic Space and Electroless Ni/Pd/Au Plating for High Density Semiconductor Package Substrate

Future Electronic Devices Technology in Cosmic Space and Electroless Ni/Pd/Au Plating for High Density Semiconductor Package Substrate JAXA 25 rd Microelectronics Workshop Future Electronic Devices Technology in Cosmic Space and Electroless Ni/Pd/Au Plating for High Density Semiconductor Package Substrate November 2, 2012 Yoshinori Ejiri

More information

Analog Devices ADSP KS-160 SHARC Digital Signal Processor

Analog Devices ADSP KS-160 SHARC Digital Signal Processor Construction Analysis Analog Devices ADSP-21062-KS-160 SHARC Digital Signal Processor Report Number: SCA 9712-575 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,

More information

Oki M A-60J 16Mbit DRAM (EDO)

Oki M A-60J 16Mbit DRAM (EDO) Construction Analysis Oki M5117805A-60J 16Mbit DRAM (EDO) Report Number: SCA 9707-545 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes. Daniel Stillman, Daniel Fresquez Texas Instruments Inc.

Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes. Daniel Stillman, Daniel Fresquez Texas Instruments Inc. Interlayer Dielectric (ILD) Cracking Mechanisms and their Effects on Probe Processes Daniel Stillman, Daniel Fresquez Texas Instruments Inc. Outline Probe Optimization Why is it needed? Objective and obstacles

More information

UMC UM F-7 2M-Bit SRAM

UMC UM F-7 2M-Bit SRAM Construction Analysis UMC UM 613264F-7 2M-Bit SRAM Report Number: SCA 9609-511 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

VTC VM365830VSJ Pre-Amp

VTC VM365830VSJ Pre-Amp Construction Analysis VTC VM365830VSJ Pre-Amp Report Number: SCA 9708-549 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781

More information

Motorola MPA1016FN FPGA

Motorola MPA1016FN FPGA Construction Analysis Motorola MPA1016FN FPGA Report Number: SCA 9711-561 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781

More information

The Emergence of High Volume Copper Ball Bonding

The Emergence of High Volume Copper Ball Bonding The Emergence of High Volume Copper Ball Bonding Michael Deley, Director, Ball Bonder Marketing Phone 215-784-6738, Fax 215-784-7588, mdeley@kns.com Lee Levine, Sr. MTS, Advanced Packaging Phone 215-784-636,

More information

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Revision 0 2006 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the

More information

National Semiconductor LM2672 Simple Switcher Voltage Regulator

National Semiconductor LM2672 Simple Switcher Voltage Regulator Construction Analysis National Semiconductor LM2672 Simple Switcher Voltage Regulator Report Number: SCA 9712-570 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,

More information

Figure 1 Copper vs Gold Wire Savings

Figure 1 Copper vs Gold Wire Savings An Update on High Volume Copper Ball Bonding By Lee Levine, Sr. MTS, Advanced Packaging Phone 215-784-6036, Fax 215-659-7588, llevine@kns.com And Michael Deley, Director, Ball Bonder Marketing Phone 215-784-6738,

More information

Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM

Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM Construction Analysis Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM Report Number: SCA 9703-499 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong

More information

MATERIAL NEEDS AND RELIABILITY CHALLENGES IN AUTOMOTIVE PACKAGING UNDER HARSH CONDITIONS

MATERIAL NEEDS AND RELIABILITY CHALLENGES IN AUTOMOTIVE PACKAGING UNDER HARSH CONDITIONS MATERIAL NEEDS AND RELIABILITY CHALLENGES IN AUTOMOTIVE PACKAGING UNDER HARSH CONDITIONS Varughese Mathew NXP Semiconductors 6501 William Cannon Drive, Austin TX, USA Automotive Innovation Driven by Electronics

More information

SGS-Thomson M28C K EEPROM

SGS-Thomson M28C K EEPROM Construction Analysis SGS-Thomson M28C64-121 64K EEPROM Report Number: SCA 9710-559 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

3D-WLCSP Package Technology: Processing and Reliability Characterization

3D-WLCSP Package Technology: Processing and Reliability Characterization 3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc. 2012 1 Outline Packaging

More information

Enhancing Fine Pitch, High I/O Devices with Copper Ball Bonding

Enhancing Fine Pitch, High I/O Devices with Copper Ball Bonding Enhancing Fine Pitch, High I/O Devices with Copper Ball Bonding Inderjit Singh, Sr. Assembly/Packaging Engineer Phone 48-486-8194, Fax 48-486-8694, isingh@nvidia.com nvidia Corporation 271 San Tomas Expressway

More information

Micron Semiconductor MT4LC16M4H9 64Mbit DRAM

Micron Semiconductor MT4LC16M4H9 64Mbit DRAM Construction Analysis Micron Semiconductor MT4LC16M4H9 64Mbit DRAM Report Number: SCA 9705-539 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:

More information

Interfacial Reactions of Ni-doped SAC105 and SAC405 Solders on Ni-Au Finish during Multiple Reflows

Interfacial Reactions of Ni-doped SAC105 and SAC405 Solders on Ni-Au Finish during Multiple Reflows Interfacial Reactions of Ni-doped SAC105 and Solders on Ni-Au Finish during Multiple Reflows Toh C.H. 1, Liu Hao 1, Tu C.T 2., Chen T.D. 2, and Jessica Yeo 1 1 United Test and Assembly Center Ltd, 5 Serangoon

More information

QFN Challenges: Second Bond Improvement to Eliminate the Weak Stitch (Fish Tail) Failure Mechanism on Pre Plated Lead Frame

QFN Challenges: Second Bond Improvement to Eliminate the Weak Stitch (Fish Tail) Failure Mechanism on Pre Plated Lead Frame QFN Challenges: Second Bond Improvement to Eliminate the Weak Stitch (Fish Tail) Failure Mechanism on Pre Plated Lead Frame Jacky Lee Sinn Fah, Sreetharan Sekaran, Rameish Rao Subarmaniyan Central Process

More information

Wire Bonding Integrity Assessment for Combined Extreme Environments

Wire Bonding Integrity Assessment for Combined Extreme Environments Wire Bonding Integrity Assessment for Combined Extreme Environments Maria Mirgkizoudi¹, Changqing Liu¹, Paul Conway¹, Steve Riches² ¹Wolfson School of Mechanical and Manufacturing Engineering, Loughborough

More information

Maximum MAX662 12V DC-DC Converter

Maximum MAX662 12V DC-DC Converter Construction Analysis Maximum MAX662 12V DC-DC Converter Report Number: SCA 9512-445 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

A STUDY OF THE ENEPIG IMC FOR EUTECTIC AND LF SOLDERS

A STUDY OF THE ENEPIG IMC FOR EUTECTIC AND LF SOLDERS A STUDY OF THE ENEPIG IMC FOR EUTECTIC AND LF SOLDERS G.Milad, D.Gudeczauskas, G.Obrien, A.Gruenwald Uyemura International Corporation Southington, CT ABSTRACT: The solder joint formed on an ENEPIG surface

More information

NSOP REDUCTION FOR QFN RFIC PACKAGES

NSOP REDUCTION FOR QFN RFIC PACKAGES As originally published in the SMTA Proceedings NSOP REDUCTION FOR QFN RFIC PACKAGES Mumtaz Y. Bora Peregrine Semiconductor San Diego, CA, USA mbora@psemi.com ABSTRACT Wire bonded packages using conventional

More information

Properties and Barrier Material Interactions of Electroless Copper used for Seed Enhancement

Properties and Barrier Material Interactions of Electroless Copper used for Seed Enhancement Mat. Res. Soc. Symp. Proc. Vol. 766 2003 Materials Research Society E1.4.1 Properties and Barrier Material Interactions of Electroless Copper used for Seed Enhancement C. Witt a,b,k.pfeifer a,c a International

More information

Overpad Metallizations and Probe Challenges

Overpad Metallizations and Probe Challenges Terence Q. Collier CVInc Overpad Metallizations and Probe Challenges June 6 to 9, 2010 San Diego, CA USA Why Packaging stuff at Probe Conference More and more wafers with ENIG finish Reliability data applicable

More information

Supplementary Materials for

Supplementary Materials for www.sciencemag.org/cgi/content/full/336/6084/1007/dc1 Supplementary Materials for Unidirectional Growth of Microbumps on (111)-Oriented and Nanotwinned Copper Hsiang-Yao Hsiao, Chien-Min Liu, Han-wen Lin,

More information

1.1 Background Cu Dual Damascene Process and Cu-CMP

1.1 Background Cu Dual Damascene Process and Cu-CMP Chapter I Introduction 1.1 Background 1.1.1 Cu Dual Damascene Process and Cu-CMP In semiconductor manufacturing, we always directed toward adding device speed and circuit function. Traditionally, we focused

More information

Choosing the Correct Capillary Design for Fine Pitch, BGA Bonding

Choosing the Correct Capillary Design for Fine Pitch, BGA Bonding Choosing the Correct Capillary Design for Fine Pitch, BGA Bonding Lee Levine, Principal Engineer phone 215-784-6036, fax 215-784-6402, email: llevine@kns.com and Michael J. Sheaffer, Director Technical

More information

The Shift to Copper Wire Bonding

The Shift to Copper Wire Bonding The Shift to Copper Wire Bonding E. Jan Vardaman President TechSearch International, Inc. www.techsearchinc.com 1/3/06 3/4/06 5/3/06 7/2/06 8/31/06 10/30/06 12/29/06 2/27/07 4/28/07 6/27/07 8/26/07 10/25/07

More information

28nm Mobile SoC Copper Pillar Probing Study. Jose Horas (Intel Mobile Communications) Amy Leong (MicroProbe) Darko Hulic (Nikad)

28nm Mobile SoC Copper Pillar Probing Study. Jose Horas (Intel Mobile Communications) Amy Leong (MicroProbe) Darko Hulic (Nikad) 28nm Mobile SoC Copper Pillar Probing Study Jose Horas (Intel Mobile Communications) Amy Leong (MicroProbe) Darko Hulic (Nikad) Overview Introduction to IMC Copper Pillar Implementation at IMC Low force

More information

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to Supporting Information: Substrate preparation and SLG growth: All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to aid in visual inspection of the graphene samples. Prior

More information

MTS Semiconductor Solution

MTS Semiconductor Solution MTS 0 unplanned down time Solution Lowest operating Cost Solution Energy saving Solution Equipment Fine Pitch and UPH Upgrade solution Quality & Yield Improvement Solution Reliability Enhancement Solution

More information

Reflow Profiling: Time a bove Liquidus

Reflow Profiling: Time a bove Liquidus Reflow Profiling: Time a bove Liquidus AIM/David Suraski Despite much research and discussion on the subject of reflow profiling, many questions and a good deal of confusion still exist. What is clear

More information

Study of Foil Resistors Under Exposure to High-Temperature, Moisture, and Humidity

Study of Foil Resistors Under Exposure to High-Temperature, Moisture, and Humidity Manufacturers of the Most Precise and Stable Resistors Available Technical Note 11 By Reuven Goldstein, Dr. Gady I. Rosen, and Jacob Musel Vishay Foil Resistors Abstract An often overlooked reliability

More information

Using Argon Plasma to Remove Fluorine, Organic and Metal Oxide Contamination for Improved Wire Bonding Performance

Using Argon Plasma to Remove Fluorine, Organic and Metal Oxide Contamination for Improved Wire Bonding Performance Using Argon Plasma to Remove Fluorine, Organic and Metal Oxide Contamination for Improved Wire Bonding Performance Scott D. Szymanski March Plasma Systems Concord, California, U.S.A. sszymanski@marchplasma.com

More information

By Ron Blankenhorn, Pac Tech USA, Santa Clara, Calif., and Thomas Oppert, Pac Tech GbmH, Nauen, Germany

By Ron Blankenhorn, Pac Tech USA, Santa Clara, Calif., and Thomas Oppert, Pac Tech GbmH, Nauen, Germany INTRODUCTION Modern microelectronic products require packages that address the driving forces of reduced size and weight, as well as increased performance at high frequencies. Flipchip and direct chip

More information

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics

More information

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Li Zheng, Student Member, IEEE, and Muhannad S. Bakir, Senior Member, IEEE Georgia Institute of Technology Atlanta,

More information

Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM

Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM Construction Analysis Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM Report Number: SCA 9412-394 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone:

More information

Flip Chip - Integrated In A Standard SMT Process

Flip Chip - Integrated In A Standard SMT Process Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical

More information

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM Construction Analysis Hitachi 5165805A 64Mbit (8Mb x 8) Dynamic RAM Report Number: SCA 9712-565 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone:

More information

Lecture 22: Integrated circuit fabrication

Lecture 22: Integrated circuit fabrication Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MASW-007921 2mm 8-Lead Plastic Package QTR-0148 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax: (978)

More information

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding Chapter 4 Fabrication Process of Silicon Carrier and Gold-Gold Thermocompression Bonding 4.1 Introduction As mentioned in chapter 2, the MEMs carrier is designed to integrate the micro-machined inductor

More information

23 rd ASEMEP National Technical Symposium

23 rd ASEMEP National Technical Symposium THE EFFECT OF GLUE BOND LINE THICKNESS (BLT) AND FILLET HEIGHT ON INTERFACE DELAMINATION Raymund Y. Agustin Janet M. Jucar Jefferson S. Talledo Corporate Packaging & Automation/ Q&R STMicroelectronics,

More information

HBLED packaging is becoming one of the new, high

HBLED packaging is becoming one of the new, high Ag plating in HBLED packaging improves reflectivity and lowers costs JONATHAN HARRIS, President, CMC Laboratories, Inc., Tempe, AZ Various types of Ag plating technology along with the advantages and limitations

More information

NSOP Reduction for QFN RFIC Packages

NSOP Reduction for QFN RFIC Packages NSOP Reduction for QFN RFIC Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, CA mbora@psemi.com Abstract Wire bonded packages using conventional copper leadframe have been used in industry for

More information

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam PHYS 534 (Fall 2008) Process Integration Srikar Vengallatore, McGill University 1 OUTLINE Examples of PROCESS FLOW SEQUENCES >Semiconductor diode >Surface-Micromachined Beam Critical Issues in Process

More information

SGS-Thomson L4990 Controller

SGS-Thomson L4990 Controller Construction Analysis SGS-Thomson L4990 Controller Report Number: SCA 9710-560 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION. Universiti Kebangsaan Malaysia UKM Bangi,Selangor, Malaysia

CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION. Universiti Kebangsaan Malaysia UKM Bangi,Selangor, Malaysia CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION W. Shualdi 1, W. M. S. W. Suliman 1, A. Isnin 2 and N. A. Mohamad 2 1 Advanced Semiconductor Packaging (ASPAC) Research Laboratory Universiti

More information

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps Materials Transactions, Vol. 52, No. 11 (2011) pp. 2106 to 2110 #2011 The Japan Institute of Metals The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu

More information

Intlvac Nanochrome I Sputter System (intlvac_sputter)

Intlvac Nanochrome I Sputter System (intlvac_sputter) 1. Intlvac_Sputter Specifications The Intlvac Nanochrome I sputter system is configured for DC, AC (40 khz), and RF (13.56 MHz) magnetron sputtering. They system has in-situ quartz lamp heating up to 200C,

More information

Motorola PC603R Microprocessor

Motorola PC603R Microprocessor Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

FINAL PRODUCT/PROCESS CHANGE NOTIFICATION Generic Copy. 11-Apr SUBJECT: ON Semiconductor Final Product/Process Change Notification #15507

FINAL PRODUCT/PROCESS CHANGE NOTIFICATION Generic Copy. 11-Apr SUBJECT: ON Semiconductor Final Product/Process Change Notification #15507 FINAL PRODUCT/PROCESS CHANGE NOTIFICATION Generic Copy 11-Apr-26 SUBJECT: ON Semiconductor Final Product/Process Change Notification #1557 TITLE: Qualification of OSPI for Assembly/Test of 8/14/16 Lead

More information

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA)

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Seung Wook Yoon, Yaojian Lin and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 E-mail

More information

DEC SA-110S StrongARM 32-Bit Microprocessor

DEC SA-110S StrongARM 32-Bit Microprocessor Construction Analysis DEC SA-110S StrongARM 32-Bit Microprocessor Report Number: SCA 9704-535 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:

More information

Predicting the Reliability of Zero-Level TSVs

Predicting the Reliability of Zero-Level TSVs Predicting the Reliability of Zero-Level TSVs Greg Caswell and Craig Hillman DfR Solutions 5110 Roanoke Place, Suite 101 College Park, MD 20740 gcaswell@dfrsolutions.com 443-834-9284 Through Silicon Vias

More information

Australian Journal of Basic and Applied Sciences. Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test

Australian Journal of Basic and Applied Sciences. Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test AENSI Journals Australian Journal of Basic and Applied Sciences ISSN:1991-8178 Journal home page: www.ajbasweb.com Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test 1,2 Tan Cai

More information

Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar,,, and SnPb Bump Structures Ahmer Syed, Karthikeyan Dhandapani, Lou Nicholls, Robert Moody, CJ Berry, and Robert Darveaux Amkor Technology

More information

OUR SPECIALTY OUR SCOPE. We specialize in the design and manufacture of thick-film hybrid microcircuits and custom packagings.

OUR SPECIALTY OUR SCOPE. We specialize in the design and manufacture of thick-film hybrid microcircuits and custom packagings. OUR SPECIALTY We specialize in the design and manufacture of thick-film hybrid microcircuits and custom packagings. OUR SCOPE We serve the global market, catering to the specific needs of a broad range

More information

Abstract. Key words. I. Introduction

Abstract. Key words. I. Introduction Increased High-Temperature Reliability and Package Hardening of Commercial Integrated Circuits (Through Die Extraction, Electroless Nickel/Gold Pad Reconditioning, and Ceramic Re-Assembly) Erick M. Spory

More information

CX Thin Fil s. Resistors Attenuators Thin-Film Products Thin-Film Services. ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant

CX Thin Fil s. Resistors Attenuators Thin-Film Products Thin-Film Services.   ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant CX Thin Fil s Resistors Attenuators Thin-Film Products Thin-Film Services www.cxthinfilms.com ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant www.cxthinfilms.com sales@cxthinfilms.com +1 (401) 461-5500

More information

A 600 Degrees C Wireless Multimorph-Based Capacitive MEMS Temperature Sensor for Component Health Monitoring

A 600 Degrees C Wireless Multimorph-Based Capacitive MEMS Temperature Sensor for Component Health Monitoring Purdue University Purdue e-pubs Birck and NCN Publications Birck Nanotechnology Center 1-29-2012 A 600 Degrees C Wireless Multimorph-Based Capacitive MEMS Temperature Sensor for Component Health Monitoring

More information

Development of a Fluxless Flip Chip Bonding Process for Optical Military Electronics

Development of a Fluxless Flip Chip Bonding Process for Optical Military Electronics Development of a Fluxless Flip Chip Bonding Process for Optical Military Electronics Michael Girardi, Daric Laughlin, Philip Abel, Steve Goldammer, John Smoot NNSA s Kansas City Plant managed by Honeywell

More information

PRODUCT/PROCESS CHANGE NOTICE (PCN)

PRODUCT/PROCESS CHANGE NOTICE (PCN) 3545 North First Street San Jose, CA 95134 USA PRODUCT/PROCESS CHANGE NOTICE (PCN) PCN Number: 06-07 Date Issued: December 13, 2006 Product(s) Affected: Products using TQFN/TDFN type packages Manufacturing

More information

Fabrication of Smart Card using UV Curable Anisotropic Conductive Adhesive (ACA) Part II: Reliability Performance of the ACA Joints

Fabrication of Smart Card using UV Curable Anisotropic Conductive Adhesive (ACA) Part II: Reliability Performance of the ACA Joints Fabrication of Smart Card using UV Curable Anisotropic Conductive Adhesive (ACA) Part II: Reliability Performance of the ACA Joints C. W. Tan, Y M Siu, K. K. Lee, *Y. C. Chan & L. M. Cheng Department of

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

Solder Joint Reliability Study for Plastic Ball Grid Array Packages

Solder Joint Reliability Study for Plastic Ball Grid Array Packages Intl. Journal of Microcircuits and Electronic Packaging Solder Joint Reliability Study for Plastic Ball Grid Array Packages L. Y. Yang and Y. C. Mui Advanced Packaging Advanced Micro Devices (AMD) 512

More information

Intel Pentium Processor W/MMX

Intel Pentium Processor W/MMX Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

Wire Bond / Ball Shear Application Note

Wire Bond / Ball Shear Application Note Wire Bond / Ball Shear Application Note P. 1 What is wirebonding Wirebonding is an electrical interconnection technique using thin wire and a combination of heat, pressure and/or ultrasonic energy. Wire

More information

Bare Die Assembly on Silicon Interposer at Room Temperature

Bare Die Assembly on Silicon Interposer at Room Temperature Minapad 2014, May 21 22th, Grenoble; France Bare Die Assembly on Silicon Interposer at Room Temperature W. Ben Naceur, F. Marion, F. Berger, A. Gueugnot, D. Henry CEA LETI, MINATEC 17, rue des Martyrs

More information

Effect of Reflow Profile (RSP Vs RTP) on Sn/Ag/Cu Solder Joint Strength in Electronic Packaging

Effect of Reflow Profile (RSP Vs RTP) on Sn/Ag/Cu Solder Joint Strength in Electronic Packaging ISSN 2231-8798 2012 UniKLBMI Effect of Reflow Profile (RSP Vs RTP) on Sn/Ag/Cu Solder Joint Strength in Electronic Packaging I. Ahmad 1, A. Jalar 2 Z. Kornain 3 & U. Hashim 4 1 Universiti Tenaga Nasional

More information

WorkShop Audace. INSA ROUEN 8 juin 2012

WorkShop Audace. INSA ROUEN 8 juin 2012 WorkShop Audace INSA ROUEN 8 juin 2012 Global Standards for the Microelectronics Industry JEDEC standards for product level qualification Christian Gautier Content JEDEC overview Environmental reliability

More information

Shear Strength in Solder Bump Joints for High Reliability Photodiode Packages

Shear Strength in Solder Bump Joints for High Reliability Photodiode Packages Materials Transactions, Vol. 44, No. 10 (2003) pp. 2163 to 2168 #2003 The Japan Institute of Metals Shear Strength in Solder Bump Joints for High Reliability Photodiode Packages Chong-Hee Yu 1, Kyung-Seob

More information

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes Jason Chou and Sze Pei Lim Indium Corporation Agenda Company introduction Semiconductor assembly roadmap challenges Fine

More information

Customer Process Change Notification Form

Customer Process Change Notification Form Customer Process Change Notification Form PCN-2013-513 Notification Date: 10/1/2013 Part Information Cirrus Logic Part # / Quantity CS42L73-CWZR PCN Effective Date: 1/1/2014 Cirrus P/N Change: Yes No If

More information

Enhancement Mode GaN FETs and ICs Visual Characterization Guide

Enhancement Mode GaN FETs and ICs Visual Characterization Guide Enhancement Mode GaN FETs and ICs Visual Characterization Guide EFFICIENT POWER CONVERSION Alana Nakata, Vice President, Product Engineering, Efficient Power Conversion Corporation A detailed description

More information

Optimizing Immersion Silver Chemistries For Copper

Optimizing Immersion Silver Chemistries For Copper Optimizing Immersion Silver Chemistries For Copper Ms Dagmara Charyk, Mr. Tom Tyson, Mr. Eric Stafstrom, Dr. Ron Morrissey, Technic Inc Cranston RI Abstract: Immersion silver chemistry has been promoted

More information