Underfill Selection for Large Body (50x50mm) Lidded Flip Chip BGA Package with ELK 40nm Pb-free Bumps

Transcription

1 Underfill Selection for Large Body (50x50mm) Lidded Flip Chip BGA Package with ELK 40nm Pb-free Bumps by Peng SUN, Vivian ZHANG, Rocky XU, Tonglong ZHANG STATS ChipPAC (Shanghai) Co., Ltd. 188, Huaxu Road, Qingpu District, Shanghai, PRC. Copyright Reprinted from 2012 Joint Conference of the International Conference on Electronics Packaging and IMAPS All Asia Conference (ICEP-IAAC) Proceedings. The material is posted here by permission of the ICEP-IAAC. Such permission of the ICEP-IAAC does not in any way imply ICEP-IAAC endorsement of any STATS ChipPAC Ltd s products or services. Internal or personal use of this material is permitted, however, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution must be obtained from the ICEP-IAAC. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 Underfill Selection for Large Body (50x50mm) Lidded Flip Chip BGA Package with ELK 40nm Pbfree Bumps Peng SUN, Vivian ZHANG, Rocky XU, Tonglong ZHANG STATS ChipPAC (Shanghai) Co., Ltd. 188, Huaxu Road, Qingpu District, Shanghai, PRC. Abstract Flip chip has become the preferred package solution for high performance IC and microprocessor device [1]. In the area of flip chip, advanced Si node is always the mainstream technology. The integration of highly fragile ELK (Extreme Low K) inner layer dielectric (ILD) material plays an important role to reduce the circuit delay time. In addition, the increasing performance demand continues to drive the scaling of feature size of the silicon as well as tighter bump pitch, smaller bump diameter and large die size for future flip chip packages [2]. From the last decade, there has been a significant focus on the development of Pb-free bump interconnection in flip chip package [3]. The Pb-free bump interconnection leads to significant challenges because the elastic modulus and yield strength of Pb-free alloys are significantly higher than that of conventional eutectic Sn-Pb material, and higher melting temperature is required to meet the Pb-free soldering in chip attach process. As a result, ILD delamination has emerged as a major reliability concern with the adoption of the intrinsically higher stiffness of Pb-free solder and lower mechanical strength of ELK dielectric materials in silicon backend structure. It is a challenge to manufacture a robust and reliable advanced flip chip product [4-6]. In this paper, we summarize some of the early development work of the high performance ASIC. The die size of the test vehicle is approximately 18x19mm fabricated using 40nm ELK technology incorporating Sn-1.8Ag plated bumps whose pitch is 150um (minimum). It is fabricated on 300mm wafer with polyimide passivation. The laminate is a 50x50mm square substrate with 800um core and (12 layers) build-up structure. The Pb-free BGA has 2397 pads with 1.0mm pitch and full array format. It is well known that underfill materials and related processes are key technology for flip chip BGA (FCBGA) packaging. Underfill is an epoxy silica composite material with optimum thermo-mechanical properties (CTE (Coefficient Thermal Expansion), T g, Modulus) to minimize stress transfer to die, then to prevent solder joint fatigue, ELK ILD delamination and die crack. In this study, UF (Underfill) selection is conducted to compare different underfill materials process capability, compatibility and reliability performance in accelerated stress tests. Common failure modes are studied, e.g., ILD delamination besides UF crack and interfacial delamination between polyimide and UF. One underfill option has passed internal qualification test including uhast (Unbiased Highly Accelerated Stress Test) 96hrs, TCB (Temperature Cycling Condition B) 1000 cycles and HTST (High Temperature Storage Test) 1000hrs. 1. Package Description and Assembly Flow The overall test vehicle is a 50x50mm square flip chip BGA package with heat spreader. The lid is a copper plate with Ni plating in one piece of hat type. The lid is attached to the substrate using an epoxy type material and one layer thermal interface material (TIM) with a thermal conductivity of ~3.8 W/m-K. The die is 18x19mm with 150um minimum pitch fabricated using 40nm Si node with ELK dielectric. Passivation on die surface is silicon nitride incorporating polyimide. The bump structure consists of a 90um diameter UBM (Under Bump Metallization) and an electroplated Sn- Ag Pb-free bump. The target bump height after reflow is 80um. Die thickness is 31mils. The laminate substrate is 800um core with build up structure. The finial thickness of substrate is 1.4mm. The substrate is solder mask defined pad structure with 90um solder resist opening (SRO). The flip chip assembly process flow is shown in Figure 1. Figure 1. Abbreviated Assembly Process Flow 2. Finite Element Analysis

3 In this study, finite element (FE) modeling is performed firstly to investigate the stress distributed in bump & ILD structure when the package is cooled down from UF cure temperature 150 o C. The element mode with local finite element mesh of bump interconnection is shown in Figure 2. The fine mesh is used to construct the fine structure of UBM, Al pad, polyimide passivation, SiO x /SiN x passivation and ELK layer in die level. The assumption in FE modeling is listed, 1) A simplified model is used to check ELK & bump stress. The symmetry boundary conditions assigned for the model is shown in Figure 2(a). 2) The uniform thermal loading condition is set from underfill cure temperature (150 o C) to the room temperature (25 o C). The package is assumed to be stress free at 150 o C. 3) Chemical shrinkage is not considered for all materials at the respective stress-free temperature. 4) The temperature change is assumed to be uniform throughout the package. And the perfect adhesion is assumed at all material interfaces. Table 1. UF material properties provided by the suppliers K1c T g E Cure Underfill CTE 1 MPa* (TMA) Material m1/2 ppm/ o (<T C g ) shrinkage C GPa (Vol%) A N/A B N/A C N/A D N/A E N/A Figure 3 shows principle positive stress (S1) and von Mises equivalent stress (S EQV ) distribution in the bump after cooling down from stress free temperature 150 o C to room temperature. It is seen that tensile stress concentrates on the interface of UBM and solder, especially on the opening of polyimide layer. While equivalent stress is high at SOP (solder on pad) side, bump crack initiates frequently, as shown in Figure 4. (a) (b) Figure 3. (a) Principle positive stress (S1) and (b) The von Mises stress (Equivalent, S EQV ) distribution in bump Figure 2A. Simplified model & boundary conditions Figure 4. Bump crack at SOP side after TCC 500 cycles Figure 2B. Local finite element mesh Table 1 listed the selected material properties of underfill options provided by the suppliers. Underfill T g of all options is in the range of 90 o C to 120 o C and their modulus at room temperature is lower than 12GPa due to potential poor performance of higher modulus underfill in protecting ELK dielectric layer from cracking. Table 2. Stress in bump and ILD layer from FE modeling UF Bump ELK Bottom Layer S1 S EQV S1 S EQV A B C D E Based on the FE simulation plan, the stress in bump and ILD structure is evaluated and the result is shown in Table 2. As seen, the combination of high T g and low modulus will

4 reduce package stress significantly. Linear materials properties are used in FE modeling, where kinematic hardening, creeping and plasticity behavior of material weren t involved, therefore, FE modeling result may not be accurate to indicate a real stress with metal fatigue. 3. Assembly Process Development Laser groove and mechanical saw on wafer with ELK ILD Laser groove is applied because device with ELK ILD trend to crack or chip during mechanical blade dicing. Compared to SiO x dielectric which is used in older silicon technology, ELK ILD has brittle nature and poor adhesion properties. In actually, laser groove process is required in 45nm or below Si node. The cross section image of Figure 7 illustrates an example of filler segregation phenomenon of two underfill materials with different filler size. The settling results in filler concentration at substrate side and resin enrichment at the die interface. Although non-homogeneous filler distribution along the Z direction will change properties, e.g., modulus, CTE and adhesion, the real impact on package reliability is still not fully understood [7]. A small amount of phase separation will not significantly affect reliability. One solution is to gel the underfill material after underfill dispensing. (a) UF A Figure 5. Die saw quality of ELK wafer Underfill process development The underfill flow is characterized using live die by C- SAM inspection. For each underfill options, dispensing parameters and cure condition need to be adjusted to cater for different material property. Generally speaking, all underfill candidates demonstrate good flowability without local undulation in front shape, although there is difference in their flow time to fill the gap. It s interesting to find that underfill A with maximum 10um filler size exhibited the fastest flow among 5 opinions. Among them, 3 out of 5 underfill materials are fine filler type. Underfill E, which is also composite with maximum 10um filler showed the second fastest flow. It seems that filler size couldn t explain all the poor and good flowability. (b) UF B Figure 7. SEM images of filler segregation in two underfills. Package warpage behavior The contribution of UF material on package warpage is evaluated in this work. A key challenge for large body size Pb-free fcbga is to meet the tight coplanarity target of 8mils at room temperature and 3mils at reflow peak with Cpk (Complex Process Capability index) 1.67 respectively. According to vision measurement data of two UFs, current package structure design still has process margin to achieve 8mils target when package assembly was done. (a) (b) Figure 6. Underfill flow showing straight front shape without local undulation. (a) A o C/15secs and (b) E o C/15secs. Oneway Analysis of Package Coplanarity By Underfill material 140 Package Coplanarity (um) A Underfill material B All Pairs Tukey-Kramer 0.05 Underfill material A B

5 Means for Oneway Anova Level A B Number Mean Std Error Lower 95% Std Error uses a pooled estimate of error variance Upper 95% Figure 8. Package coplanarity at room temperature by UF materials 4. Reliability Performance Three types of reliability tests are carried out. All parts are subjected to MSL3 (Moisture Sensitivity Level 3) preconditioning test first and are followed by uhast (130 o C/85%RH/96hrs), TSC (Thermal Shock Condition C, - 55 o C to 125 o C, 10mins/cycle) and TCC (Temperature Cycling Condition C, -65 o C to 150 o C, 30mins/cycle) respectively. Because TCC test condition is harsher than standard qualification condition TCB (-55 o C to 125 o C, 30mins/cycle) of flip chip package, it is employed to compare different materials performance in accelerated mode. After reliability, heat spreaders are removed. Parts are inspected by C-SAM (C-Mode Scanning Acoustic Microscope) to verify delamination as a result of stress. TC is extended up to 1000 cycles because no delamination is found in all legs after TCC 500 cycles. Reliability results are summarized in Table 3. When crack propagates through path 3, it may extend into die level BEOL structure resulting in ILD fracture or penetrate into interfaces, e.g., polyimide and SiN x passivation or underfill and PI interface. The underfill to sidewall delamination hypothesis had been studied, but the mechanism is not rigorously known [6, 8]. (a) C-SAM (b) Optical photo Table 3. Reliability screening results of underfill options Underfill MSL3 uhast TSC TCC TCC 96hrs 500x 500x 1000x A 0/32 0/10 0/10 0/12 0/12 B 0/32 0/10 1/10 0/12 11/12 C 0/32 1/10 5/10 0/12 11/12 D 0/32 0/10 0/10 0/12 3/12 E 0/32 0/10 2/10 0/12 3/12 Referring to Table 3, test vehicle assembled with underfill A survives preconditioning and all reliability tests. It is a potential candidate for next step Pb-free underfill qualification. At the same time, underfill crack and delamination are observed in underfill materials B to E in extended TCC test until 1000 cycles. An example of C-SAM image and the corresponding underfill fillet crack at die corner are shown in Figure 9 (a) and (b). Underfill material crack is a reliability issue and the worst location for fillet cracking is at a die corner, where is the highest stress point [8]. Corner crack can propagate to the substrate to break copper trace, or they can spread underneath the die resulting in PI delamination and bump crack. Figure 9 (c) and (d) are SEM images for the sample with fillet crack at corner, which show underfill material bulk crack, delamination on the die/underfill interface and fracture between polyimide and SiN x passivation. In terms of failure modes observed in FA (Failure Analysis), fracture/delamination interfaces are described in Figure 10. 1) Internal crack in underfill bulk material; 2) Delamination on chip sidewall; 3) Delamination between underfill and die passivation; (c) Corner delam. & crack (d) Crack in die Figure 9. FA of an example assembled with underfill B after TCC1000x Figure 10. Underfill crack paths In terms of the finding in accelerated TCC test, underfill material A and B are selected for internal qualification. Parts are sent for MSL4 preconditioning and subsequently subjected to uhast and TC tests. HTST is done without preconditioning. UF C-SAM inspection is done after reliability tests. Table 4 shows the reliability stress result with 40nm live TV (Test Vehicle). Capillary underfill B fails TCB1000 cycles due to delamination issue observed by C- SAM. It is confirmed as interfacial delamination between underfill and polyimide passivation, shown in Figure 11. Since the filler distribution is fine in separation area, the failure may be concluded that adhesion with polyimide is poor. Table 4. Summary of internal qualification test Underfill MSL4 uhast TCB HTS 96hrs 1000x 150 o C/1000hrs A 0/66 0/26 0/40 0/16 B 0/66 0/26 1/40 0/16

6 Figure 11. Cross section image of underfill B confirming the delamination between underfill and die passivation PI layer. Figure 12 is cross section view of bumps after TCB 1000 cycles and HTS 1000 hours. No fracture in bump is detected, while partial crack and Kirkendall voids are observed in parts after TC and HTS test. These voids are formed in the boundary between Cu 6 Sn 5 and Cu 3 Sn intermetallic at SOP side on Cu pad after long time aging. (a) After TCB 1000cycles (b) After HTS 1000hrs Figure 12. Cross section views of bumps after reliability tests. Conclusions In this study, we present the development work of Pb-free flip chip package with 40nm large die. Underfill material A has passed internal qualification including uhast 96hrs, TCB 1000 cycles and HTST 1000hrs. Compared to underfill A, lower Modulus underfill B exhibits less package warpage, but it fails in TCB test due to delamination between underfill and polyimide passivation. For next generation flip chip package with advanced Si node and Pb-free first level interconnect, it becomes more challenging to build up a robust process window and reliability. Acknowledgments The authors would like to acknowledge many colleagues for helpful discussion and support. At STATS Chippac Korea, we acknowledge MyoungSu CHAE for FE simulation analyse work. At STATS Chippac China, we acknowledge Zhenliang WANG, Wei SUN for many discussions on underfill selection. Thanks to Qili Li, Bo CHEN, Bin CANG, Lihui LU, Susan Liu, Paul QU for parts assembly and XueMei WANG, QiuYing GAO, Pei HUANG for help on package reliability test and failure analysis. Last but not least, we want to thank our customers for providing the wafer, substrate and support. References 1. Raj N. Master, Mohammed Khan, Maria Guardado, Orion Starr, Edd Alcid, Flip chip for AMD K6 microprocessor, Proc. Electronic Components and Technology Conference, Tim Chen, Jinlin Wang and Daoqiang Lu, Emerging challenges of underfill for flip chip application, Proc. Electronic Components and Technology Conference, 2004, pp Neha M. Patel, Vijay Wakharkar, Sairam Agrahram, Nitin Deshpande, Mengzhi Pang, Ravindra Tanikella, Rahul Manepalli, Pat Stover, James Jackson, Ravi Mahajan, Prabhat Tiwari, Flip chip packaging technology for enabling 45nm products, Intel Technology Journal, Vol.12, Issue 2, 2008, pp Marie-Claude Paquet, Michael Caynes, Eric Duchesne, David Questad, Luc Belanger and Julien Sylvestre, Underfill selection strategy for Pb-free, ELK and fine pitch organic flip chip applications, Proc. Electronic Components and Technology Conference, 2006, pp Christine Chiu, K. C. Chang, Jones Wang and C. H. Lee, Challenges of thin core substrate flip chip package on advanced Si nodes, Proc. Electronic Components and Technology Conference, 2007, pp Marie-Claude Paquet, Julien Sylvestre, Emmanuelle Gros, Nicolas Boyer, Underfill delamination to chip sidewall in advanced flip chip packages, Proc. Electronic Components and Technology Conference, 2009, pp VijayWakharkar, Chris Matayabas, Ed Lehman, Rahul Manepalli, Mukul Renavikar, Saikumar Jayaraman, Vassou LeBonheur, Material technologies for thermo mechanical management of organic packages, Intel Technology Journal, Vol. 9, Issue 4, 2005, pp IPC J-STD-030, Guideline for selection and application of underfill material for flip chip and other micro packages.