Liquid Interface at Wafer Test

Transcription

1 IBM Microelectronics Liquid Interface at Wafer Test Phil Diesing, David Gardell, David Audette SWTW 2005 P. Diesing 6/4/05

2 Agenda Why liquid thermal interface? Existing thermal problems at module test Thermal roadmap Predicted thermal problems at wafer test Proposed solution Predicted benefit from lower resistance Results of hardware development effort 1 P, Diesing 6/4/05

3 CHIP LEAKAGE HOTSPOTS (microprocessor logic cores) Source [2] 2 P, Diesing 6/4/05

4 THERMAL RUNAWAY Thermal runaway is a positive feedback phenomena in which leakage current and temperature interact in an exponential fashion with each other More Current More Current More Current More Current Higher Temperature Higher Temperature Higher Temperature Higher Temperature Initial IC T J Source [2] 3 P, Diesing 6/4/05

5 THERMAL RUNAWAY View of damaged chip from C4 (solder ball) side Failure analysis photo Source [2] 4 P, Diesing 6/4/05

6 Thermal Problems at Wafer Test Sharply increasing power roadmap Predicts that module test problems will also be seen at wafer test 5 P, Diesing 6/4/05

7 Module Power Trends Module Heat Flux(watts/cm 2 ) Bipolar IBM ES9000 Fujitsu VP2000 IBM 3090S NTT Fujitsu M-780 IBM 3090 Start of Water CDC Cyber 205 IBM 4381 Cooling IBM 3081 Fujitsu M380 Vacuum IBM 360 IBM 370 IBM Year of Announcement IBM RY5 IBM RY6 IBM RY4 IBM RY7 Pulsar Apache CMOS T-Rex Mckinley IBM GP Merced Squadrons Pentium 4 Pentium II(DSIP) Prescott Jayhawk(dual) Source [1] 6 P, Diesing 6/4/05

8 Leakage Current Roadmap High Performance Microprocessor Ampere Technology node (nm) 7 P, Diesing 6/4/05

9 Anticipated Thermal Problems at Wafer Test Problems from high power levels Wafer damage Unknown wafer sort status due to incomplete test (overcurrent shutdown) Incorrect speed sorting due to temperature rise and resulting speed shift Probe card damage 8 P, Diesing 6/4/05

10 Incomplete Wafer Testing High leakage parts may exceed power supply capacity These untested parts are passed on to module test Increased number of defective parts causes higher packaging and test costs 9 P, Diesing 6/4/05

11 Thermal Problems at Wafer Test Incorrect Speed Sorting Due to Temperature Rise Power variations can cause a temperature difference greater than 30 C % Change in speed Max allowable speed change Temperature Rise (C) 10 P, Diesing 6/4/05

12 Probe Card Damage High currents can damage probe cards Expensive to repair or replace Delay in shipping tested wafers (if cards in limited supply) [5] 11 P, Diesing 6/4/05

13 Solution Thermal resistance improvement This provides three benefits: Reduces the temperature rise vs. power Reduces the die to die temperature variation (due to varying power levels) Reduces the effect of across the chuck resistance variation 12 P, Diesing 6/4/05

14 Speed sorting benefit from reduced thermal resistance Larger power variation without sort error Temperature Rise C/W 0.25 C/W Power 10 X 10 mm powered area 13 P, Diesing 6/4/05

15 Assessing the Most Effective Approach to Reduce Thermal Resistance First step is to quantify the contributors to thermal resistance 14 P, Diesing 6/4/05

16 Thermal Resistance Components Wafer to chuck resistance (R0+R1) is largest contributor R0 100% 90% R1 80% R2 R3 R4 70% 60% 50% 40% 77.3% R0+R1 R2 R3+R4+R5 R5 R6 30% 20% 10% 0% 8% 14.7% Rate of thermal 1 resistance Source: Tokyo Electron 15 P, Diesing 6/4/05

17 Improving wafer to chuck dry contact Theoretically, resistance could be improved by increasing chuck and wafer smoothness and flatness However, this resistance would be likely be sensitive to any particles or surface damage Measurements showed that it wasn t possible to match wafer and chuck contours Backside polishing of 300 mm wafers gave only 5 to 10% improvement and added processing cost (Data courtesy of David Audette, IBM) 16 P, Diesing 6/4/05

18 Chuck top Smoothness 1. Overall chuck flatness was 2.9um across more than 300 mm. (High quality surface) 2. However, localized roughness was 1.9 um (Silicon wafer is about 0.35 um) 10mm 2 Maximum Conclusion: it is not practical to make sufficiently smooth matching surfaces (chuck to wafer) Source: Tokyo Electron 1.9um P, Diesing 6/4/05-2

19 Thermal Resistance Options Interface Gas Helium would give some improvement but not enough (approximately 20%) 18 P, Diesing 6/4/05

20 Thermal Resistance Benefit from Wet Interface Main resistance is at interface of wafer to chuck Fluid replaces air in microscopic gaps Note that the heat is not carried away by fluid flow; it is conducted through the fluid into the chuck Thermal uniformity is less sensitive to surface finish or particles, since fluid fills any gaps. 19 P, Diesing 6/4/05

21 Liquid Interface Chuck System Goal : achieve the minimum thermal resistance and maximum thermal uniformity. At least 600 W capability Approach must be consistent with the following guidelines Avoid radical change to the tool Avoid large development costs, and reduce lead time Upgrade must be retrofittable to minimize the cost Minimize additional processing cost Dry or wet mode operation (same prober, with minimal transition time) 200 and 300 mm 20 P, Diesing 6/4/05

22 Concept a) The wafer is pulled tightly onto the dry chuck by vacuum. b) Fluid is supplied under pressure on the supply side and pulled by vacuum at the recovery side. c) The fluid seeps between the supply and recovery sides via the wafer / chuck interface. Wafer Vacuum Fluid Chuck top Source: Tokyo Electron 21 P, Diesing 6/4/05

23 Fluid Under Glass Wafer (Prototype Chuck) Note that the wafer is lifted up on the pins, at which point the fluid is normally completely recovered. Source: Tokyo Electron 22 P, Diesing 6/4/05

24 LTI Testing Results 1,21 3,20 0,17 1,18 4,15-5,15-2,15 1,15 7,15 Thermal resistance (dc/w) ,15 7,15 3,20 1,21 Wet Wet -5,15 1,8-2,15 1,18 4,15 0,17 1,8 Die location 0.13 C/W (Avg) Front Die Location Source: Tokyo Electron 23 P, Diesing 6/4/05

25 Thermal Resistance vs. Die size Experimental data Current chuck *8mm Thermal resistance (dc/w) Dry Chuck 20*20mm Wet Chuck 20*40mm Area (mm2) Source: Tokyo Electron 24 P, Diesing 6/4/05

26 Installed System Circulator for liquid interface with TEL P12XLn and Teradyne J P, Diesing 6/4/05

27 Current Status System meets all specifications Reduces thermal resistance by 50% Uniformity is better by 70 % Maintains performance at 600 W or more Liquid thermal interface system has been installed and has run engineering wafers Wet vs. dry operation is transparent to operators (part of product file) No wafer handling issues 26 P, Diesing 6/4/05

28 Predicted Benefit This chuck will be an essential tool for Preventing thermal runaway Improving speed sorting accuracy Reducing probe card damage 27 P, Diesing 6/4/05

29 ACKNOWLEDGEMENTS This liquid interface system was a joint development project between IBM and Tokyo Electron Principal Contributors IBM: Phil Diesing, David Audette, David Gardell TEL: Yutaka Akaike, Glen Lansman, Shane Pudvah, Yoshinao Kono 28 P, Diesing 6/4/05

30 References: 1. New York Data Center Facilities and Engineering, Conference / Expo Roger Schmidt, IBM 2. IC Power: the Influence and Impact of Semiconductor Technology. Marc Knox, IBM Microelectronics, BiTS Dean Percy, IBM Microelectronics 4. Steven Duda, IBM Microelectronics 29 P, Diesing 6/4/05