The Red Brick Wall of Traditional Semiconductor Electronics

Transcription

1 The Red Brick Wall of Traditional Semiconductor Electronics H. Jörg Osten Institute for Semiconductor Devices and Electronic Materials University of Hannover

2 150 Years of Electronics Edison Effect Lilienfeld Patents Point Contact & Junction Transistors Diode &Triode Vacuum Tubes I.C. MOS Silicon Gate Scaling, Scaling Traditional Equivalent th Century 20th Century 21st Century

3 I think there is a world market for maybe five computers Thomas Watson Senior, Chairman of IBM, 1943

4 The Birth of Microelectronics : The first Ge point contact device showed a current gain of 18 (Bell Laboratories) Current Transfer + Resistor = Transistor

5 Silicon Wafer Today

6 The Intel Family A new processor every 2-3 years! Transistors 10 M 1M 100K 10K Pentium III Pentium Pentium II

7 Electronics, Vol. 38, Nr. 8, April 19, 1965

8 Moore s Law The number of transistors per chip doubles every 18 months

9 CPU MHz Trend 1000 Pentium(R)Pro Processor 100 Pentium(R) Processor MHz 386TM 486TM x per year YEAR

10 DRAM Cost Per Function Price per bit (Millicents) ,1 '65 '70 '75 '80 '85 '90 '

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12 Semiconductor End Markets % 10% 8% PC other Computer 12% 12% 17% Cell phones other Commun. Industrial/Military Automotive Consumer 30% Source: SIA 2003

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14 What is the Best Technology? Simplicity Simplicity Reliability Reliability Needed Needed tools tools & investments Integration Integration in in existing existing processes processes CMOS III/V-Devices Si-Bipolar Si-BiCMOS SiGe-Bipolar SiGe-BiCMOS Needed Needed device device parameter parameter Power consumption Power consumption Maturity Maturity Production cost Production cost Environmental issues issues

15 What is the Best Technology? The best technology depends on desired application As cheap as possible As established as possible Performance only sufficiently high

16 Major Technologies 2003 Global market: $154.9 B Billion $ Products Discrete Optoelectronics Analog MOS µ-processors MOS µ-controllers MOS DSP 4% 6.6% 17% 22% 10% 6.3% 3.6% MOS Logic MOS DRAM Flash EEPROMS 17% 5.4% 8.6% 5.5 others more than 90 % is based on Si more than 80 % is integrated Source: SIA 2003

17 It is revolutionary time... Processor: 30% more components per year, doubling in speed every 1.5 years Memory: 60% more capacity every year Harddisk: 60% more capacity every year Cost per function: 25% lower every year

18 Moore s Law: New Structures 1960 s: Bipolar, Mesa, Metal gate 1970 s: MOS, Poly-gate, LOCOS isolation 1980 s: CMOS, W plugs, salicide process 1990 s: STI isolation, BiCMOS, CMP, multilevel metal, SiGe bipolar 2000 s: Hetero MOS (strained silicon),

19 Moore s Law: New Materials 1960 s: Si, Al, SiO s: Poly-Si, PSG, Al-Si, Si 3 N s: BPSG, WSi 2, Polyimide, SOG, TiN, TiN 1990 s: Al-Cu, W, MoSi 2, SiOF, Cu, SiGe, TiSi 2, CoSi 2, Low-K ILD 2000 s: High-K dielectrics,?

20 CMOS Technology Breakthrough Takes Time Tool or Technology developed In production Silicon epitaxy APCVD silicon nitride Ion implantation TiW metallization Charge-coupled devices (CCD) Reactive ion etch (RIE) Poly-Si emitter Refractory gate SIMOX (SOI via implantation) Trench capacitors Silicide (self-aligned) Lightly-doped drain (LDD)

21 Moore s Law today: New Capabilities Resist, optics, mask (157nm, EUV, ) Chemical-mechanical polishing Deposition of high-k dielectrics Low-K dielectrics (organics) integration Thinner conformal barrier metals Higher thermal conductivity materials Atomic layer conformal deposition

22 Example: Heterojunction Bipolar Transistor (HBT) W As doped emitter XTEM image of a SiGe:C HBTs W Poly SiGe:C/Si STI SiGe:C Emitter window Active region Thin, heteroepitaxial base layer IHP 2001

23 HBT: Boron on Outdiffusion the Key Problem n-emitter (Si) p-base (SiGe) n-collector (Si) Boron doping

24 HBT: Boron on Outdiffusion the Key Problem n-emitter (Si) p-base (SiGe) n-collector (Si) Boron doping

25 Boron Outdiffusion: The Problem Conduction band for heavily p-doped Si and SiGe (schematically) npn-si npn-si/sige/si Parasitic barriers

26 Material Solution: Suppression of Boron Outdiffusion by Carbon BORON SiGe SiGe:C B concentration Annealing B concentration Depth (nm) Depth (nm) SIMS investigations on real devices

27 SUMMARY: Dopant Diffusion in SiGe:C Model of C outdiffusion provides quantitative description Coupled diffusion of C and Si point defects Suppressed B diffusion due to C incorporation Interstitial undersaturation due to C outdiffusion diffusivity reduction of ~20 for < cm -3 C C suppresses also transient enhanced diffusion (TED) during damage annealing Boron and phosphorous diffusion is suppressed by C Interstitial-mediated dopant diffusion Antimony and arsenic diffusion is enhanced by C Vacancy-mediated dopant diffusion

28 SiGe:C Heterojunction Bipolar Transistor - First realization with MBE f T or f max (GHz) f max V CE = 2 V Emitter Area 0.5 x 5 µm² R SBi = 2.3 kω f T Collector Current (A) Ring Oscillator Delay CML-type, FI/FO = 1 25 HBTs, 0.9 x1.3 µm² t d ± σ = (12.9 ± 0.2) ps best value: 12.6 ps Osten et al. IEDM 97 Meanwhile both frequencies are above 200 GHz Si-based analog circuits for mobile communication

29 Modular Integration: BiCMOS for Everybody bipolar step corrected CMOS bipolar modul proce ss step CMOS classical BiCMOS modular BiCMOS

30 Modular Integration of SiGe:C HBTs into CMOS CMOS + HBT = digital BiCMOS IHP module can be integrated into nearly any CMOS process No changes in CMOS flow (modular integration) CMOS libraries can be re-used Adds only 4 additional masks to the process Requires only epi-sige:c CVD as a new step

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32 Prognosis. There is no reason anyone would want a computer in their home Ken Olsen President, Chairman and founder of Digital, 1977

33 The Coming Years ITRS Roadmap Consult the oracle

34 The ITRS Consortium TWG Members by Regions Korea 64 8% Japan USA % 39% 19% Taiwan 161 8% Europe 68 TWG Members by Affiliations Research Inst. / Consortia / Other University 1% % 22% Equipment / Materials Suppliers 185 Chip Makers % Source: 2001 ITRS - Exec. Summary

35 The Plan for Globalization - ITRS Working Groups International Technology Working Groups (ITWG) Design International Crosscut Technology Working Group (ICCT WG) Environment Safety & Health Metrology Defect Reduction Modeling & Simulation Test Front End Processes Interconnect Lithography Process Integration Assembly & Packaging Factory Integration

36 The latest ITRS Roadmap (selected example) Year of Production: DRAM Half-Pitch [nm]: Overlay Accuracy [nm]: MPU Gate Length [nm]: CD Control [nm]: T OX (equivalent) [nm]: Junction Depth [nm]: Metal Cladding [nm]: Inter-Metal Dielectric K: Solution known R&D needed Solution unknown

37 The Red Brick Wall of Microelectronics Year of Production: DRAM Half-Pitch [nm]: Overlay Accuracy [nm]: MPU Gate Length [nm]: CD Control [nm]: T OX (equivalent) [nm]: Junction Depth [nm]: Metal Cladding [nm]: Inter-Metal Dielectric K: Solution known R&D needed Solution unknown

38 Ultrathin Gate oxide: 30 nm Transistor 30 nm FET (Intel)

39 Need for Alternative Gate Dielectrics Production year Technology Node (nm) Gate dielectric (SiO2 equivalent) thickness (Å) Gate bias, V dd (V) Leakage current for Vdd (for max. EOT) (A/cm²) > > > > > > > >

40 Alternatives Needed: thicker gate dielectric BUT: The capacity cannot be changed! C ~ K A / t Solution: Materials with higher dielectric constant (High-K) For a given capacitance, the possible layer thickne ss scale s with K Capacitance scales linearly with thickness Equivalent Oxide Thickne ss: EOT = t * 3.9/K

41 High-K Dielectrics: cs: Requirements Dielectric constant between 15 and 40 Chemical Stability against silicon No tendency for silicide formation No tendency for silicon oxide interfacial layer formation Compatibility with CMOS Process Includes thermal stability Selective etching Important parameter: Interface trap density (D it ) impacts carrier mobility Sufficiently high K and suitable band offsets to Si impacts leakage current (for FET and memory) Epitaxia l?

42 Search for Suitable Binary Oxides H not solid at 1000K He Li Be radioactive B C N O F Ne Na Mg Al Si P S Cl Ar K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe Cs Ba * Lu Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra ** Lr Rf Db Sg Bh Hs Mt * Lanthanoids La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb ** Actinoids Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No

43 Search for Suitable Binary Oxides Si + MO x M+SiO 2 ; MSi z + SiO 2 ; M + MSi x O y H not solid at 1000K He Li Be radioactive B C N O F Ne Na Mg Also not suitable Al Si P S Cl Ar K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe Cs Ba * Lu Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra ** Lr Rf Db Sg Bh Hs Mt * Lanthanoids La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb ** Actinoids Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No

44 Praseodymium Oxide: : Leakage Current 16 Au/Pr 2 O 3 /n-si capacitors 1.9 x 10-3 cm², EOT = 1.4 nm. Leakage current density for different dielectrics with EOT = 1.4 nm. J g (A/cm -2 ) Material J g (A/cm V g = 1V Pr 2 O 3 7*10-9 HfO 2 1*10-4 ZrO 2 5*10-4 SiO 2 ~ 1 SiO 2 (3 nm ) ~ V g (V) Osten et al. IEDM 2000 Lowest reported values for leakage current

45 Pr 2 O 3 Growth on Si(111) epi Si X-HREM of a 6 nm thick, hexagonal Pr 2 O 3 film grown epitaxially on a Si(111) substrate. h-pr 2 O 3 5 nm (111) Si Si overgrowth leads to the formation of epitaxial, (111) oriented silicon. Novel tunneling devices?

46 Epitaxial Growth of Heterolayers

47 Pseudomorphic Growth (Strained Layer) compressive strained SiGe (pseudomorphic) Si substrate

48 Relaxed Layer (Misfit Dislocations) relaxed SiGe mf dislocation Si substrate

49 Virtual Substrate (Strained Si Layer) tensile strained Si Relaxed SiGe Si Substrate

50 Band Gap for Strained SiGe and silicon 1.2 Band Gap (ev) at 90 K Strained SiGe on Si Relaxed SiGe Strained Si on relaxed SiGe Ge Concentration Strain reduces the band gap

51 SiGe Valley Splitting: Conduction Band [001] [010] Strained SiGe on Si [100] Strained Si on relaxed SiGe [001] [010] [001] [010] [100] Unstrained Si 6-fold degenerated [100] Intervalley scattering can be reduced Increase in carrier mobility

52 Strain and Carrier Mobility 2,5 Normalized Mobility 2,0 1,5 NMOS PMOS 1, Ge Concentration (%) of the Substrate Strained Si on relaxed SiGe

53 State-of-the-Art the-art CMOS with silicide 50 nm Gate length Strained Silicon 1.2 nm SiO 2 Nickel silicide 1.2nm SiO 2 Strained Si 1.2 nm INTEL: IEDM Dez. 2002

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55 Scaling will go on

56 Moore s Law The number of transistors per chip doubles every 18 months Execution to Moore s Law is becoming more material dependent Further scaling will reach physical limits

57 Material Complexity is Compounding 50 Number of New Fab Materials Compared to the 0.35 m icron Baseline Revolutionary: Characterized by or resulting in radical change. Evolutionary: A gradual process in which something changes into a different and usually more complex or better form micron 0.18 micron 0.13 micron 0.13 micron (300 mm) Source: INTEL

58 Evolutionary Changes CMP: Composite abrasive slurries SILICON: Double-Sided Polished PHOTORESIST: 193 nm DIELECTRICS: Fluorine- & Carbon-Doped SiO 2 METALS Ta Barrier Salicides Target Assembly

59 Revolutionary Changes LOW K DIELECTRICS Spin-on polymers Porous materials HIGH K GATE DIELECTRICS Metal ox ides Mixed silicates METALS Dual Damascene Copper Advanced Bump Metallurgy instead of bonding Atomic Layer Deposition

60 Revolutionary Changes CHEMICAL-MECHANICAL POLISHING (CMP) Fixed & bonded abrasive pads Abrasive-free slurries SILICON Isotopically-enriched Si (28) Si on Insulator (FD or PD-SOI) PHOTORESIST 157 nm EUV CARRIER: FOUP

61 Power Density Continues to Get Worse P446 P P650 P P854 P P858 P P1262 P Watt/cm 2

62 Future Drivers Logic process technologies are driven by 3 key technology areas: Transistor performance Gate oxide quality, channel mobility, Leakage currents Patterning / etching of nanometer lines Low RC interconnects

63 Lithography: Yesterday, Today, and Tomorrow

64 Bridging the SubWavelength Gap

65 CPU Multi-layer layer Metal Increase Trend # of Metal Layers µ µ µ µ µ µ µ µ µ µ

66 Epi Epi 0.5µm P-WELL ELL P+ Substrate N-WEL L P-WELL ELL N-WEL L

67 RC Delay Assumption: two parallel interconnects will be treated as a capacitor t met t ox C = LW K ox ε 0 /t ox RC ~ ρ met K ox L²/t ox t met R = ρ met L/W t met Only a problem for long interconnects!

68 RC Delay Strategies: RC ~ ρ met K ox L²/t ox t met - lowest possible resistivity - thick interlayer dielectric - thick metal layer Limited by global design issues Interlayer with low K ox (low-k dielectrics, e.a. polymers)

69 Groups of Low-K Materials Reducing dielectric constant k Decreasing polarity 1 Decreasing density 2 Groups of materials Bulk dielectric constant Deposition SiO K CVD Fluorinated oxide low-k CVD Organosilicate glass 1, low-k CVD Organic polymer low-k CVD/SOD Porous organic polymer 1, ultra low-k SOD Porous organic polymer 1, extreme low-k SOD

70 Calculated Delay vs. Technology Generation Delay (ps) Gate Delay Al: 3.0 µωcm Cu + low-k Cu: 1.7 µωcm Al + SiO 2 SiO 2 : κ = 3.9 Total (Cu + low-k) Low K: κ = 2.0 Total (Al + SiO 2 ) Al & Cu: 0.8 µm thick 50 µm long Pitch Size (nm) Interconnect optimized circuit design will be needed

71 Cost of a Chip Factory Second Moore s Law Fab cost doubles every 3 years

72 Worldwide Semiconductor Sales $Billions * 2005* Source: SIA Fall 2002 Forecast * Forecast

73 Intel Toshiba NEC Samsung TI STMicro Motorola Hitachi Infineon Micron Hyundai Philips Mitsubishi Fujitsu TSMC* Lucent AMD IBM Matsushita Sony Sharp UMC* $35 $30 $25 $20 $15 $10 $5 $0 Top 22 Chip Manufacturers 2000 Final 2000 numbers from Dataquest* '98 ($B) '99 ($B) '00 ($B) Source: Dataquest, *TSMC and UMC annual reports the latter don't sell chips into the market

74 The Need for Globalization 90 s 21 st Century Technology Economics manufacturer manufacturer Global Semiconductor Industry

75 Mega Business Trends Cost of Fab, instead of technology breakthrough, impacts global industry food chain size matter; CPU, DRAM alliance Foundry fab (TSMC and others) Migration to Developing Country will accelerate Foundry to Asia (Taiwan, China ) Fabless design to Taiwan, Israel, Russia, India

76 Asia Pacific Leads $Billions 90 Regional Semiconductor Market * 2003* 2004* 2005* Americas Europe Japan Asia Pacific Source: SIA Fall 2002 Forecast *2002 Grow th Rates

77 Growth of the Internet Mill World population TV & Telephone PC 100 Internetter

78 Wireless Internet Wireless (of course!) But much more than wireless access to the net Personal Accessed by personalized, handheld terminals Wearable computers Location aware Information & services you need where you happen to be Context aware You need a ticket at the train station Transaction based

79 Web Tablet

80 Nanoelectronics

81 Other New Concepts (here: Memories)

82 Visions Integration of Opto and Microelectronics on one Chip

83 New Device Concepts Poly Gate Gate Oxide Source Body Drain Silicon Film Body Buried Oxide Substrate Source Gate Drain Source Drain BOX Si fin - Body!

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85 Beyond the classical FET 1) MOSFET 3) CNTFET V S V G V D 2) SBFET 4) Molecular transistors? V G V D V G V S V S V D

86 Scaling will reach physical limits. 10 nm MOSFET Molecule or?

87 Carbon Nanotubes

88 Summary Innovations on all levels are needed for future progress Materials (high-k, low-k, new metals, SOI, ) Device concepts (3D integration, ) IC architectures (interconnect optimized design, ) The classica l microelectronic (CMOS, ) is getting closer to its limits Material limits Technical limits Economical limits (too expensive) Nanoelectronics Devices with small number of electrons Molecular approaches Fabrication by self organization Various quantum effects (spintronic, quantum computing)