The International Technology Roadmap for Semiconductors (ESH THRUST)

Transcription

1 The International Technology Roadmap for Semiconductors (ESH THRUST) 2000 Jim Jewett Intel Corporation

2 The ITRS is a document which identifies technology needs and possible solutions

3 From NTRS to ITRS The SIA NTRS document has been recognized internationally as a useful document Semiconductor Industry has become global Inputs into NTRS limited to the USA companies Broader participation would enrich the data and give better guidance to global suppliers and researchers

4 SIA Roadmap Acceleration Minimum Feature Size (nm) Best Case Opportunity IRC/ITWG Agreement July,1999 MPU Gate DRAM Half Pitch

5 More Aggressive Goal vs. Most Achievable Goal

6 1999 ITRS Provides: Targets for equipment/material and software suppliers Targets for researchers A common reference for the semiconductor industry

7 Presumes That Driving ESH Solution During Technology Development Is The Right Thing To Do.

8 EHS:Technology Engagement Model Here is where we need to operate more often Here is where we operate today Optimal Integration Process-specific environmental impacts unknown Company Research... Process Development Process too close to manufacturing for major change External Research Supplier R&D Equip. Selection Mfg. Ramp Concept Development α β Commercialization Phases Years Integration Demonstration Ramp to High Vol. Mfg.

9 Technology Driven ESH Objectives vs. Regulatory Driven ESH Objectives

10 Semiconductor Technology Environmental "Roadmap" Rev. 0 12/98 Technology Generation 8" / 0.18um 8" / 0.15um 12" / 0.13um 12" / 0.10um 12" / 0.07um 12" / 0.05um Year Increase Product Speed 1. Technical Feature (Technical Decription) - Potential Environmental Impact Area(s) 1. Interconnect (Cu metal) - PFCs, HAPs, Waste, Water, Slurry Use 1. Metal Bumps (Potential Lead ban) - Waste, Water, Energy 1. Metal Bumps (Potential Lead ban) - Waste, Water, Energy 1. Gate Dielectric (Oxynitride/Silicon Nitride) - PFCs, HAPs, VOCs, Energy 1. Gate Dielectric (alternaitve High k dielectric) - PFCs, HAPs, VOCs, Energy Increase Power Dissipation Capablility, Decrease in Power Consumption 2. Technical Feature (Technical Decription) - Potential Environmental Impact Area(s) 2. Gate Electrode (Poly/Silicide Gates) - PFCs, HAPs, VOCs, Energy, Slurry Use 2. Gate Electrode (Metal Gates) - PFCs, HAPs, VOCs, Energy, Waste, Water, Slurry Use 1. Interconnect (Advanced Technology) -??? Increase Product Density/Capacity Decrease Electrical Defect Density 1. Resist Development (193 nm resist)- VOCs, Water 1. Resist Development (Post Optical) - VOCs, Water, Energy 2. Lithography Type (Post Optical) - Energy, VOCs Minimize Signal Loss Increase Wafer Size (300 mm) Decrease Final Cost 1. Low K ILD (SiOF) - PFCs, HAPs 1. Low K ILD (CxFy) - PFCs, HAPs 2. Low K ILD (Spin-on Polymer) - VOCs, PFCs, HAPs, Water, Waste, Slurry Use 1. Drain Extension & Contact Doping (New Process) -??? n/a n/a 1. FOUP (cleaning) - Surfactants 2. Larger Tool Set (consumption) - PFCs, HAPs, VOCs, Water, Waste, Energy 1. Drain Extension & Contact Doping (New Process) -???

11 Five Global Challenges Chemicals, Materials, and Equipment Management Climate Change Mitigation Workplace Protection Resource Conservation ESH Design and Measurement Methods

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13 Factory Int. ESH Crosscut Text &Table Front End Processes ESH Crosscut Text & Table Lithography ESH Crosscut Text & Table Interconnect ESH Crosscut Text & Table Assmbly & Pkg ESH Crosscut Text & Table ESH Roadmap Format Scope & Diff. Challenges Tech Reqmts Interconnect Lithography Potential Sols Front-End Processing Assembly & Packaging Factory Integration Links For additional information to further explain data ESH Technology Requirements ESH Potential Solutions Difficult Challenges Chem, Mtls & Eq Mgmt Interconnect Years/Nodes Chem, Mtls & Eq Mgmt Interconnect Years/Nodes FEP FEP

14 2000/2001 ITRS Preliminary Schedule 2000 ITRS Update Kick off 2000 ITRS Update on Dec 1st, major ITRS meetings: Europe in April, US in July, Japan in December 2001 ITRS December Kick off In Japan Presentation of draft in conjunction with Semicon West December Publication and Presentation

15 Backup Material

16 ESH International Technology Working Group (ITWG) Members Semiconductor Industry Association (SIA) Jim Jewett, Intel Larry Novak, Radian Electronic Industries Association of Japan (EIAJ) Osamu Anzai, Fujitsu Jun-ichi Aoyama, Sony Korea Semiconductor Industry Association (KSIA) C.H. Cho, LG Semicon European Electronic Component Association (EECA) Francesca Illuzzi, STM Leo Klerks, Philips Wolfgang Bloch, Infineon Taiwan Semiconductor Industry Association (TSIA) Eddy Liu, TSMC Jung-Sheng Hsiue, TSMC Abel C.F. Hsu, UMC

17 New Chemicals and Materials Technical Drivers Interconnect Lo-K Copper Advanced metalization Hi-K Lithography Photoresists Thinners Developers Rinses Strippers Front-End Processes Precursors for Hi-K and electrode films Metal-containing precursors Hydride-based dopant precursors Cleaning processes Assembly and Packaging Lead alternatives Flame retardants Solvents

18 1998/99 ITRS Working Groups International Technology Working Groups (ITWG) Design Environment Safety & Health International Crosscut Technology Working Group (ICCT WG) Metrology Defect Reduction Modeling & Simulation Test Front End Processes Interconnect Lithography Process Integration Assembly & Packaging Factory Integration

19 Technology Flow Technology Needs Potential Solutions Consortia Researchers Suppliers Detailed Solutions Implementation Suppliers Manufacturers

20 1999 Technology Nodes and Timing Short Term Years Year of Introduction nm nm nm Dram 1/2 Pitch (nm) MPU Gate Length (nm) Long Term Years Year of Introduction nm nm nm Dram 1/2 Pitch (nm) MPU Gate Length (nm)