Microelectronics Packaging. Microsystems Packaging

Transcription

1 Microelectronics Packaging Microsystems Packaging 1

2 Integration of IC, Packaging and System Packaging Hierarchy 2

3 System Packaging Technologies Summary of Microsystems Packaging 3

4 Moore s Law Evolution of the Microprocessor 4

5 IC Packaging Requirements Protect circuit from external environment Mechanical interface to PCB Interface for production testing Good signal transfer between chip and PCB Good power supply to IC Cooling Through-hole and Surface Mount Packages 5

6 Integrated Circuit Packaging Different applications have different requirements Logic (Microprocessors, ASIC s) High power, I/O count Small number per board (ok if bigger) Relatively high Average Selling Price (ASP) Memory (DRAM, Flash) Lower power and fewer I/O s per die Large number per board IC Package Types 6

7 Traditional IC Package Types Dual-in-line (DIP) 7

8 Quad Flat Pack (QFP) Wire Bond package Leads are coplanar fanning into die - higher coupling New IC Package Types 8

9 Ball Grid Array (BGA) Most popular ASIC package Basically a small printed circuit board Create a 2-D array of pins under the package Multiple planes available in package Possible to route larger numbers of signals Better signal integrity Chip Scale Packages (CSP) Packages is same size as die Very space efficient Very short leads good electrical properties Back side of die exposed good thermal properties Possible to fabricate at wafer level 9

10 New IC Package Types Number of I/Os in a Package N KM p Rent s Rule N: number of pins or terminals K: average number of terminals per logic circuit M: number of circuits/gates P: Rent s constant 10

11 Rent s Constants System or Chip Type P K Static Memory Microprocessor Gate Array High Speed Computer Chip/module level Board / System level Terminals vs Number of Circuits 11

12 I/Os of a Chip For a 64MB Static RAM chip, signal I/Os of this chip is N SRAM 6 ( ) For a gate array chip with 5000 gates, signal I/Os of this chip is N gatearray Packaging Trend 12

13 IC Packaging Efficiency Technology Trend in IC Packaging Source: ERSO/ITRI 13

14 Bottlenecks & Break Through Solutions Source: ERSO/ITRI SHARP s 3-D System in Package 14

15 Multi-chip Module (MCM) Multi-chip Module (Cont.) SP5MX1 Pentium Module (43mm x 43mm) 15

16 Schematic Overview of SP5MX1 Cooling for MCM 16

17 Thermal Conduction Module (TCM) Source: IBM Three Types of MCM MCM-L MCM-C MCM-D 17

18 MCM-L Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63 MCM-C Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63 18

19 MCM-D Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63 Signal and Power Distribution for MCM 19

20 Fabrication of MCM-C Fabrication of MCM-D 20

21 MCM-L Substrate Structure Ni/Au solder resist metal 1 metal 2 core (FR4/5) prepregs metal 3 metal 4 drilled via (buried) micro via Source: Cork Institute of Technology PCB Laminate Materials NEMA Grade FR-2 FR-3 FR-4 FR-5 FR-6 CEM-1 CEM-3 Resin System Phenolic Epoxy Epoxy Epoxy Polyester Epoxy Epoxy Reinforcement Paper Paper Woven glass Woven glass Glass matte Paper and glass Woven glass and glass matte Description Punchable, flame resistant Flame resistant, high insulation resistance Flame resistance, Tg ~ 130C Flame resistant, higher Tg, better thermal Flame resistant, low capacitance or high impact applications Paper core and glass surface, selfextinguishing, excellent punching, longer drill life and minimal dust. Nonwoven glass core and woven glass surface, similar to FR-4, longer drill life 21

22 Comparison of MCM Source: JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 63 Chip Scale Package (CSP) 22

23 System in Package (SIP) Wireless (RF) Market is the Key Driver Motorola, Philips LTCC is the Substrate of Choice CBGA Package SiP is not SOC (System On Chip) System In Package (Cont.) 23

24 Advantages of SIP over SOC RF IC s s Typically Take Manufacturing Passes Total Cost of Up To 5 Million Dollars 66 Month Impact to Schedule SIP on LTCC Total Cost Less Than 500K for Manufacturing Passes 66 Week Impact to Schedule Mixed Technology Support CMOS, GaAs, SiGe all on One Substrate Flexible Design Partitioning Bluetooth Standard Platform LTCC Process 24

25 Applications for LTCC Bonding Methodologies (a) Wire bonding (b) Flip-chip bonding (c) Tape-automated bonding 25

26 Wire Bonding Pads are placed in one or two rows Logic devices Around periphery of die 1 row: 70μ pitch 2 rows: 40-50μ staggered pitch Memory (DRAM) in a line at center of die 1 row: μ pitch Wire Bonding Oldest attachment method and still dominant for ICs Au or Al wires are attached between pads and substrate using Thermocompression bonding Ultrasonic bonding Thermosonic bonding The process is time-consuming since each wire must be attached individually 26

27 Wire Bonding (Cont.) Used in Lead Frame, PGA and BGA Over 80% of Packages are Wirebonded Typically Gold Wire Also Copper, Aluminum Wire length- 1-5 mm Wire diameter µm Inexpensive, Reliable Source: Cadence Thermocompression Bonding (a) Gold wire (15-75 mm diameter) fed from a spool through a capillary (b) Electric spark melts end of wire, forming a ball (c) Ball is positioned over the chip bonding pad, capillary is lowered, and ball deforms into a "nail head" (d) Capillary raised and wire fed from spool and positioned over substrate; bond to package is a wedge produced by deforming the wire with the edge of the capillary (e) Capillary is raised and wire is broken near the edge of the bond 27

28 Ultrasonic Bonding Problems with thermocompression Oxidation of Al makes it difficult to form a good ball Epoxies can t withstand high temperatures Ultrasonic is a lower temperature alternative Relies on pressure and rapid mechanical vibration to form bonds Ultrasonic vibration at khz causes the metal to deform and flow Thermosonic Bonding Combination of thermocompression and ultrasonic Temperature maintained at ~ 150 o C Ultrasonic vibration and pressure used to cause metal to flow to form weld Capable of producing 5-10 bonds/sec 28

29 Pros and Cons of Wire Bonding Pros Cost: cheapest packages use wire bonding Allows ready access to front side of die for probing Cons Relatively high inductance connections Bond wires are 1nH/mm Bond wire length is typically 3-5mm Number of bonds is proportional to square root of die area Not great for distributing large amounts of power Not great for large numbers of I/O s Tape-Automated Bonding Developed in early 1970s ICs first mounted on flexible polymer tape (usually polyimide) with Cu interconnection Cu leads defined by lithography and etching After aligning IC pads to metal interconnection on the tape, attachment occurs by thermocompression Au bumps formed on either side of the die or tape used to bond die to the leads 29

30 Pros and Cons of TAB Process Pros all bonds formed simultaneously, improving throughput Cons Requires solder bumps with complex metallurgy A particular tape can only be used for a chip Flip-Chip Process IC is mounted upside-down onto module or PCB Connections made via solder bumps located over the surface of IC Owing to shorter interconnect lengths, signal inductance is reduced 30

31 Flip-Chip Bonding Chips are placed face down on the substrates so that I/O pads on the chip are aligned with those on the substrates Solder reflow process is used to form all the required connections Drawback: bump fabrication process is fairly complex and capital intensive Solderless flip-chip technology is another alternative; involves stencil printing of organic polymer onto an IC Two Methods of Bumping the Chip RDL- Re-Distribution Layer Direct Bumping (UBM) Source: Cadence 31

32 Solder Bumping Structure Under Bump Metallurgy (UBM) Adhesion layer: Ti, Cr, TiW Wetting layer: Ni, Mo, Cu Protective layer: Au Solder High lead solder: 5Sn/95Pb, 3Sn/97Pb Eutectic solder: 63Sn/37Pb Nonlead solder Under Bump Metallization (UBM) 32

33 Metallization of Solder Bumping Under Bump Metallurgy Evaporation Sputtering Solder Bump Evaporation: High resolution Electro plating Stencil printing: Low cost, High throughput Fabrication of Solder Bump Wafer clean Deposition of BLM P/R coating Etching Solder paste printing Reflow and ball formation 33

34 Solder Bumping Process Source: Advanpack Solutions Pte Ltd Pros and Cons of Flip Chip Pros Large number of connections 1cm x 1cm wire bond 50μ staggered pitch: 800 pads 1cm x 1cm flip 250μ centers: 1600 pads Better power distribution Flip chip: current flows through 20μ thick power plane routing Wire bond: Current flows through 1μ thick top layer metal Cons Cost Debug 34

35 Current Trends for IC Packaging 3D Packaging- Stacked Die Build-Up Substrates Green Manufacturing Removing Lead (Pb) New Materials (tin, silver, copper) for Die Attach, plating, solder balls 3D Packaging- Stacked Die Definition: Packaging technology with 2 or more DIE stacked in a single package or multiple packages stacked together Supports Wirebond Flip chip Hybrid- combination of flip-chip and wirebond Packaging Applications CSP (most common) PBGA, BGA, TSOP, TQFP Benefits of 3D Packaging Smaller, thinner and lighter Packages Reduced packaging costs and components Reduced system level cost for system in package (SiP) and system on chip (SoC) approach System level size reduction due to smaller footprints and decrease component count Common for wireless handsets, handheld electronics and memory intensive requirements 35

36 Increasing Package Density Large memory systems, density is key For portable electronics, space is key Reduce required package size Stack die on top of one another 3-D Packaging 36

37 Amkor 3D Packaging Roadmap Source: Amkor 3D Packaging Platform Technologies Design rules and infrastructure for thinner, high density substrate technologies Advanced wafer thinning and handling systems Thinner die attach and die stacking processes High density and low loop wire bonding Pb free and environmentally "Green" material sets Flip chip plus wire bonding mixed technology stacking 37

38 Build-Up Substrates Sequential lamination is used to make highperformance, multi-layer PCBs for mounting high pin packages Build-up structure is used to make highdensity PCBs for mounting fine pin pitch packages closely together, High-density Design flexibility Layer reduction Cost Reduction Build-Up Substrates (Cont.) Source: Fujitsu 38

39 Green Packaging All the electrical and electronic equipment with lead cannot be produced in and shipped to the EU Countries after July 1, 2006 Seeks to increase recycling and recovery of waste equipment Green Packaging (Cont.) Elimination of certain elements and compounds Recycling of products at "end of life" 39

40 Green Packaging Banned Materials Lead (Pb) Lead mainly destroys body s nerve system, blood circulation and kidney function Cadmium (Cd) Cadmium-containing compound is a very harmful substance to human s health, which is mainly in kidney Green Packaging Banned Materials Mercury (Hg) When inorganic mercury disperses into water, then becomes harmful to human s brain Organic mercury inflicts relatively less harm to human body Hexavalent Chromium (Cr +6 ) Cr +6 can easily enter cell through cell membrane and can destroy DNA 40

41 Green Packaging Banned Materials PBB and PBDE Polybrominated Biphenyls (PBB) Polybrominated Diphenyl Ethers (PBDE) difficult to recycle plastics PBDE will produce cancer-incurring PBDD and PBDF in extrusion process Green Packaging Materials 41

42 Lead-free Solder Alloys in Japan The lead-free solder alloys used by some Japanese noticeable companies are Matsushita: SnAgBiIn, SnCu Sony: SnAgBiCu and Sn2Ag4Bi0.5Cu0.1Ge Toshiba: SnAgCu Hitachi: SnAgBi, SnAgCu, SnAgCuIn NEC: SnZn, SnCu, SnZnBi, SnAgCu These companies are all focusing on SnAgCu Solutions for the Elimination of Lead Solder Alloys Ternary Sn/Ag/Cu alloys contain 3-4% silver, % copper Sn/4.0Ag/0.5Cu, Sn/3.0Ag/0.5Cu alloy are adopted by Amkor Melting ranges of Sn/Ag/Cu alloys are around 220 C, while eutectic tin/lead are at 183 C Lead Finish pure Sn coating - deposition processes are available, cost efficient, and is compatible with soldering processes but reliability concerns about tin whiskers is a major issue nickel-palladium pre-plated leadframes - Japanese electronics industry has used a higher percentage of these packages 42

43 Solutions for the Elimination of Lead Flip Chip Sn/Ag/Cu or other similar alloy bump gold stud bump Anisotropic Conductive Film (ACF) Reliability Board assembly reflow processes are required to maintain peak temperatures of C which is as much as C higher than current processes Temperatures of Solders Solidus Temp: Above the solidus temperature, material consists of liquid phase and solid phase Liquidus Temp: The temperature above which the liquid phase is stable 43

44 Lead-Tin Binary Phase Diagram Lead Free Critical Issues Overall costs increase Impact of PCB finishes Impact of component finishes Tin whisker (short) risk Component reliability Rework Solder joint reliability Reliability tests Infrastructure 44

45 IC packaging Materials Ceramic Good heat conductivity Hermetic Expensive ( often more expensive than chip itself!) Metal Good heat conductivity Hermetic Electrical conductive Plastic Cheap Poor heat conductivity Properties of Materials (Ceramics) 45

46 Properties of Materials (Metal) Properties of Materials (Polymers) 46

47 Properties of Lead Frame Properties of Wirebonding Materials Pure Al, Au, and Cu are too soft mechanically to draw and handle Aluminum (Al + 1% Si, Al+0.5 1% Mg) wires (diameter > 25 μm) Gold (Au + ppm Be, Pd,..) wires (diameter ~ 25 μm) Copper (Cu + % Fe, Zn,..) wires (diameter > 25 μm) 47

48 Issues of Wirebonding Intermetallic compound Purple plague: AuAl 2 White plague: Au 5 Al 2 Kirkendahl voids 48